1=========================== 2ARM64 CPU Feature Registers 3=========================== 4 5Author: Suzuki K Poulose <suzuki.poulose@arm.com> 6 7 8This file describes the ABI for exporting the AArch64 CPU ID/feature 9registers to userspace. The availability of this ABI is advertised 10via the HWCAP_CPUID in HWCAPs. 11 121. Motivation 13------------- 14 15The ARM architecture defines a set of feature registers, which describe 16the capabilities of the CPU/system. Access to these system registers is 17restricted from EL0 and there is no reliable way for an application to 18extract this information to make better decisions at runtime. There is 19limited information available to the application via HWCAPs, however 20there are some issues with their usage. 21 22 a) Any change to the HWCAPs requires an update to userspace (e.g libc) 23 to detect the new changes, which can take a long time to appear in 24 distributions. Exposing the registers allows applications to get the 25 information without requiring updates to the toolchains. 26 27 b) Access to HWCAPs is sometimes limited (e.g prior to libc, or 28 when ld is initialised at startup time). 29 30 c) HWCAPs cannot represent non-boolean information effectively. The 31 architecture defines a canonical format for representing features 32 in the ID registers; this is well defined and is capable of 33 representing all valid architecture variations. 34 35 362. Requirements 37--------------- 38 39 a) Safety: 40 41 Applications should be able to use the information provided by the 42 infrastructure to run safely across the system. This has greater 43 implications on a system with heterogeneous CPUs. 44 The infrastructure exports a value that is safe across all the 45 available CPU on the system. 46 47 e.g, If at least one CPU doesn't implement CRC32 instructions, while 48 others do, we should report that the CRC32 is not implemented. 49 Otherwise an application could crash when scheduled on the CPU 50 which doesn't support CRC32. 51 52 b) Security: 53 54 Applications should only be able to receive information that is 55 relevant to the normal operation in userspace. Hence, some of the 56 fields are masked out(i.e, made invisible) and their values are set to 57 indicate the feature is 'not supported'. See Section 4 for the list 58 of visible features. Also, the kernel may manipulate the fields 59 based on what it supports. e.g, If FP is not supported by the 60 kernel, the values could indicate that the FP is not available 61 (even when the CPU provides it). 62 63 c) Implementation Defined Features 64 65 The infrastructure doesn't expose any register which is 66 IMPLEMENTATION DEFINED as per ARMv8-A Architecture. 67 68 d) CPU Identification: 69 70 MIDR_EL1 is exposed to help identify the processor. On a 71 heterogeneous system, this could be racy (just like getcpu()). The 72 process could be migrated to another CPU by the time it uses the 73 register value, unless the CPU affinity is set. Hence, there is no 74 guarantee that the value reflects the processor that it is 75 currently executing on. REVIDR and AIDR are not exposed due to this 76 constraint, as these registers only make sense in conjunction with 77 the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed 78 via sysfs at:: 79 80 /sys/devices/system/cpu/cpu$ID/regs/identification/ 81 \- midr_el1 82 \- revidr_el1 83 \- aidr_el1 84 853. Implementation 86-------------------- 87 88The infrastructure is built on the emulation of the 'MRS' instruction. 89Accessing a restricted system register from an application generates an 90exception and ends up in SIGILL being delivered to the process. 91The infrastructure hooks into the exception handler and emulates the 92operation if the source belongs to the supported system register space. 93 94The infrastructure emulates only the following system register space:: 95 96 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7 97 98(See Table C5-6 'System instruction encodings for non-Debug System 99register accesses' in ARMv8 ARM DDI 0487A.h, for the list of 100registers). 101 102The following rules are applied to the value returned by the 103infrastructure: 104 105 a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. 106 b) The value of a reserved field is populated with the reserved 107 value as defined by the architecture. 108 c) The value of a 'visible' field holds the system wide safe value 109 for the particular feature (except for MIDR_EL1, see section 4). 110 d) All other fields (i.e, invisible fields) are set to indicate 111 the feature is missing (as defined by the architecture). 112 1134. List of registers with visible features 114------------------------------------------- 115 116 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 117 118 +------------------------------+---------+---------+ 119 | Name | bits | visible | 120 +------------------------------+---------+---------+ 121 | RNDR | [63-60] | y | 122 +------------------------------+---------+---------+ 123 | TS | [55-52] | y | 124 +------------------------------+---------+---------+ 125 | FHM | [51-48] | y | 126 +------------------------------+---------+---------+ 127 | DP | [47-44] | y | 128 +------------------------------+---------+---------+ 129 | SM4 | [43-40] | y | 130 +------------------------------+---------+---------+ 131 | SM3 | [39-36] | y | 132 +------------------------------+---------+---------+ 133 | SHA3 | [35-32] | y | 134 +------------------------------+---------+---------+ 135 | RDM | [31-28] | y | 136 +------------------------------+---------+---------+ 137 | ATOMICS | [23-20] | y | 138 +------------------------------+---------+---------+ 139 | CRC32 | [19-16] | y | 140 +------------------------------+---------+---------+ 141 | SHA2 | [15-12] | y | 142 +------------------------------+---------+---------+ 143 | SHA1 | [11-8] | y | 144 +------------------------------+---------+---------+ 145 | AES | [7-4] | y | 146 +------------------------------+---------+---------+ 147 148 149 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 150 151 +------------------------------+---------+---------+ 152 | Name | bits | visible | 153 +------------------------------+---------+---------+ 154 | DIT | [51-48] | y | 155 +------------------------------+---------+---------+ 156 | MPAM | [43-40] | n | 157 +------------------------------+---------+---------+ 158 | SVE | [35-32] | y | 159 +------------------------------+---------+---------+ 160 | GIC | [27-24] | n | 161 +------------------------------+---------+---------+ 162 | AdvSIMD | [23-20] | y | 163 +------------------------------+---------+---------+ 164 | FP | [19-16] | y | 165 +------------------------------+---------+---------+ 166 | EL3 | [15-12] | n | 167 +------------------------------+---------+---------+ 168 | EL2 | [11-8] | n | 169 +------------------------------+---------+---------+ 170 | EL1 | [7-4] | n | 171 +------------------------------+---------+---------+ 172 | EL0 | [3-0] | n | 173 +------------------------------+---------+---------+ 174 175 176 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 177 178 +------------------------------+---------+---------+ 179 | Name | bits | visible | 180 +------------------------------+---------+---------+ 181 | SME | [27-24] | y | 182 +------------------------------+---------+---------+ 183 | MTE | [11-8] | y | 184 +------------------------------+---------+---------+ 185 | SSBS | [7-4] | y | 186 +------------------------------+---------+---------+ 187 | BT | [3-0] | y | 188 +------------------------------+---------+---------+ 189 190 191 4) MIDR_EL1 - Main ID Register 192 193 +------------------------------+---------+---------+ 194 | Name | bits | visible | 195 +------------------------------+---------+---------+ 196 | Implementer | [31-24] | y | 197 +------------------------------+---------+---------+ 198 | Variant | [23-20] | y | 199 +------------------------------+---------+---------+ 200 | Architecture | [19-16] | y | 201 +------------------------------+---------+---------+ 202 | PartNum | [15-4] | y | 203 +------------------------------+---------+---------+ 204 | Revision | [3-0] | y | 205 +------------------------------+---------+---------+ 206 207 NOTE: The 'visible' fields of MIDR_EL1 will contain the value 208 as available on the CPU where it is fetched and is not a system 209 wide safe value. 210 211 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 212 213 +------------------------------+---------+---------+ 214 | Name | bits | visible | 215 +------------------------------+---------+---------+ 216 | I8MM | [55-52] | y | 217 +------------------------------+---------+---------+ 218 | DGH | [51-48] | y | 219 +------------------------------+---------+---------+ 220 | BF16 | [47-44] | y | 221 +------------------------------+---------+---------+ 222 | SB | [39-36] | y | 223 +------------------------------+---------+---------+ 224 | FRINTTS | [35-32] | y | 225 +------------------------------+---------+---------+ 226 | GPI | [31-28] | y | 227 +------------------------------+---------+---------+ 228 | GPA | [27-24] | y | 229 +------------------------------+---------+---------+ 230 | LRCPC | [23-20] | y | 231 +------------------------------+---------+---------+ 232 | FCMA | [19-16] | y | 233 +------------------------------+---------+---------+ 234 | JSCVT | [15-12] | y | 235 +------------------------------+---------+---------+ 236 | API | [11-8] | y | 237 +------------------------------+---------+---------+ 238 | APA | [7-4] | y | 239 +------------------------------+---------+---------+ 240 | DPB | [3-0] | y | 241 +------------------------------+---------+---------+ 242 243 6) ID_AA64MMFR0_EL1 - Memory model feature register 0 244 245 +------------------------------+---------+---------+ 246 | Name | bits | visible | 247 +------------------------------+---------+---------+ 248 | ECV | [63-60] | y | 249 +------------------------------+---------+---------+ 250 251 7) ID_AA64MMFR2_EL1 - Memory model feature register 2 252 253 +------------------------------+---------+---------+ 254 | Name | bits | visible | 255 +------------------------------+---------+---------+ 256 | AT | [35-32] | y | 257 +------------------------------+---------+---------+ 258 259 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0 260 261 +------------------------------+---------+---------+ 262 | Name | bits | visible | 263 +------------------------------+---------+---------+ 264 | F64MM | [59-56] | y | 265 +------------------------------+---------+---------+ 266 | F32MM | [55-52] | y | 267 +------------------------------+---------+---------+ 268 | I8MM | [47-44] | y | 269 +------------------------------+---------+---------+ 270 | SM4 | [43-40] | y | 271 +------------------------------+---------+---------+ 272 | SHA3 | [35-32] | y | 273 +------------------------------+---------+---------+ 274 | B16B16 | [27-24] | y | 275 +------------------------------+---------+---------+ 276 | BF16 | [23-20] | y | 277 +------------------------------+---------+---------+ 278 | BitPerm | [19-16] | y | 279 +------------------------------+---------+---------+ 280 | AES | [7-4] | y | 281 +------------------------------+---------+---------+ 282 | SVEVer | [3-0] | y | 283 +------------------------------+---------+---------+ 284 285 8) ID_AA64MMFR1_EL1 - Memory model feature register 1 286 287 +------------------------------+---------+---------+ 288 | Name | bits | visible | 289 +------------------------------+---------+---------+ 290 | AFP | [47-44] | y | 291 +------------------------------+---------+---------+ 292 293 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2 294 295 +------------------------------+---------+---------+ 296 | Name | bits | visible | 297 +------------------------------+---------+---------+ 298 | CSSC | [55-52] | y | 299 +------------------------------+---------+---------+ 300 | RPRFM | [51-48] | y | 301 +------------------------------+---------+---------+ 302 | BC | [23-20] | y | 303 +------------------------------+---------+---------+ 304 | MOPS | [19-16] | y | 305 +------------------------------+---------+---------+ 306 | APA3 | [15-12] | y | 307 +------------------------------+---------+---------+ 308 | GPA3 | [11-8] | y | 309 +------------------------------+---------+---------+ 310 | RPRES | [7-4] | y | 311 +------------------------------+---------+---------+ 312 | WFXT | [3-0] | y | 313 +------------------------------+---------+---------+ 314 315 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 316 317 +------------------------------+---------+---------+ 318 | Name | bits | visible | 319 +------------------------------+---------+---------+ 320 | FPDP | [11-8] | y | 321 +------------------------------+---------+---------+ 322 323 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1 324 325 +------------------------------+---------+---------+ 326 | Name | bits | visible | 327 +------------------------------+---------+---------+ 328 | SIMDFMAC | [31-28] | y | 329 +------------------------------+---------+---------+ 330 | SIMDSP | [19-16] | y | 331 +------------------------------+---------+---------+ 332 | SIMDInt | [15-12] | y | 333 +------------------------------+---------+---------+ 334 | SIMDLS | [11-8] | y | 335 +------------------------------+---------+---------+ 336 337 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 338 339 +------------------------------+---------+---------+ 340 | Name | bits | visible | 341 +------------------------------+---------+---------+ 342 | CRC32 | [19-16] | y | 343 +------------------------------+---------+---------+ 344 | SHA2 | [15-12] | y | 345 +------------------------------+---------+---------+ 346 | SHA1 | [11-8] | y | 347 +------------------------------+---------+---------+ 348 | AES | [7-4] | y | 349 +------------------------------+---------+---------+ 350 351 352Appendix I: Example 353------------------- 354 355:: 356 357 /* 358 * Sample program to demonstrate the MRS emulation ABI. 359 * 360 * Copyright (C) 2015-2016, ARM Ltd 361 * 362 * Author: Suzuki K Poulose <suzuki.poulose@arm.com> 363 * 364 * This program is free software; you can redistribute it and/or modify 365 * it under the terms of the GNU General Public License version 2 as 366 * published by the Free Software Foundation. 367 * 368 * This program is distributed in the hope that it will be useful, 369 * but WITHOUT ANY WARRANTY; without even the implied warranty of 370 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 371 * GNU General Public License for more details. 372 * This program is free software; you can redistribute it and/or modify 373 * it under the terms of the GNU General Public License version 2 as 374 * published by the Free Software Foundation. 375 * 376 * This program is distributed in the hope that it will be useful, 377 * but WITHOUT ANY WARRANTY; without even the implied warranty of 378 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 379 * GNU General Public License for more details. 380 */ 381 382 #include <asm/hwcap.h> 383 #include <stdio.h> 384 #include <sys/auxv.h> 385 386 #define get_cpu_ftr(id) ({ \ 387 unsigned long __val; \ 388 asm("mrs %0, "#id : "=r" (__val)); \ 389 printf("%-20s: 0x%016lx\n", #id, __val); \ 390 }) 391 392 int main(void) 393 { 394 395 if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { 396 fputs("CPUID registers unavailable\n", stderr); 397 return 1; 398 } 399 400 get_cpu_ftr(ID_AA64ISAR0_EL1); 401 get_cpu_ftr(ID_AA64ISAR1_EL1); 402 get_cpu_ftr(ID_AA64MMFR0_EL1); 403 get_cpu_ftr(ID_AA64MMFR1_EL1); 404 get_cpu_ftr(ID_AA64PFR0_EL1); 405 get_cpu_ftr(ID_AA64PFR1_EL1); 406 get_cpu_ftr(ID_AA64DFR0_EL1); 407 get_cpu_ftr(ID_AA64DFR1_EL1); 408 409 get_cpu_ftr(MIDR_EL1); 410 get_cpu_ftr(MPIDR_EL1); 411 get_cpu_ftr(REVIDR_EL1); 412 413 #if 0 414 /* Unexposed register access causes SIGILL */ 415 get_cpu_ftr(ID_MMFR0_EL1); 416 #endif 417 418 return 0; 419 } 420