1===================================================== 2Freescale i.MX8 DDR Performance Monitoring Unit (PMU) 3===================================================== 4 5There are no performance counters inside the DRAM controller, so performance 6signals are brought out to the edge of the controller where a set of 4 x 32 bit 7counters is implemented. This is controlled by the CSV modes programed in counter 8control register which causes a large number of PERF signals to be generated. 9 10Selection of the value for each counter is done via the config registers. There 11is one register for each counter. Counter 0 is special in that it always counts 12“time” and when expired causes a lock on itself and the other counters and an 13interrupt is raised. If any other counter overflows, it continues counting, and 14no interrupt is raised. 15 16The "format" directory describes format of the config (event ID) and config1 17(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ 18devices/imx8_ddr0/format/. The "events" directory describes the events types 19hardware supported that can be used with perf tool, see /sys/bus/event_source/ 20devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented 21in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. 22 23 .. code-block:: bash 24 25 perf stat -a -e imx8_ddr0/cycles/ cmd 26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd 27 28AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) 29to count reading or writing matches filter setting. Filter setting is various 30from different DRAM controller implementations, which is distinguished by quirks 31in the driver. You also can dump info from userspace, filter in "caps" directory 32indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates 33whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and 34value 1 for supported. 35 36* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0). 37 Filter is defined with two configuration parts: 38 --AXI_ID defines AxID matching value. 39 --AXI_MASKING defines which bits of AxID are meaningful for the matching. 40 41 - 0: corresponding bit is masked. 42 - 1: corresponding bit is not masked, i.e. used to do the matching. 43 44 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. 45 When non-masked bits are matching corresponding AXI_ID bits then counter is 46 incremented. Perf counter is incremented if:: 47 48 AxID && AXI_MASKING == AXI_ID && AXI_MASKING 49 50 This filter doesn't support filter different AXI ID for axid-read and axid-write 51 event at the same time as this filter is shared between counters. 52 53 .. code-block:: bash 54 55 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd 56 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd 57 58 .. note:: 59 60 axi_mask is inverted in userspace(i.e. set bits are bits to mask), and 61 it will be reverted in driver automatically. so that the user can just specify 62 axi_id to monitor a specific id, rather than having to specify axi_mask. 63 64 .. code-block:: bash 65 66 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 67 68* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1). 69 This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits 70 counting the number of bytes (as opposed to the number of bursts) from DDR 71 read and write transactions concurrently with another set of data counters. 72