1====================================================== 2HiSilicon SoC uncore Performance Monitoring Unit (PMU) 3====================================================== 4 5The HiSilicon SoC chip includes various independent system device PMUs 6such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are 7independent and have hardware logic to gather statistics and performance 8information. 9 10The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster 11(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is 12called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has 13two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. 14 15HiSilicon SoC uncore PMU driver 16------------------------------- 17 18Each device PMU has separate registers for event counting, control and 19interrupt, and the PMU driver shall register perf PMU drivers like L3C, 20HHA and DDRC etc. The available events and configuration options shall 21be described in the sysfs, see: 22 23/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or 24/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>. 25The "perf list" command shall list the available events from sysfs. 26 27Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU 28name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>. 29where "sccl-id" is the identifier of the SCCL and "index-id" is the index of 30module. 31 32e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in 33SCCL ID #3. 34 35e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in 36SCCL ID #1. 37 38The driver also provides a "cpumask" sysfs attribute, which shows the CPU core 39ID used to count the uncore PMU event. 40 41Example usage of perf:: 42 43 $# perf list 44 hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] 45 ------------------------------------------ 46 hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] 47 ------------------------------------------ 48 hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] 49 ------------------------------------------ 50 hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] 51 ------------------------------------------ 52 53 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 54 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 55 56For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same 57as PMU v1, but some new functions are added to the hardware. 58 591. L3C PMU supports filtering by core/thread within the cluster which can be 60specified as a bitmap:: 61 62 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5 63 64This will only count the operations from core/thread 0 and 1 in this cluster. 65 662. Tracetag allow the user to chose to count only read, write or atomic 67operations via the tt_req parameeter in perf. The default value counts all 68operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101 69represents write operations, 3'b110 represents atomic store operations and 703'b111 represents atomic non-store operations, other values are reserved:: 71 72 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5 73 74This will only count the read operations in this cluster. 75 763. Datasrc allows the user to check where the data comes from. It is 5 bits. 77Some important codes are as follows: 78 79- 5'b00001: comes from L3C in this die; 80- 5'b01000: comes from L3C in the cross-die; 81- 5'b01001: comes from L3C which is in another socket; 82- 5'b01110: comes from the local DDR; 83- 5'b01111: comes from the cross-die DDR; 84- 5'b10000: comes from cross-socket DDR; 85 86etc, it is mainly helpful to find that the data source is nearest from the CPU 87cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be 88configured in perf command:: 89 90 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/, 91 hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5 92 934. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die 94contains several Compute Clusters (CCLs). The I/O dies are called Super I/O 95clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the 96SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit 97CCL/ICL-ID. For I/O die, the ICL-ID is followed by: 98 99- 5'b00000: I/O_MGMT_ICL; 100- 5'b00001: Network_ICL; 101- 5'b00011: HAC_ICL; 102- 5'b10000: PCIe_ICL; 103 1045. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request 105uring channel. It is 2 bits. Some important codes are as follows: 106 107- 2'b11: count the events which sent to the uring_ext (MATA) channel; 108- 2'b01: is the same as 2'b11; 109- 2'b10: count the events which sent to the uring (non-MATA) channel; 110- 2'b00: default value, count the events which sent to the both uring and 111 uring_ext channel; 112 113Users could configure IDs to count data come from specific CCL/ICL, by setting 114srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting 115tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not 116check the bit when matching against the srcid_cmd/tgtid_cmd. 117 118If all of these options are disabled, it can works by the default value that 119doesn't distinguish the filter condition and ID information and will return 120the total counter values in the PMU counters. 121 122The current driver does not support sampling. So "perf record" is unsupported. 123Also attach to a task is unsupported as the events are all uncore. 124 125Note: Please contact the maintainer for a complete list of events supported for 126the PMU devices in the SoC and its information if needed. 127