1====================================================== 2HiSilicon SoC uncore Performance Monitoring Unit (PMU) 3====================================================== 4 5The HiSilicon SoC chip includes various independent system device PMUs 6such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are 7independent and have hardware logic to gather statistics and performance 8information. 9 10The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster 11(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is 12called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has 13two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. 14 15HiSilicon SoC uncore PMU driver 16------------------------------- 17 18Each device PMU has separate registers for event counting, control and 19interrupt, and the PMU driver shall register perf PMU drivers like L3C, 20HHA and DDRC etc. The available events and configuration options shall 21be described in the sysfs, see:: 22 23/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}> 24 25The "perf list" command shall list the available events from sysfs. 26 27Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU 28name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>. 29where "sccl-id" is the identifier of the SCCL and "index-id" is the index of 30module. 31 32e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in 33SCCL ID #3. 34 35e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in 36SCCL ID #1. 37 38The driver also provides a "cpumask" sysfs attribute, which shows the CPU core 39ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is 40also provided to show the CPUs associated with this PMU. The "cpumask" indicates 41the CPUs to open the events, usually as a hint for userspaces tools like perf. 42It only contains one associated CPU from the "associated_cpus". 43 44Example usage of perf:: 45 46 $# perf list 47 hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] 48 ------------------------------------------ 49 hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] 50 ------------------------------------------ 51 hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] 52 ------------------------------------------ 53 hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] 54 ------------------------------------------ 55 56 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 57 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 58 59For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same 60as PMU v1, but some new functions are added to the hardware. 61 621. L3C PMU supports filtering by core/thread within the cluster which can be 63specified as a bitmap:: 64 65 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5 66 67This will only count the operations from core/thread 0 and 1 in this cluster. 68 69User should not use tt_core_deprecated to specify the core/thread filtering. 70This option is provided for backward compatiblility and only support 8bit 71which may not cover all the core/thread sharing L3C. 72 732. Tracetag allow the user to chose to count only read, write or atomic 74operations via the tt_req parameeter in perf. The default value counts all 75operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101 76represents write operations, 3'b110 represents atomic store operations and 773'b111 represents atomic non-store operations, other values are reserved:: 78 79 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5 80 81This will only count the read operations in this cluster. 82 833. Datasrc allows the user to check where the data comes from. It is 5 bits. 84Some important codes are as follows: 85 86- 5'b00001: comes from L3C in this die; 87- 5'b01000: comes from L3C in the cross-die; 88- 5'b01001: comes from L3C which is in another socket; 89- 5'b01110: comes from the local DDR; 90- 5'b01111: comes from the cross-die DDR; 91- 5'b10000: comes from cross-socket DDR; 92 93etc, it is mainly helpful to find that the data source is nearest from the CPU 94cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be 95configured in perf command:: 96 97 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/, 98 hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5 99 1004. Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die 101contains several Compute Clusters (CCLs). The I/O dies are called Super I/O 102clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the 103SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit 104CCL/ICL-ID. For I/O die, the ICL-ID is followed by: 105 106- 5'b00000: I/O_MGMT_ICL; 107- 5'b00001: Network_ICL; 108- 5'b00011: HAC_ICL; 109- 5'b10000: PCIe_ICL; 110 1115. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request 112uring channel. It is 2 bits. Some important codes are as follows: 113 114- 2'b11: count the events which sent to the uring_ext (MATA) channel; 115- 2'b01: is the same as 2'b11; 116- 2'b10: count the events which sent to the uring (non-MATA) channel; 117- 2'b00: default value, count the events which sent to both uring and 118 uring_ext channels; 119 1206. ch: NoC PMU supports filtering the event counts of certain transaction 121channel with this option. The current supported channels are as follows: 122 123- 3'b010: Request channel 124- 3'b100: Snoop channel 125- 3'b110: Response channel 126- 3'b111: Data channel 127 1287. tt_en: NoC PMU supports counting only transactions that have tracetag set 129if this option is set. See the 2nd list for more information about tracetag. 130 131For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are 132further divided into parts for finer granularity of tracing, each part has its 133own dedicated PMU, and all such PMUs together cover the monitoring job of events 134on particular uncore device. Such PMUs are described in sysfs with name format 135slightly changed:: 136 137/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}> 138 139Z is the sub-id, indicating different PMUs for part of hardware device. 140 141Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU 142provides ``ext`` option to allow exploration of even finer granual statistics 143of L3C PMU. L3C PMU driver uses that as hint of termination when delivering 144perf command to hardware: 145 146- ext=0: Default, could be used with event names. 147- ext=1 and ext=2: Must be used with event codes, event names are not supported. 148 149An example of perf command could be:: 150 151 $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5 152 153or:: 154 155 $# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5 156 157As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1 158pipe0. 159 160First command locates the first part of L3C since ``ext=0`` is implied by 161default. Second command issues the counting on another part of L3C with the 162event ``0x1``. 163 164Users could configure IDs to count data come from specific CCL/ICL, by setting 165srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting 166tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not 167check the bit when matching against the srcid_cmd/tgtid_cmd. 168 169If all of these options are disabled, it can works by the default value that 170doesn't distinguish the filter condition and ID information and will return 171the total counter values in the PMU counters. 172 173The current driver does not support sampling. So "perf record" is unsupported. 174Also attach to a task is unsupported as the events are all uncore. 175 176Note: Please contact the maintainer for a complete list of events supported for 177the PMU devices in the SoC and its information if needed. 178