1What: /sys/bus/platform/devices/dfl-port.0/id 2Date: June 2018 3KernelVersion: 4.19 4Contact: Wu Hao <hao.wu@intel.com> 5Description: Read-only. It returns id of this port. One DFL FPGA device 6 may have more than one port. Userspace could use this id to 7 distinguish different ports under same FPGA device. 8 9What: /sys/bus/platform/devices/dfl-port.0/afu_id 10Date: June 2018 11KernelVersion: 4.19 12Contact: Wu Hao <hao.wu@intel.com> 13Description: Read-only. User can program different PR bitstreams to FPGA 14 Accelerator Function Unit (AFU) for different functions. It 15 returns uuid which could be used to identify which PR bitstream 16 is programmed in this AFU. 17 18What: /sys/bus/platform/devices/dfl-port.0/power_state 19Date: August 2019 20KernelVersion: 5.4 21Contact: Wu Hao <hao.wu@intel.com> 22Description: Read-only. It reports the APx (AFU Power) state, different APx 23 means different throttling level. When reading this file, it 24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6. 25 26What: /sys/bus/platform/devices/dfl-port.0/ap1_event 27Date: August 2019 28KernelVersion: 5.4 29Contact: Wu Hao <hao.wu@intel.com> 30Description: Read-write. Read this file for AP1 (AFU Power State 1) event. 31 It's used to indicate transient AP1 state. Write 1 to this 32 file to clear AP1 event. 33 34What: /sys/bus/platform/devices/dfl-port.0/ap2_event 35Date: August 2019 36KernelVersion: 5.4 37Contact: Wu Hao <hao.wu@intel.com> 38Description: Read-write. Read this file for AP2 (AFU Power State 2) event. 39 It's used to indicate transient AP2 state. Write 1 to this 40 file to clear AP2 event. 41 42What: /sys/bus/platform/devices/dfl-port.0/ltr 43Date: August 2019 44KernelVersion: 5.4 45Contact: Wu Hao <hao.wu@intel.com> 46Description: Read-write. Read or set AFU latency tolerance reporting value. 47 Set ltr to 1 if the AFU can tolerate latency >= 40us or set it 48 to 0 if it is latency sensitive. 49