10a27ff24SKang LuweiWhat: /sys/bus/platform/devices/dfl-fme.0/ports_num 20a27ff24SKang LuweiDate: June 2018 30a27ff24SKang LuweiKernelVersion: 4.19 40a27ff24SKang LuweiContact: Wu Hao <hao.wu@intel.com> 50a27ff24SKang LuweiDescription: Read-only. One DFL FPGA device may have more than 1 60a27ff24SKang Luwei port/Accelerator Function Unit (AFU). It returns the 70a27ff24SKang Luwei number of ports on the FPGA device when read it. 80a27ff24SKang Luwei 90a27ff24SKang LuweiWhat: /sys/bus/platform/devices/dfl-fme.0/bitstream_id 100a27ff24SKang LuweiDate: June 2018 110a27ff24SKang LuweiKernelVersion: 4.19 120a27ff24SKang LuweiContact: Wu Hao <hao.wu@intel.com> 130a27ff24SKang LuweiDescription: Read-only. It returns Bitstream (static FPGA region) 140a27ff24SKang Luwei identifier number, which includes the detailed version 150a27ff24SKang Luwei and other information of this static FPGA region. 160a27ff24SKang Luwei 170a27ff24SKang LuweiWhat: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata 180a27ff24SKang LuweiDate: June 2018 190a27ff24SKang LuweiKernelVersion: 4.19 200a27ff24SKang LuweiContact: Wu Hao <hao.wu@intel.com> 210a27ff24SKang LuweiDescription: Read-only. It returns Bitstream (static FPGA region) meta 220a27ff24SKang Luwei data, which includes the synthesis date, seed and other 230a27ff24SKang Luwei information of this static FPGA region. 24*52eb6d31SWu Hao 25*52eb6d31SWu HaoWhat: /sys/bus/platform/devices/dfl-fme.0/cache_size 26*52eb6d31SWu HaoDate: August 2019 27*52eb6d31SWu HaoKernelVersion: 5.4 28*52eb6d31SWu HaoContact: Wu Hao <hao.wu@intel.com> 29*52eb6d31SWu HaoDescription: Read-only. It returns cache size of this FPGA device. 30*52eb6d31SWu Hao 31*52eb6d31SWu HaoWhat: /sys/bus/platform/devices/dfl-fme.0/fabric_version 32*52eb6d31SWu HaoDate: August 2019 33*52eb6d31SWu HaoKernelVersion: 5.4 34*52eb6d31SWu HaoContact: Wu Hao <hao.wu@intel.com> 35*52eb6d31SWu HaoDescription: Read-only. It returns fabric version of this FPGA device. 36*52eb6d31SWu Hao Userspace applications need this information to select 37*52eb6d31SWu Hao best data channels per different fabric design. 38*52eb6d31SWu Hao 39*52eb6d31SWu HaoWhat: /sys/bus/platform/devices/dfl-fme.0/socket_id 40*52eb6d31SWu HaoDate: August 2019 41*52eb6d31SWu HaoKernelVersion: 5.4 42*52eb6d31SWu HaoContact: Wu Hao <hao.wu@intel.com> 43*52eb6d31SWu HaoDescription: Read-only. It returns socket_id to indicate which socket 44*52eb6d31SWu Hao this FPGA belongs to, only valid for integrated solution. 45*52eb6d31SWu Hao User only needs this information, in case standard numa node 46*52eb6d31SWu Hao can't provide correct information. 47