1What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status 2Date: February 2023 3KernelVersion: 6.4 4Contact: Nava kishore Manne <nava.kishore.manne@amd.com> 5Description: (RO) Read fpga status. 6 Read returns a hexadecimal value that tells the current status 7 of the FPGA device. Each bit position in the status value is 8 described Below(see ug570 chapter 9). 9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration 10 11 ====================== ============================================== 12 BIT(0) 0: No CRC error 13 1: CRC error 14 15 BIT(1) 0: Decryptor security not set 16 1: Decryptor security set 17 18 BIT(2) 0: MMCMs/PLLs are not locked 19 1: MMCMs/PLLs are locked 20 21 BIT(3) 0: DCI not matched 22 1: DCI matched 23 24 BIT(4) 0: Start-up sequence has not finished 25 1: Start-up sequence has finished 26 27 BIT(5) 0: All I/Os are placed in High-Z state 28 1: All I/Os behave as configured 29 30 BIT(6) 0: Flip-flops and block RAM are write disabled 31 1: Flip-flops and block RAM are write enabled 32 33 BIT(7) 0: GHIGH_B_STATUS asserted 34 1: GHIGH_B_STATUS deasserted 35 36 BIT(8) to BIT(10) Status of the mode pins 37 38 BIT(11) 0: Initialization has not finished 39 1: Initialization finished 40 41 BIT(12) Value on INIT_B_PIN pin 42 43 BIT(13) 0: Signal not released 44 1: Signal released 45 46 BIT(14) Value on DONE_PIN pin. 47 48 BIT(15) 0: No IDCODE_ERROR 49 1: IDCODE_ERROR 50 51 BIT(16) 0: No SECURITY_ERROR 52 1: SECURITY_ERROR 53 54 BIT(17) System Monitor over-temperature if set 55 56 BIT(18) to BIT(20) Start-up state machine (0 to 7) 57 Phase 0 = 000 58 Phase 1 = 001 59 Phase 2 = 011 60 Phase 3 = 010 61 Phase 4 = 110 62 Phase 5 = 111 63 Phase 6 = 101 64 Phase 7 = 100 65 66 BIT(25) to BIT(26) Indicates the detected bus width 67 00 = x1 68 01 = x8 69 10 = x16 70 11 = x32 71 ====================== ============================================== 72 73 The other bits are reserved. 74