1What: /sys/class/habanalabs/hl<n>/armcp_kernel_ver 2Date: Jan 2019 3KernelVersion: 5.1 4Contact: ogabbay@kernel.org 5Description: Version of the Linux kernel running on the device's CPU. 6 Will be DEPRECATED in Linux kernel version 5.10, and be 7 replaced with cpucp_kernel_ver 8 9What: /sys/class/habanalabs/hl<n>/armcp_ver 10Date: Jan 2019 11KernelVersion: 5.1 12Contact: ogabbay@kernel.org 13Description: Version of the application running on the device's CPU 14 Will be DEPRECATED in Linux kernel version 5.10, and be 15 replaced with cpucp_ver 16 17What: /sys/class/habanalabs/hl<n>/clk_max_freq_mhz 18Date: Jun 2019 19KernelVersion: not yet upstreamed 20Contact: ogabbay@kernel.org 21Description: Allows the user to set the maximum clock frequency, in MHz. 22 The device clock might be set to lower value than the maximum. 23 The user should read the clk_cur_freq_mhz to see the actual 24 frequency value of the device clock. This property is valid 25 only for the Gaudi ASIC family 26 27What: /sys/class/habanalabs/hl<n>/clk_cur_freq_mhz 28Date: Jun 2019 29KernelVersion: not yet upstreamed 30Contact: ogabbay@kernel.org 31Description: Displays the current frequency, in MHz, of the device clock. 32 This property is valid only for the Gaudi ASIC family 33 34What: /sys/class/habanalabs/hl<n>/cpld_ver 35Date: Jan 2019 36KernelVersion: 5.1 37Contact: ogabbay@kernel.org 38Description: Version of the Device's CPLD F/W 39 40What: /sys/class/habanalabs/hl<n>/cpucp_kernel_ver 41Date: Oct 2020 42KernelVersion: 5.10 43Contact: ogabbay@kernel.org 44Description: Version of the Linux kernel running on the device's CPU 45 46What: /sys/class/habanalabs/hl<n>/cpucp_ver 47Date: Oct 2020 48KernelVersion: 5.10 49Contact: ogabbay@kernel.org 50Description: Version of the application running on the device's CPU 51 52What: /sys/class/habanalabs/hl<n>/device_type 53Date: Jan 2019 54KernelVersion: 5.1 55Contact: ogabbay@kernel.org 56Description: Displays the code name of the device according to its type. 57 The supported values are: "GOYA" 58 59What: /sys/class/habanalabs/hl<n>/eeprom 60Date: Jan 2019 61KernelVersion: 5.1 62Contact: ogabbay@kernel.org 63Description: A binary file attribute that contains the contents of the 64 on-board EEPROM 65 66What: /sys/class/habanalabs/hl<n>/fuse_ver 67Date: Jan 2019 68KernelVersion: 5.1 69Contact: ogabbay@kernel.org 70Description: Displays the device's version from the eFuse 71 72What: /sys/class/habanalabs/hl<n>/fw_os_ver 73Date: Dec 2021 74KernelVersion: 5.18 75Contact: ogabbay@kernel.org 76Description: Version of the firmware OS running on the device's CPU 77 78What: /sys/class/habanalabs/hl<n>/hard_reset 79Date: Jan 2019 80KernelVersion: 5.1 81Contact: ogabbay@kernel.org 82Description: Interface to trigger a hard-reset operation for the device. 83 Hard-reset will reset ALL internal components of the device 84 except for the PCI interface and the internal PLLs 85 86What: /sys/class/habanalabs/hl<n>/hard_reset_cnt 87Date: Jan 2019 88KernelVersion: 5.1 89Contact: ogabbay@kernel.org 90Description: Displays how many times the device have undergone a hard-reset 91 operation since the driver was loaded 92 93What: /sys/class/habanalabs/hl<n>/high_pll 94Date: Jan 2019 95KernelVersion: 5.1 96Contact: ogabbay@kernel.org 97Description: Allows the user to set the maximum clock frequency for MME, TPC 98 and IC when the power management profile is set to "automatic". 99 This property is valid only for the Goya ASIC family 100 101What: /sys/class/habanalabs/hl<n>/ic_clk 102Date: Jan 2019 103KernelVersion: 5.1 104Contact: ogabbay@kernel.org 105Description: Allows the user to set the maximum clock frequency, in Hz, of 106 the Interconnect fabric. Writes to this parameter affect the 107 device only when the power management profile is set to "manual" 108 mode. The device IC clock might be set to lower value than the 109 maximum. The user should read the ic_clk_curr to see the actual 110 frequency value of the IC. This property is valid only for the 111 Goya ASIC family 112 113What: /sys/class/habanalabs/hl<n>/ic_clk_curr 114Date: Jan 2019 115KernelVersion: 5.1 116Contact: ogabbay@kernel.org 117Description: Displays the current clock frequency, in Hz, of the Interconnect 118 fabric. This property is valid only for the Goya ASIC family 119 120What: /sys/class/habanalabs/hl<n>/infineon_ver 121Date: Jan 2019 122KernelVersion: 5.1 123Contact: ogabbay@kernel.org 124Description: Version of the Device's power supply F/W code. Relevant only to GOYA and GAUDI 125 126What: /sys/class/habanalabs/hl<n>/max_power 127Date: Jan 2019 128KernelVersion: 5.1 129Contact: ogabbay@kernel.org 130Description: Allows the user to set the maximum power consumption of the 131 device in milliwatts. 132 133What: /sys/class/habanalabs/hl<n>/mme_clk 134Date: Jan 2019 135KernelVersion: 5.1 136Contact: ogabbay@kernel.org 137Description: Allows the user to set the maximum clock frequency, in Hz, of 138 the MME compute engine. Writes to this parameter affect the 139 device only when the power management profile is set to "manual" 140 mode. The device MME clock might be set to lower value than the 141 maximum. The user should read the mme_clk_curr to see the actual 142 frequency value of the MME. This property is valid only for the 143 Goya ASIC family 144 145What: /sys/class/habanalabs/hl<n>/mme_clk_curr 146Date: Jan 2019 147KernelVersion: 5.1 148Contact: ogabbay@kernel.org 149Description: Displays the current clock frequency, in Hz, of the MME compute 150 engine. This property is valid only for the Goya ASIC family 151 152What: /sys/class/habanalabs/hl<n>/pci_addr 153Date: Jan 2019 154KernelVersion: 5.1 155Contact: ogabbay@kernel.org 156Description: Displays the PCI address of the device. This is needed so the 157 user would be able to open a device based on its PCI address 158 159What: /sys/class/habanalabs/hl<n>/pm_mng_profile 160Date: Jan 2019 161KernelVersion: 5.1 162Contact: ogabbay@kernel.org 163Description: Power management profile. Values are "auto", "manual". In "auto" 164 mode, the driver will set the maximum clock frequency to a high 165 value when a user-space process opens the device's file (unless 166 it was already opened by another process). The driver will set 167 the max clock frequency to a low value when there are no user 168 processes that are opened on the device's file. In "manual" 169 mode, the user sets the maximum clock frequency by writing to 170 ic_clk, mme_clk and tpc_clk. This property is valid only for 171 the Goya ASIC family 172 173What: /sys/class/habanalabs/hl<n>/preboot_btl_ver 174Date: Jan 2019 175KernelVersion: 5.1 176Contact: ogabbay@kernel.org 177Description: Version of the device's preboot F/W code 178 179What: /sys/class/habanalabs/hl<n>/soft_reset 180Date: Jan 2019 181KernelVersion: 5.1 182Contact: ogabbay@kernel.org 183Description: Interface to trigger a soft-reset operation for the device. 184 Soft-reset will reset only the compute and DMA engines of the 185 device 186 187What: /sys/class/habanalabs/hl<n>/soft_reset_cnt 188Date: Jan 2019 189KernelVersion: 5.1 190Contact: ogabbay@kernel.org 191Description: Displays how many times the device have undergone a soft-reset 192 operation since the driver was loaded 193 194What: /sys/class/habanalabs/hl<n>/status 195Date: Jan 2019 196KernelVersion: 5.1 197Contact: ogabbay@kernel.org 198Description: Status of the card: "Operational", "Malfunction", "In reset". 199 200What: /sys/class/habanalabs/hl<n>/thermal_ver 201Date: Jan 2019 202KernelVersion: 5.1 203Contact: ogabbay@kernel.org 204Description: Version of the Device's thermal daemon 205 206What: /sys/class/habanalabs/hl<n>/tpc_clk 207Date: Jan 2019 208KernelVersion: 5.1 209Contact: ogabbay@kernel.org 210Description: Allows the user to set the maximum clock frequency, in Hz, of 211 the TPC compute engines. Writes to this parameter affect the 212 device only when the power management profile is set to "manual" 213 mode. The device TPC clock might be set to lower value than the 214 maximum. The user should read the tpc_clk_curr to see the actual 215 frequency value of the TPC. This property is valid only for 216 Goya ASIC family 217 218What: /sys/class/habanalabs/hl<n>/tpc_clk_curr 219Date: Jan 2019 220KernelVersion: 5.1 221Contact: ogabbay@kernel.org 222Description: Displays the current clock frequency, in Hz, of the TPC compute 223 engines. This property is valid only for the Goya ASIC family 224 225What: /sys/class/habanalabs/hl<n>/uboot_ver 226Date: Jan 2019 227KernelVersion: 5.1 228Contact: ogabbay@kernel.org 229Description: Version of the u-boot running on the device's CPU 230 231What: /sys/class/habanalabs/hl<n>/vrm_ver 232Date: Jan 2022 233KernelVersion: not yet upstreamed 234Contact: ogabbay@kernel.org 235Description: Version of the Device's Voltage Regulator Monitor F/W code. N/A to GOYA and GAUDI 236