1What: /sys/class/habanalabs/hl<n>/armcp_kernel_ver 2Date: Jan 2019 3KernelVersion: 5.1 4Contact: oded.gabbay@gmail.com 5Description: Version of the Linux kernel running on the device's CPU 6 7What: /sys/class/habanalabs/hl<n>/armcp_ver 8Date: Jan 2019 9KernelVersion: 5.1 10Contact: oded.gabbay@gmail.com 11Description: Version of the application running on the device's CPU 12 13What: /sys/class/habanalabs/hl<n>/clk_max_freq_mhz 14Date: Jun 2019 15KernelVersion: not yet upstreamed 16Contact: oded.gabbay@gmail.com 17Description: Allows the user to set the maximum clock frequency, in MHz. 18 The device clock might be set to lower value than the maximum. 19 The user should read the clk_cur_freq_mhz to see the actual 20 frequency value of the device clock. This property is valid 21 only for the Gaudi ASIC family 22 23What: /sys/class/habanalabs/hl<n>/clk_cur_freq_mhz 24Date: Jun 2019 25KernelVersion: not yet upstreamed 26Contact: oded.gabbay@gmail.com 27Description: Displays the current frequency, in MHz, of the device clock. 28 This property is valid only for the Gaudi ASIC family 29 30What: /sys/class/habanalabs/hl<n>/cpld_ver 31Date: Jan 2019 32KernelVersion: 5.1 33Contact: oded.gabbay@gmail.com 34Description: Version of the Device's CPLD F/W 35 36What: /sys/class/habanalabs/hl<n>/device_type 37Date: Jan 2019 38KernelVersion: 5.1 39Contact: oded.gabbay@gmail.com 40Description: Displays the code name of the device according to its type. 41 The supported values are: "GOYA" 42 43What: /sys/class/habanalabs/hl<n>/eeprom 44Date: Jan 2019 45KernelVersion: 5.1 46Contact: oded.gabbay@gmail.com 47Description: A binary file attribute that contains the contents of the 48 on-board EEPROM 49 50What: /sys/class/habanalabs/hl<n>/fuse_ver 51Date: Jan 2019 52KernelVersion: 5.1 53Contact: oded.gabbay@gmail.com 54Description: Displays the device's version from the eFuse 55 56What: /sys/class/habanalabs/hl<n>/hard_reset 57Date: Jan 2019 58KernelVersion: 5.1 59Contact: oded.gabbay@gmail.com 60Description: Interface to trigger a hard-reset operation for the device. 61 Hard-reset will reset ALL internal components of the device 62 except for the PCI interface and the internal PLLs 63 64What: /sys/class/habanalabs/hl<n>/hard_reset_cnt 65Date: Jan 2019 66KernelVersion: 5.1 67Contact: oded.gabbay@gmail.com 68Description: Displays how many times the device have undergone a hard-reset 69 operation since the driver was loaded 70 71What: /sys/class/habanalabs/hl<n>/high_pll 72Date: Jan 2019 73KernelVersion: 5.1 74Contact: oded.gabbay@gmail.com 75Description: Allows the user to set the maximum clock frequency for MME, TPC 76 and IC when the power management profile is set to "automatic". 77 This property is valid only for the Goya ASIC family 78 79What: /sys/class/habanalabs/hl<n>/ic_clk 80Date: Jan 2019 81KernelVersion: 5.1 82Contact: oded.gabbay@gmail.com 83Description: Allows the user to set the maximum clock frequency, in Hz, of 84 the Interconnect fabric. Writes to this parameter affect the 85 device only when the power management profile is set to "manual" 86 mode. The device IC clock might be set to lower value than the 87 maximum. The user should read the ic_clk_curr to see the actual 88 frequency value of the IC. This property is valid only for the 89 Goya ASIC family 90 91What: /sys/class/habanalabs/hl<n>/ic_clk_curr 92Date: Jan 2019 93KernelVersion: 5.1 94Contact: oded.gabbay@gmail.com 95Description: Displays the current clock frequency, in Hz, of the Interconnect 96 fabric. This property is valid only for the Goya ASIC family 97 98What: /sys/class/habanalabs/hl<n>/infineon_ver 99Date: Jan 2019 100KernelVersion: 5.1 101Contact: oded.gabbay@gmail.com 102Description: Version of the Device's power supply F/W code 103 104What: /sys/class/habanalabs/hl<n>/max_power 105Date: Jan 2019 106KernelVersion: 5.1 107Contact: oded.gabbay@gmail.com 108Description: Allows the user to set the maximum power consumption of the 109 device in milliwatts. 110 111What: /sys/class/habanalabs/hl<n>/mme_clk 112Date: Jan 2019 113KernelVersion: 5.1 114Contact: oded.gabbay@gmail.com 115Description: Allows the user to set the maximum clock frequency, in Hz, of 116 the MME compute engine. Writes to this parameter affect the 117 device only when the power management profile is set to "manual" 118 mode. The device MME clock might be set to lower value than the 119 maximum. The user should read the mme_clk_curr to see the actual 120 frequency value of the MME. This property is valid only for the 121 Goya ASIC family 122 123What: /sys/class/habanalabs/hl<n>/mme_clk_curr 124Date: Jan 2019 125KernelVersion: 5.1 126Contact: oded.gabbay@gmail.com 127Description: Displays the current clock frequency, in Hz, of the MME compute 128 engine. This property is valid only for the Goya ASIC family 129 130What: /sys/class/habanalabs/hl<n>/pci_addr 131Date: Jan 2019 132KernelVersion: 5.1 133Contact: oded.gabbay@gmail.com 134Description: Displays the PCI address of the device. This is needed so the 135 user would be able to open a device based on its PCI address 136 137What: /sys/class/habanalabs/hl<n>/pm_mng_profile 138Date: Jan 2019 139KernelVersion: 5.1 140Contact: oded.gabbay@gmail.com 141Description: Power management profile. Values are "auto", "manual". In "auto" 142 mode, the driver will set the maximum clock frequency to a high 143 value when a user-space process opens the device's file (unless 144 it was already opened by another process). The driver will set 145 the max clock frequency to a low value when there are no user 146 processes that are opened on the device's file. In "manual" 147 mode, the user sets the maximum clock frequency by writing to 148 ic_clk, mme_clk and tpc_clk. This property is valid only for 149 the Goya ASIC family 150 151What: /sys/class/habanalabs/hl<n>/preboot_btl_ver 152Date: Jan 2019 153KernelVersion: 5.1 154Contact: oded.gabbay@gmail.com 155Description: Version of the device's preboot F/W code 156 157What: /sys/class/habanalabs/hl<n>/soft_reset 158Date: Jan 2019 159KernelVersion: 5.1 160Contact: oded.gabbay@gmail.com 161Description: Interface to trigger a soft-reset operation for the device. 162 Soft-reset will reset only the compute and DMA engines of the 163 device 164 165What: /sys/class/habanalabs/hl<n>/soft_reset_cnt 166Date: Jan 2019 167KernelVersion: 5.1 168Contact: oded.gabbay@gmail.com 169Description: Displays how many times the device have undergone a soft-reset 170 operation since the driver was loaded 171 172What: /sys/class/habanalabs/hl<n>/status 173Date: Jan 2019 174KernelVersion: 5.1 175Contact: oded.gabbay@gmail.com 176Description: Status of the card: "Operational", "Malfunction", "In reset". 177 178What: /sys/class/habanalabs/hl<n>/thermal_ver 179Date: Jan 2019 180KernelVersion: 5.1 181Contact: oded.gabbay@gmail.com 182Description: Version of the Device's thermal daemon 183 184What: /sys/class/habanalabs/hl<n>/tpc_clk 185Date: Jan 2019 186KernelVersion: 5.1 187Contact: oded.gabbay@gmail.com 188Description: Allows the user to set the maximum clock frequency, in Hz, of 189 the TPC compute engines. Writes to this parameter affect the 190 device only when the power management profile is set to "manual" 191 mode. The device TPC clock might be set to lower value than the 192 maximum. The user should read the tpc_clk_curr to see the actual 193 frequency value of the TPC. This property is valid only for 194 Goya ASIC family 195 196What: /sys/class/habanalabs/hl<n>/tpc_clk_curr 197Date: Jan 2019 198KernelVersion: 5.1 199Contact: oded.gabbay@gmail.com 200Description: Displays the current clock frequency, in Hz, of the TPC compute 201 engines. This property is valid only for the Goya ASIC family 202 203What: /sys/class/habanalabs/hl<n>/uboot_ver 204Date: Jan 2019 205KernelVersion: 5.1 206Contact: oded.gabbay@gmail.com 207Description: Version of the u-boot running on the device's CPU