1*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/BINF.2 2*0a4cad9cSEnric Balletbo i SerraDate: May 2022 3*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 4*0a4cad9cSEnric Balletbo i SerraDescription: 5*0a4cad9cSEnric Balletbo i Serra This file shows information about the current boot of 6*0a4cad9cSEnric Balletbo i Serra the active EC firmware. 7*0a4cad9cSEnric Balletbo i Serra * 0 - Read only (recovery) firmware. 8*0a4cad9cSEnric Balletbo i Serra * 1 - Rewritable firmware. 9*0a4cad9cSEnric Balletbo i Serra 10*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/BINF.3 11*0a4cad9cSEnric Balletbo i SerraDate: May 2022 12*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 13*0a4cad9cSEnric Balletbo i SerraDescription: 14*0a4cad9cSEnric Balletbo i Serra This file shows information about the current boot of 15*0a4cad9cSEnric Balletbo i Serra the active main firmware type. 16*0a4cad9cSEnric Balletbo i Serra * 0 - Recovery. 17*0a4cad9cSEnric Balletbo i Serra * 1 - Normal. 18*0a4cad9cSEnric Balletbo i Serra * 2 - Developer. 19*0a4cad9cSEnric Balletbo i Serra * 3 - Netboot (factory installation only). 20*0a4cad9cSEnric Balletbo i Serra 21*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/CHSW 22*0a4cad9cSEnric Balletbo i SerraDate: May 2022 23*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 24*0a4cad9cSEnric Balletbo i SerraDescription: 25*0a4cad9cSEnric Balletbo i Serra This file shows the switch position for the Chrome OS specific 26*0a4cad9cSEnric Balletbo i Serra hardware switches. 27*0a4cad9cSEnric Balletbo i Serra * 0 - No changes. 28*0a4cad9cSEnric Balletbo i Serra * 2 - Recovery button was pressed when firmware booted. 29*0a4cad9cSEnric Balletbo i Serra * 4 - Recovery button was pressed when EC firmware booted. 30*0a4cad9cSEnric Balletbo i Serra * 32 - Developer switch was enabled when firmware booted. 31*0a4cad9cSEnric Balletbo i Serra * 512 - Firmware write protection was disabled when firmware 32*0a4cad9cSEnric Balletbo i Serra booted. 33*0a4cad9cSEnric Balletbo i Serra 34*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/FMAP 35*0a4cad9cSEnric Balletbo i SerraDate: May 2022 36*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 37*0a4cad9cSEnric Balletbo i SerraDescription: 38*0a4cad9cSEnric Balletbo i Serra This file shows the physical memory address of the start of 39*0a4cad9cSEnric Balletbo i Serra the main processor firmware flashmap. 40*0a4cad9cSEnric Balletbo i Serra 41*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/FRID 42*0a4cad9cSEnric Balletbo i SerraDate: May 2022 43*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 44*0a4cad9cSEnric Balletbo i SerraDescription: 45*0a4cad9cSEnric Balletbo i Serra This file shows the firmware version for the read-only portion 46*0a4cad9cSEnric Balletbo i Serra of the main processor firmware. 47*0a4cad9cSEnric Balletbo i Serra 48*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/FWID 49*0a4cad9cSEnric Balletbo i SerraDate: May 2022 50*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 51*0a4cad9cSEnric Balletbo i SerraDescription: 52*0a4cad9cSEnric Balletbo i Serra This file shows the firmware version for the rewritable portion 53*0a4cad9cSEnric Balletbo i Serra of the main processor firmware. 54*0a4cad9cSEnric Balletbo i Serra 55*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/GPIO.X/GPIO.0 56*0a4cad9cSEnric Balletbo i SerraDate: May 2022 57*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 58*0a4cad9cSEnric Balletbo i SerraDescription: 59*0a4cad9cSEnric Balletbo i Serra This file shows the type of the GPIO signal for the Chrome OS 60*0a4cad9cSEnric Balletbo i Serra specific GPIO assignments. 61*0a4cad9cSEnric Balletbo i Serra * 1 - Recovery button. 62*0a4cad9cSEnric Balletbo i Serra * 2 - Developer mode switch. 63*0a4cad9cSEnric Balletbo i Serra * 3 - Firmware write protection switch. 64*0a4cad9cSEnric Balletbo i Serra * 256 to 511 - Debug header GPIO 0 to GPIO 255. 65*0a4cad9cSEnric Balletbo i Serra 66*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/GPIO.X/GPIO.1 67*0a4cad9cSEnric Balletbo i SerraDate: May 2022 68*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 69*0a4cad9cSEnric Balletbo i SerraDescription: 70*0a4cad9cSEnric Balletbo i Serra This file shows the signal attributes of the GPIO signal. 71*0a4cad9cSEnric Balletbo i Serra * 0 - Signal is active low. 72*0a4cad9cSEnric Balletbo i Serra * 1 - Signal is active high. 73*0a4cad9cSEnric Balletbo i Serra 74*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/GPIO.X/GPIO.2 75*0a4cad9cSEnric Balletbo i SerraDate: May 2022 76*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 77*0a4cad9cSEnric Balletbo i SerraDescription: 78*0a4cad9cSEnric Balletbo i Serra This file shows the GPIO number on the specified GPIO 79*0a4cad9cSEnric Balletbo i Serra controller. 80*0a4cad9cSEnric Balletbo i Serra 81*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/GPIO.X/GPIO.3 82*0a4cad9cSEnric Balletbo i SerraDate: May 2022 83*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 84*0a4cad9cSEnric Balletbo i SerraDescription: 85*0a4cad9cSEnric Balletbo i Serra This file shows the name of the GPIO controller. 86*0a4cad9cSEnric Balletbo i Serra 87*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/HWID 88*0a4cad9cSEnric Balletbo i SerraDate: May 2022 89*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 90*0a4cad9cSEnric Balletbo i SerraDescription: 91*0a4cad9cSEnric Balletbo i Serra This file shows the hardware ID for the Chromebook. 92*0a4cad9cSEnric Balletbo i Serra 93*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/MECK 94*0a4cad9cSEnric Balletbo i SerraDate: May 2022 95*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 96*0a4cad9cSEnric Balletbo i SerraDescription: 97*0a4cad9cSEnric Balletbo i Serra This binary file returns the SHA-1 or SHA-256 hash that is 98*0a4cad9cSEnric Balletbo i Serra read out of the Management Engine extended registers during 99*0a4cad9cSEnric Balletbo i Serra boot. The hash is exported vi ACPI so the OS can verify that 100*0a4cad9cSEnric Balletbo i Serra the Management Engine firmware has not changed. If Management 101*0a4cad9cSEnric Balletbo i Serra Engine is not present, or if the firmware was unable to read the 102*0a4cad9cSEnric Balletbo i Serra extended registers, this buffer size can be zero. 103*0a4cad9cSEnric Balletbo i Serra 104*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/VBNV.0 105*0a4cad9cSEnric Balletbo i SerraDate: May 2022 106*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 107*0a4cad9cSEnric Balletbo i SerraDescription: 108*0a4cad9cSEnric Balletbo i Serra This file shows the offset in CMOS bank 0 of the verified boot 109*0a4cad9cSEnric Balletbo i Serra non-volatile storage block, counting from the first writable 110*0a4cad9cSEnric Balletbo i Serra CMOS byte (that is, 'offset = 0' is the byte following the 14 111*0a4cad9cSEnric Balletbo i Serra bytes of clock data). 112*0a4cad9cSEnric Balletbo i Serra 113*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/VBNV.1 114*0a4cad9cSEnric Balletbo i SerraDate: May 2022 115*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 116*0a4cad9cSEnric Balletbo i SerraDescription: 117*0a4cad9cSEnric Balletbo i Serra This file shows the size in bytes of the verified boot 118*0a4cad9cSEnric Balletbo i Serra non-volatile storage block. 119*0a4cad9cSEnric Balletbo i Serra 120*0a4cad9cSEnric Balletbo i SerraWhat: /sys/bus/platform/devices/GGL0001:*/VDAT 121*0a4cad9cSEnric Balletbo i SerraDate: May 2022 122*0a4cad9cSEnric Balletbo i SerraKernelVersion: 5.19 123*0a4cad9cSEnric Balletbo i SerraDescription: 124*0a4cad9cSEnric Balletbo i Serra This binary file returns the verified boot data block shared 125*0a4cad9cSEnric Balletbo i Serra between the firmware verification step and the kernel 126*0a4cad9cSEnric Balletbo i Serra verification step. 127