1*2ceb3fb0SAlex ChiangWhat: /sys/devices/system/cpu/ 2*2ceb3fb0SAlex ChiangDate: pre-git history 3*2ceb3fb0SAlex ChiangContact: Linux kernel mailing list <linux-kernel@vger.kernel.org> 4*2ceb3fb0SAlex ChiangDescription: 5*2ceb3fb0SAlex Chiang A collection of both global and individual CPU attributes 6*2ceb3fb0SAlex Chiang 7*2ceb3fb0SAlex Chiang Individual CPU attributes are contained in subdirectories 8*2ceb3fb0SAlex Chiang named by the kernel's logical CPU number, e.g.: 9*2ceb3fb0SAlex Chiang 10*2ceb3fb0SAlex Chiang /sys/devices/system/cpu/cpu#/ 11*2ceb3fb0SAlex Chiang 12*2ceb3fb0SAlex Chiang 13468727abSAlex ChiangWhat: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X 14468727abSAlex ChiangDate: August 2008 15468727abSAlex ChiangKernelVersion: 2.6.27 16468727abSAlex ChiangContact: mark.langsdorf@amd.com 17468727abSAlex ChiangDescription: These files exist in every cpu's cache index directories. 18468727abSAlex Chiang There are currently 2 cache_disable_# files in each 19468727abSAlex Chiang directory. Reading from these files on a supported 20468727abSAlex Chiang processor will return that cache disable index value 21468727abSAlex Chiang for that processor and node. Writing to one of these 22468727abSAlex Chiang files will cause the specificed cache index to be disabled. 23468727abSAlex Chiang 24468727abSAlex Chiang Currently, only AMD Family 10h Processors support cache index 25468727abSAlex Chiang disable, and only for their L3 caches. See the BIOS and 26468727abSAlex Chiang Kernel Developer's Guide at 27468727abSAlex Chiang http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf 28468727abSAlex Chiang for formatting information and other details on the 29468727abSAlex Chiang cache index disable. 30468727abSAlex ChiangUsers: joachim.deguara@amd.com 31