1What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present 2What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present 3What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present 4What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present 5What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present 6What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present 7KernelVersion: 3.4.0 8Contact: linux-iio@vger.kernel.org 9Description: 10 Reading returns either '1' or '0'. 11 '1' means that the clock in question is present. 12 '0' means that the clock is missing. 13 14What: /sys/bus/iio/devices/iio:deviceX/pllY_locked 15KernelVersion: 3.4.0 16Contact: linux-iio@vger.kernel.org 17Description: 18 Reading returns either '1' or '0'. '1' means that the 19 pllY is locked. 20 21What: /sys/bus/iio/devices/iio:deviceX/sync_dividers 22KernelVersion: 3.4.0 23Contact: linux-iio@vger.kernel.org 24Description: 25 Writing '1' triggers the clock distribution synchronization 26 functionality. All dividers are reset and the channels start 27 with their predefined phase offsets (out_altvoltageY_phase). 28 Writing this file has the effect as driving the external 29 /SYNC pin low. 30