1f9cc5b5aSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable 2f9cc5b5aSTao ZhangDate: December 2025 3f9cc5b5aSTao ZhangKernelVersion: 6.20 4f9cc5b5aSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 5f9cc5b5aSTao ZhangDescription: 6f9cc5b5aSTao Zhang (RW) Enable/disable cross trigger synchronization sequence interface. 7f9cc5b5aSTao Zhang 8f9cc5b5aSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable 9f9cc5b5aSTao ZhangDate: December 2025 10f9cc5b5aSTao ZhangKernelVersion: 6.20 11f9cc5b5aSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 12f9cc5b5aSTao ZhangDescription: 13f9cc5b5aSTao Zhang (RW) Enable/disable cross trigger FLAG packet request interface. 14f9cc5b5aSTao Zhang 15f9cc5b5aSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable 16f9cc5b5aSTao ZhangDate: December 2025 17f9cc5b5aSTao ZhangKernelVersion: 6.20 18f9cc5b5aSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 19f9cc5b5aSTao ZhangDescription: 20f9cc5b5aSTao Zhang (RW) Enable/disable cross trigger FREQ packet request interface. 21f9cc5b5aSTao Zhang 22f9cc5b5aSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable 23f9cc5b5aSTao ZhangDate: December 2025 24f9cc5b5aSTao ZhangKernelVersion: 6.20 25f9cc5b5aSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 26f9cc5b5aSTao ZhangDescription: 27f9cc5b5aSTao Zhang (RW) Enable/disable the timestamp for all FREQ packets. 28f9cc5b5aSTao Zhang 29f9cc5b5aSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode 30f9cc5b5aSTao ZhangDate: December 2025 31f9cc5b5aSTao ZhangKernelVersion: 6.20 32f9cc5b5aSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 33f9cc5b5aSTao ZhangDescription: 34f9cc5b5aSTao Zhang (RW) Configure the CMB/MCMB channel mode for all enabled ports. 35f9cc5b5aSTao Zhang Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. 368e1c358aSJie Gan 378e1c358aSJie GanWhat: /sys/bus/coresight/devices/<tpda-name>/global_flush_req 388e1c358aSJie GanDate: December 2025 398e1c358aSJie GanKernelVersion: 6.20 408e1c358aSJie GanContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 418e1c358aSJie GanDescription: 428e1c358aSJie Gan (RW) Set global (all ports) flush request bit. The bit remains set until a 438e1c358aSJie Gan global flush request sequence completes. 4433f04eadSTao Zhang 4533f04eadSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/syncr_mode 4633f04eadSTao ZhangDate: December 2025 4733f04eadSTao ZhangKernelVersion: 6.20 4833f04eadSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 4933f04eadSTao ZhangDescription: 5033f04eadSTao Zhang (RW) Set mode the of the syncr counter. 5133f04eadSTao Zhang mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests 5233f04eadSTao Zhang mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K 5333f04eadSTao Zhang data by writing a value 13 to the COUNT[11:7] field. 5433f04eadSTao Zhang 5533f04eadSTao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/syncr_count 5633f04eadSTao ZhangDate: December 2025 5733f04eadSTao ZhangKernelVersion: 6.20 5833f04eadSTao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 5933f04eadSTao ZhangDescription: 6033f04eadSTao Zhang (RW) Set value the of the syncr counter. 6133f04eadSTao Zhang Range: 0-4095 62*a089d585STao Zhang 63*a089d585STao ZhangWhat: /sys/bus/coresight/devices/<tpda-name>/port_flush_req 64*a089d585STao ZhangDate: December 2025 65*a089d585STao ZhangKernelVersion: 6.20 66*a089d585STao ZhangContact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> 67*a089d585STao ZhangDescription: 68*a089d585STao Zhang (RW) Configure the bit i to requests a flush operation of port i on the TPDA. 69*a089d585STao Zhang The requested bit(s) remain set until the flush request completes. 70