1What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr 2Date: November 2014 3KernelVersion: 3.19 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Disables write access to the Trace RAM by stopping the 6 formatter after a defined number of words have been stored 7 following the trigger event. Additional interface for this 8 driver are expected to be added as it matures. 9 10What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz 11Date: March 2016 12KernelVersion: 4.7 13Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 14Description: (R) Defines the size, in 32-bit words, of the local RAM buffer. 15 The value is read directly from HW register RSZ, 0x004. 16 17What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts 18Date: March 2016 19KernelVersion: 4.7 20Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 21Description: (R) Shows the value held by the TMC status register. The value 22 is read directly from HW register STS, 0x00C. 23 24What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp 25Date: March 2016 26KernelVersion: 4.7 27Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 28Description: (R) Shows the value held by the TMC RAM Read Pointer register 29 that is used to read entries from the Trace RAM over the APB 30 interface. The value is read directly from HW register RRP, 31 0x014. 32 33What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp 34Date: March 2016 35KernelVersion: 4.7 36Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 37Description: (R) Shows the value held by the TMC RAM Write Pointer register 38 that is used to sets the write pointer to write entries from 39 the CoreSight bus into the Trace RAM. The value is read directly 40 from HW register RWP, 0x018. 41 42What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg 43Date: March 2016 44KernelVersion: 4.7 45Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 46Description: (R) Similar to "trigger_cntr" above except that this value is 47 read directly from HW register TRG, 0x01C. 48 49What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl 50Date: March 2016 51KernelVersion: 4.7 52Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 53Description: (R) Shows the value held by the TMC Control register. The value 54 is read directly from HW register CTL, 0x020. 55 56What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr 57Date: March 2016 58KernelVersion: 4.7 59Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 60Description: (R) Shows the value held by the TMC Formatter and Flush Status 61 register. The value is read directly from HW register FFSR, 62 0x300. 63 64What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr 65Date: March 2016 66KernelVersion: 4.7 67Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 68Description: (R) Shows the value held by the TMC Formatter and Flush Control 69 register. The value is read directly from HW register FFCR, 70 0x304. 71 72What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode 73Date: March 2016 74KernelVersion: 4.7 75Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 76Description: (R) Shows the value held by the TMC Mode register, which 77 indicate the mode the device has been configured to enact. The 78 The value is read directly from the MODE register, 0x028. 79 80What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid 81Date: March 2016 82KernelVersion: 4.7 83Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 84Description: (R) Indicates the capabilities of the Coresight TMC. 85 The value is read directly from the DEVID register, 0xFC8, 86 87What: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size 88Date: December 2018 89KernelVersion: 4.19 90Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 91Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS 92 mode. Writable only for TMC-ETR configurations. The value 93 should be aligned to the kernel pagesize. 94