1What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 2Date: April 2016 3KernelVersion: 4.7 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Enable/disable tracing on this specific trace macrocell. 6 Enabling the trace macrocell implies it has been configured 7 properly and a sink has been identified for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 12Date: April 2016 13KernelVersion: 4.7 14Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15Description: (RW) Provides access to the HW event enable register, used in 16 conjunction with HW event bank select register. 17 18What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 19Date: April 2016 20KernelVersion: 4.7 21Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 22Description: (RW) Gives access to the HW event block select register 23 (STMHEBSR) in order to configure up to 256 channels. Used in 24 conjunction with "hwevent_enable" register as described above. 25 26What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 27Date: April 2016 28KernelVersion: 4.7 29Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 30Description: (RW) Provides access to the stimulus port enable register 31 (STMSPER). Used in conjunction with "port_select" described 32 below. 33 34What: /sys/bus/coresight/devices/<memory_map>.stm/port_select 35Date: April 2016 36KernelVersion: 4.7 37Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 38Description: (RW) Used to determine which bank of stimulus port bit in 39 register STMSPER (see above) apply to. 40 41What: /sys/bus/coresight/devices/<memory_map>.stm/status 42Date: April 2016 43KernelVersion: 4.7 44Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 45Description: (Read) List various control and status registers. The specific 46 layout and content is driver specific. 47 48What: /sys/bus/coresight/devices/<memory_map>.stm/traceid 49Date: April 2016 50KernelVersion: 4.7 51Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 52Description: (RW) Holds the trace ID that will appear in the trace stream 53 coming from this trace entity. 54