1What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source 2Date: April 2015 3KernelVersion: 4.01 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Enable/disable tracing on this specific trace entiry. 6 Enabling a source implies the source has been configured 7 properly and a sink has been identidifed for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11What: /sys/bus/coresight/devices/<memory_map>.etm/cpu 12Date: April 2015 13KernelVersion: 4.01 14Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15Description: (R) The CPU this tracing entity is associated with. 16 17What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp 18Date: April 2015 19KernelVersion: 4.01 20Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 21Description: (R) Indicates the number of PE comparator inputs that are 22 available for tracing. 23 24What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp 25Date: April 2015 26KernelVersion: 4.01 27Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 28Description: (R) Indicates the number of address comparator pairs that are 29 available for tracing. 30 31What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr 32Date: April 2015 33KernelVersion: 4.01 34Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 35Description: (R) Indicates the number of counters that are available for 36 tracing. 37 38What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp 39Date: April 2015 40KernelVersion: 4.01 41Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 42Description: (R) Indicates how many external inputs are implemented. 43 44What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc 45Date: April 2015 46KernelVersion: 4.01 47Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 48Description: (R) Indicates the number of Context ID comparators that are 49 available for tracing. 50 51What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc 52Date: April 2015 53KernelVersion: 4.01 54Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 55Description: (R) Indicates the number of VMID comparators that are available 56 for tracing. 57 58What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate 59Date: April 2015 60KernelVersion: 4.01 61Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 62Description: (R) Indicates the number of sequencer states that are 63 implemented. 64 65What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource 66Date: April 2015 67KernelVersion: 4.01 68Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 69Description: (R) Indicates the number of resource selection pairs that are 70 available for tracing. 71 72What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp 73Date: April 2015 74KernelVersion: 4.01 75Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 76Description: (R) Indicates the number of single-shot comparator controls that 77 are available for tracing. 78 79What: /sys/bus/coresight/devices/<memory_map>.etm/reset 80Date: April 2015 81KernelVersion: 4.01 82Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 83Description: (W) Cancels all configuration on a trace unit and set it back 84 to its boot configuration. 85 86What: /sys/bus/coresight/devices/<memory_map>.etm/mode 87Date: April 2015 88KernelVersion: 4.01 89Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 90Description: (RW) Controls various modes supported by this ETM, for example 91 P0 instruction tracing, branch broadcast, cycle counting and 92 context ID tracing. 93 94What: /sys/bus/coresight/devices/<memory_map>.etm/pe 95Date: April 2015 96KernelVersion: 4.01 97Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 98Description: (RW) Controls which PE to trace. 99 100What: /sys/bus/coresight/devices/<memory_map>.etm/event 101Date: April 2015 102KernelVersion: 4.01 103Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 104Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. 105 106What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren 107Date: April 2015 108KernelVersion: 4.01 109Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 110Description: (RW) Controls the behavior of the events in bank 0 to 3. 111 112What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts 113Date: April 2015 114KernelVersion: 4.01 115Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 116Description: (RW) Controls the insertion of global timestamps in the trace 117 streams. 118 119What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq 120Date: April 2015 121KernelVersion: 4.01 122Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 123Description: (RW) Controls how often trace synchronization requests occur. 124 125What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold 126Date: April 2015 127KernelVersion: 4.01 128Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 129Description: (RW) Sets the threshold value for cycle counting. 130 131What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl 132Date: April 2015 133KernelVersion: 4.01 134Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 135Description: (RW) Controls which regions in the memory map are enabled to 136 use branch broadcasting. 137 138What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst 139Date: April 2015 140KernelVersion: 4.01 141Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 142Description: (RW) Controls instruction trace filtering. 143 144What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst 145Date: April 2015 146KernelVersion: 4.01 147Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 148Description: (RW) In Secure state, each bit controls whether instruction 149 tracing is enabled for the corresponding exception level. 150 151What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst 152Date: April 2015 153KernelVersion: 4.01 154Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 155Description: (RW) In non-secure state, each bit controls whether instruction 156 tracing is enabled for the corresponding exception level. 157 158What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx 159Date: April 2015 160KernelVersion: 4.01 161Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 162Description: (RW) Select which address comparator or pair (of comparators) to 163 work with. 164 165What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype 166Date: April 2015 167KernelVersion: 4.01 168Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 169Description: (RW) Controls what type of comparison the trace unit performs. 170 171What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single 172Date: April 2015 173KernelVersion: 4.01 174Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 175Description: (RW) Used to setup single address comparator values. 176 177What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range 178Date: April 2015 179KernelVersion: 4.01 180Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 181Description: (RW) Used to setup address range comparator values. 182 183What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx 184Date: April 2015 185KernelVersion: 4.01 186Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 187Description: (RW) Select which sequensor. 188 189What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state 190Date: April 2015 191KernelVersion: 4.01 192Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 193Description: (RW) Use this to set, or read, the sequencer state. 194 195What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event 196Date: April 2015 197KernelVersion: 4.01 198Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 199Description: (RW) Moves the sequencer state to a specific state. 200 201What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event 202Date: April 2015 203KernelVersion: 4.01 204Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 205Description: (RW) Moves the sequencer to state 0 when a programmed event 206 occurs. 207 208What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx 209Date: April 2015 210KernelVersion: 4.01 211Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 212Description: (RW) Select which counter unit to work with. 213 214What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr 215Date: April 2015 216KernelVersion: 4.01 217Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 218Description: (RW) This sets or returns the reload count value of the 219 specific counter. 220 221What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val 222Date: April 2015 223KernelVersion: 4.01 224Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 225Description: (RW) This sets or returns the current count value of the 226 specific counter. 227 228What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl 229Date: April 2015 230KernelVersion: 4.01 231Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 232Description: (RW) Controls the operation of the selected counter. 233 234What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx 235Date: April 2015 236KernelVersion: 4.01 237Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 238Description: (RW) Select which resource selection unit to work with. 239 240What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl 241Date: April 2015 242KernelVersion: 4.01 243Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 244Description: (RW) Controls the selection of the resources in the trace unit. 245 246What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx 247Date: April 2015 248KernelVersion: 4.01 249Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 250Description: (RW) Select which context ID comparator to work with. 251 252What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid 253Date: April 2015 254KernelVersion: 4.01 255Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 256Description: (RW) Get/Set the context ID comparator value to trigger on. 257 258What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks 259Date: April 2015 260KernelVersion: 4.01 261Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 262Description: (RW) Mask for all 8 context ID comparator value 263 registers (if implemented). 264 265What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx 266Date: April 2015 267KernelVersion: 4.01 268Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 269Description: (RW) Select which virtual machine ID comparator to work with. 270 271What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val 272Date: April 2015 273KernelVersion: 4.01 274Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 275Description: (RW) Get/Set the virtual machine ID comparator value to 276 trigger on. 277 278What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks 279Date: April 2015 280KernelVersion: 4.01 281Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 282Description: (RW) Mask for all 8 virtual machine ID comparator value 283 registers (if implemented). 284 285What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr 286Date: April 2015 287KernelVersion: 4.01 288Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 289Description: (R) Print the content of the OS Lock Status Register (0x304). 290 The value it taken directly from the HW. 291 292What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr 293Date: April 2015 294KernelVersion: 4.01 295Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 296Description: (R) Print the content of the Power Down Control Register 297 (0x310). The value is taken directly from the HW. 298 299What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr 300Date: April 2015 301KernelVersion: 4.01 302Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 303Description: (R) Print the content of the Power Down Status Register 304 (0x314). The value is taken directly from the HW. 305 306What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr 307Date: April 2015 308KernelVersion: 4.01 309Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 310Description: (R) Print the content of the SW Lock Status Register 311 (0xFB4). The value is taken directly from the HW. 312 313What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus 314Date: April 2015 315KernelVersion: 4.01 316Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 317Description: (R) Print the content of the Authentication Status Register 318 (0xFB8). The value is taken directly from the HW. 319 320What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid 321Date: April 2015 322KernelVersion: 4.01 323Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 324Description: (R) Print the content of the Device ID Register 325 (0xFC8). The value is taken directly from the HW. 326 327What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype 328Date: April 2015 329KernelVersion: 4.01 330Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 331Description: (R) Print the content of the Device Type Register 332 (0xFCC). The value is taken directly from the HW. 333 334What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 335Date: April 2015 336KernelVersion: 4.01 337Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 338Description: (R) Print the content of the Peripheral ID0 Register 339 (0xFE0). The value is taken directly from the HW. 340 341What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 342Date: April 2015 343KernelVersion: 4.01 344Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 345Description: (R) Print the content of the Peripheral ID1 Register 346 (0xFE4). The value is taken directly from the HW. 347 348What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 349Date: April 2015 350KernelVersion: 4.01 351Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 352Description: (R) Print the content of the Peripheral ID2 Register 353 (0xFE8). The value is taken directly from the HW. 354 355What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 356Date: April 2015 357KernelVersion: 4.01 358Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 359Description: (R) Print the content of the Peripheral ID3 Register 360 (0xFEC). The value is taken directly from the HW. 361 362What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 363Date: April 2015 364KernelVersion: 4.01 365Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 366Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). 367 The value is taken directly from the HW. 368 369What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 370Date: April 2015 371KernelVersion: 4.01 372Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 373Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). 374 The value is taken directly from the HW. 375 376What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 377Date: April 2015 378KernelVersion: 4.01 379Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 380Description: (R) Returns the maximum size of the data value, data address, 381 VMID, context ID and instuction address in the trace unit 382 (0x1E8). The value is taken directly from the HW. 383 384What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 385Date: April 2015 386KernelVersion: 4.01 387Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 388Description: (R) Returns the value associated with various resources 389 available to the trace unit. See the Trace Macrocell 390 architecture specification for more details (0x1E8). 391 The value is taken directly from the HW. 392 393What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 394Date: April 2015 395KernelVersion: 4.01 396Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 397Description: (R) Returns how many resources the trace unit supports (0x1F0). 398 The value is taken directly from the HW. 399 400What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 401Date: April 2015 402KernelVersion: 4.01 403Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 404Description: (R) Returns how many resources the trace unit supports (0x1F4). 405 The value is taken directly from the HW. 406 407What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 408Date: April 2015 409KernelVersion: 4.01 410Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 411Description: (R) Returns the maximum speculation depth of the instruction 412 trace stream. (0x180). The value is taken directly from the HW. 413 414What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 415Date: April 2015 416KernelVersion: 4.01 417Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 418Description: (R) Returns the number of P0 right-hand keys that the trace unit 419 can use (0x184). The value is taken directly from the HW. 420 421What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 422Date: April 2015 423KernelVersion: 4.01 424Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 425Description: (R) Returns the number of P1 right-hand keys that the trace unit 426 can use (0x188). The value is taken directly from the HW. 427 428What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 429Date: April 2015 430KernelVersion: 4.01 431Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 432Description: (R) Returns the number of special P1 right-hand keys that the 433 trace unit can use (0x18C). The value is taken directly from 434 the HW. 435 436What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 437Date: April 2015 438KernelVersion: 4.01 439Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 440Description: (R) Returns the number of conditional P1 right-hand keys that 441 the trace unit can use (0x190). The value is taken directly 442 from the HW. 443 444What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 445Date: April 2015 446KernelVersion: 4.01 447Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 448Description: (R) Returns the number of special conditional P1 right-hand keys 449 that the trace unit can use (0x194). The value is taken 450 directly from the HW. 451