1*2e1cdfe1SPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.etm/enable_source 2*2e1cdfe1SPratik PatelDate: April 2015 3*2e1cdfe1SPratik PatelKernelVersion: 4.01 4*2e1cdfe1SPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*2e1cdfe1SPratik PatelDescription: (RW) Enable/disable tracing on this specific trace entiry. 6*2e1cdfe1SPratik Patel Enabling a source implies the source has been configured 7*2e1cdfe1SPratik Patel properly and a sink has been identidifed for it. The path 8*2e1cdfe1SPratik Patel of coresight components linking the source to the sink is 9*2e1cdfe1SPratik Patel configured and managed automatically by the coresight framework. 10*2e1cdfe1SPratik Patel 11*2e1cdfe1SPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.etm/cpu 12*2e1cdfe1SPratik PatelDate: April 2015 13*2e1cdfe1SPratik PatelKernelVersion: 4.01 14*2e1cdfe1SPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 15*2e1cdfe1SPratik PatelDescription: (R) The CPU this tracing entity is associated with. 16