1What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source 2Date: November 2014 3KernelVersion: 3.19 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Enable/disable tracing on this specific trace entiry. 6 Enabling a source implies the source has been configured 7 properly and a sink has been identidifed for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx 12Date: November 2014 13KernelVersion: 3.19 14Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15Description: Select which address comparator or pair (of comparators) to 16 work with. 17 18What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype 19Date: November 2014 20KernelVersion: 3.19 21Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 22Description: (RW) Used in conjunction with @addr_idx. Specifies 23 characteristics about the address comparator being configure, 24 for example the access type, the kind of instruction to trace, 25 processor contect ID to trigger on, etc. Individual fields in 26 the access type register may vary on the version of the trace 27 entity. 28 29What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range 30Date: November 2014 31KernelVersion: 3.19 32Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 33Description: (RW) Used in conjunction with @addr_idx. Specifies the range of 34 addresses to trigger on. Inclusion or exclusion is specificed 35 in the corresponding access type register. 36 37What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single 38Date: November 2014 39KernelVersion: 3.19 40Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 41Description: (RW) Used in conjunction with @addr_idx. Specifies the single 42 address to trigger on, highly influenced by the configuration 43 options of the corresponding access type register. 44 45What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start 46Date: November 2014 47KernelVersion: 3.19 48Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 49Description: (RW) Used in conjunction with @addr_idx. Specifies the single 50 address to start tracing on, highly influenced by the 51 configuration options of the corresponding access type register. 52 53What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop 54Date: November 2014 55KernelVersion: 3.19 56Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 57Description: (RW) Used in conjunction with @addr_idx. Specifies the single 58 address to stop tracing on, highly influenced by the 59 configuration options of the corresponding access type register. 60 61What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx 62Date: November 2014 63KernelVersion: 3.19 64Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 65Description: (RW) Specifies the counter to work on. 66 67What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event 68Date: November 2014 69KernelVersion: 3.19 70Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 71Description: (RW) Used in conjunction with cntr_idx, give access to the 72 counter event register. 73 74What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val 75Date: November 2014 76KernelVersion: 3.19 77Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 78Description: (RW) Used in conjunction with cntr_idx, give access to the 79 counter value register. 80 81What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val 82Date: November 2014 83KernelVersion: 3.19 84Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 85Description: (RW) Used in conjunction with cntr_idx, give access to the 86 counter reload value register. 87 88What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event 89Date: November 2014 90KernelVersion: 3.19 91Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 92Description: (RW) Used in conjunction with cntr_idx, give access to the 93 counter reload event register. 94 95What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx 96Date: November 2014 97KernelVersion: 3.19 98Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 99Description: (RW) Specifies the index of the context ID register to be 100 selected. 101 102What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask 103Date: November 2014 104KernelVersion: 3.19 105Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 106Description: (RW) Mask to apply to all the context ID comparator. 107 108What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid 109Date: November 2014 110KernelVersion: 3.19 111Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 112Description: (RW) Used with the ctxid_idx, specify with context ID to trigger 113 on. 114 115What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event 116Date: November 2014 117KernelVersion: 3.19 118Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 119Description: (RW) Defines which event triggers a trace. 120 121What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr 122Date: November 2014 123KernelVersion: 3.19 124Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 125Description: (RW) Gives access to the ETM status register, which holds 126 programming information and status on certains events. 127 128What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level 129Date: November 2014 130KernelVersion: 3.19 131Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 132Description: (RW) Number of byte left in the fifo before considering it full. 133 Depending on the tracer's version, can also hold threshold for 134 data suppression. 135 136What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode 137Date: November 2014 138KernelVersion: 3.19 139Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 140Description: (RW) Interface with the driver's 'mode' field, controlling 141 various aspect of the trace entity such as time stamping, 142 context ID size and cycle accurate tracing. Driver specific 143 and bound to change depending on the driver. 144 145What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp 146Date: November 2014 147KernelVersion: 3.19 148Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 149Description: (Read) Provides the number of address comparators pairs accessible 150 on a trace unit, as specified by bit 3:0 of register ETMCCR. 151 152What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr 153Date: November 2014 154KernelVersion: 3.19 155Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 156Description: (Read) Provides the number of counters accessible on a trace unit, 157 as specified by bit 15:13 of register ETMCCR. 158 159What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp 160Date: November 2014 161KernelVersion: 3.19 162Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 163Description: (Read) Provides the number of context ID comparator available on a 164 trace unit, as specified by bit 25:24 of register ETMCCR. 165 166What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset 167Date: November 2014 168KernelVersion: 3.19 169Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 170Description: (Write) Cancels all configuration on a trace unit and set it back 171 to its boot configuration. 172 173What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event 174Date: November 2014 175KernelVersion: 3.19 176Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 177Description: (RW) Defines the event that causes the sequencer to transition 178 from state 1 to state 2. 179 180What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event 181Date: November 2014 182KernelVersion: 3.19 183Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 184Description: (RW) Defines the event that causes the sequencer to transition 185 from state 1 to state 3. 186 187What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event 188Date: November 2014 189KernelVersion: 3.19 190Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 191Description: (RW) Defines the event that causes the sequencer to transition 192 from state 2 to state 1. 193 194What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event 195Date: November 2014 196KernelVersion: 3.19 197Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 198Description: (RW) Defines the event that causes the sequencer to transition 199 from state 2 to state 3. 200 201What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event 202Date: November 2014 203KernelVersion: 3.19 204Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 205Description: (RW) Defines the event that causes the sequencer to transition 206 from state 3 to state 1. 207 208What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event 209Date: November 2014 210KernelVersion: 3.19 211Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 212Description: (RW) Defines the event that causes the sequencer to transition 213 from state 3 to state 2. 214 215What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state 216Date: November 2014 217KernelVersion: 3.19 218Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 219Description: (Read) Holds the current state of the sequencer. 220 221What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq 222Date: November 2014 223KernelVersion: 3.19 224Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 225Description: (RW) Holds the trace synchronization frequency value - must be 226 programmed with the various implementation behavior in mind. 227 228What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event 229Date: November 2014 230KernelVersion: 3.19 231Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 232Description: (RW) Defines an event that requests the insertion of a timestamp 233 into the trace stream. 234 235What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid 236Date: November 2014 237KernelVersion: 3.19 238Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 239Description: (RW) Holds the trace ID that will appear in the trace stream 240 coming from this trace entity. 241 242What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event 243Date: November 2014 244KernelVersion: 3.19 245Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 246Description: (RW) Define the event that controls the trigger. 247 248What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu 249Date: October 2015 250KernelVersion: 4.4 251Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 252Description: (RO) Holds the cpu number this tracer is affined to. 253 254What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr 255Date: September 2015 256KernelVersion: 4.4 257Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 258Description: (RO) Print the content of the ETM Configuration Code register 259 (0x004). The value is read directly from the HW. 260 261What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer 262Date: September 2015 263KernelVersion: 4.4 264Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 265Description: (RO) Print the content of the ETM Configuration Code Extension 266 register (0x1e8). The value is read directly from the HW. 267 268What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr 269Date: September 2015 270KernelVersion: 4.4 271Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 272Description: (RO) Print the content of the ETM System Configuration 273 register (0x014). The value is read directly from the HW. 274 275What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr 276Date: September 2015 277KernelVersion: 4.4 278Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 279Description: (RO) Print the content of the ETM ID register (0x1e4). The 280 value is read directly from the HW. 281 282What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr 283Date: September 2015 284KernelVersion: 4.4 285Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 286Description: (RO) Print the content of the ETM Main Control register (0x000). 287 The value is read directly from the HW. 288 289What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr 290Date: September 2015 291KernelVersion: 4.4 292Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 293Description: (RO) Print the content of the ETM Trace ID register (0x200). 294 The value is read directly from the HW. 295 296What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr 297Date: September 2015 298KernelVersion: 4.4 299Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 300Description: (RO) Print the content of the ETM Trace Enable Event register 301 (0x020). The value is read directly from the HW. 302 303What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr 304Date: September 2015 305KernelVersion: 4.4 306Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 307Description: (RO) Print the content of the ETM Trace Start/Stop Conrol 308 register (0x018). The value is read directly from the HW. 309 310What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1 311Date: September 2015 312KernelVersion: 4.4 313Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 314Description: (RO) Print the content of the ETM Enable Conrol #1 315 register (0x024). The value is read directly from the HW. 316 317What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2 318Date: September 2015 319KernelVersion: 4.4 320Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 321Description: (RO) Print the content of the ETM Enable Conrol #2 322 register (0x01c). The value is read directly from the HW. 323