1What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source 2Date: November 2014 3KernelVersion: 3.19 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Enable/disable tracing on this specific trace entiry. 6 Enabling a source implies the source has been configured 7 properly and a sink has been identidifed for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/status 12Date: November 2014 13KernelVersion: 3.19 14Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15Description: (R) List various control and status registers. The specific 16 layout and content is driver specific. 17 18What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx 19Date: November 2014 20KernelVersion: 3.19 21Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 22Description: Select which address comparator or pair (of comparators) to 23 work with. 24 25What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype 26Date: November 2014 27KernelVersion: 3.19 28Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 29Description: (RW) Used in conjunction with @addr_idx. Specifies 30 characteristics about the address comparator being configure, 31 for example the access type, the kind of instruction to trace, 32 processor contect ID to trigger on, etc. Individual fields in 33 the access type register may vary on the version of the trace 34 entity. 35 36What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range 37Date: November 2014 38KernelVersion: 3.19 39Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 40Description: (RW) Used in conjunction with @addr_idx. Specifies the range of 41 addresses to trigger on. Inclusion or exclusion is specificed 42 in the corresponding access type register. 43 44What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single 45Date: November 2014 46KernelVersion: 3.19 47Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 48Description: (RW) Used in conjunction with @addr_idx. Specifies the single 49 address to trigger on, highly influenced by the configuration 50 options of the corresponding access type register. 51 52What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start 53Date: November 2014 54KernelVersion: 3.19 55Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 56Description: (RW) Used in conjunction with @addr_idx. Specifies the single 57 address to start tracing on, highly influenced by the 58 configuration options of the corresponding access type register. 59 60What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop 61Date: November 2014 62KernelVersion: 3.19 63Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 64Description: (RW) Used in conjunction with @addr_idx. Specifies the single 65 address to stop tracing on, highly influenced by the 66 configuration options of the corresponding access type register. 67 68What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx 69Date: November 2014 70KernelVersion: 3.19 71Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 72Description: (RW) Specifies the counter to work on. 73 74What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event 75Date: November 2014 76KernelVersion: 3.19 77Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 78Description: (RW) Used in conjunction with cntr_idx, give access to the 79 counter event register. 80 81What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val 82Date: November 2014 83KernelVersion: 3.19 84Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 85Description: (RW) Used in conjunction with cntr_idx, give access to the 86 counter value register. 87 88What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val 89Date: November 2014 90KernelVersion: 3.19 91Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 92Description: (RW) Used in conjunction with cntr_idx, give access to the 93 counter reload value register. 94 95What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event 96Date: November 2014 97KernelVersion: 3.19 98Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 99Description: (RW) Used in conjunction with cntr_idx, give access to the 100 counter reload event register. 101 102What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx 103Date: November 2014 104KernelVersion: 3.19 105Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 106Description: (RW) Specifies the index of the context ID register to be 107 selected. 108 109What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask 110Date: November 2014 111KernelVersion: 3.19 112Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 113Description: (RW) Mask to apply to all the context ID comparator. 114 115What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid 116Date: November 2014 117KernelVersion: 3.19 118Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 119Description: (RW) Used with the ctxid_idx, specify with context ID to trigger 120 on. 121 122What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event 123Date: November 2014 124KernelVersion: 3.19 125Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 126Description: (RW) Defines which event triggers a trace. 127 128What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr 129Date: November 2014 130KernelVersion: 3.19 131Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 132Description: (RW) Gives access to the ETM status register, which holds 133 programming information and status on certains events. 134 135What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level 136Date: November 2014 137KernelVersion: 3.19 138Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 139Description: (RW) Number of byte left in the fifo before considering it full. 140 Depending on the tracer's version, can also hold threshold for 141 data suppression. 142 143What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode 144Date: November 2014 145KernelVersion: 3.19 146Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 147Description: (RW) Interface with the driver's 'mode' field, controlling 148 various aspect of the trace entity such as time stamping, 149 context ID size and cycle accurate tracing. Driver specific 150 and bound to change depending on the driver. 151 152What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp 153Date: November 2014 154KernelVersion: 3.19 155Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 156Description: (R) Provides the number of address comparators pairs accessible 157 on a trace unit, as specified by bit 3:0 of register ETMCCR. 158 159What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr 160Date: November 2014 161KernelVersion: 3.19 162Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 163Description: (R) Provides the number of counters accessible on a trace unit, 164 as specified by bit 15:13 of register ETMCCR. 165 166What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp 167Date: November 2014 168KernelVersion: 3.19 169Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 170Description: (R) Provides the number of context ID comparator available on a 171 trace unit, as specified by bit 25:24 of register ETMCCR. 172 173What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset 174Date: November 2014 175KernelVersion: 3.19 176Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 177Description: (W) Cancels all configuration on a trace unit and set it back 178 to its boot configuration. 179 180What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event 181Date: November 2014 182KernelVersion: 3.19 183Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 184Description: (RW) Defines the event that causes the sequencer to transition 185 from state 1 to state 2. 186 187What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event 188Date: November 2014 189KernelVersion: 3.19 190Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 191Description: (RW) Defines the event that causes the sequencer to transition 192 from state 1 to state 3. 193 194What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event 195Date: November 2014 196KernelVersion: 3.19 197Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 198Description: (RW) Defines the event that causes the sequencer to transition 199 from state 2 to state 1. 200 201What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event 202Date: November 2014 203KernelVersion: 3.19 204Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 205Description: (RW) Defines the event that causes the sequencer to transition 206 from state 2 to state 3. 207 208What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event 209Date: November 2014 210KernelVersion: 3.19 211Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 212Description: (RW) Defines the event that causes the sequencer to transition 213 from state 3 to state 1. 214 215What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event 216Date: November 2014 217KernelVersion: 3.19 218Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 219Description: (RW) Defines the event that causes the sequencer to transition 220 from state 3 to state 2. 221 222What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state 223Date: November 2014 224KernelVersion: 3.19 225Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 226Description: (R) Holds the current state of the sequencer. 227 228What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq 229Date: November 2014 230KernelVersion: 3.19 231Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 232Description: (RW) Holds the trace synchronization frequency value - must be 233 programmed with the various implementation behavior in mind. 234 235What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event 236Date: November 2014 237KernelVersion: 3.19 238Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 239Description: (RW) Defines an event that requests the insertion of a timestamp 240 into the trace stream. 241 242What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid 243Date: November 2014 244KernelVersion: 3.19 245Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 246Description: (RW) Holds the trace ID that will appear in the trace stream 247 coming from this trace entity. 248 249What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event 250Date: November 2014 251KernelVersion: 3.19 252Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 253Description: (RW) Define the event that controls the trigger. 254