xref: /linux/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp (revision ec8a42e7343234802b9054874fe01810880289ce)
1What:		/sys/devices/platform/firmware\:zynqmp-firmware/ggs*
2Date:		March 2020
3KernelVersion:	5.6
4Contact:	"Jolly Shah" <jollys@xilinx.com>
5Description:
6		Read/Write PMU global general storage register value,
7		GLOBAL_GEN_STORAGE{0:3}.
8		Global general storage register that can be used
9		by system to pass information between masters.
10
11		The register is reset during system or power-on
12		resets. Three registers are used by the FSBL and
13		other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
14
15		Usage::
16
17		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18		    # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
19
20		Example::
21
22		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23		    # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
24
25Users:		Xilinx
26
27What:		/sys/devices/platform/firmware\:zynqmp-firmware/pggs*
28Date:		March 2020
29KernelVersion:	5.6
30Contact:	"Jolly Shah" <jollys@xilinx.com>
31Description:
32		Read/Write PMU persistent global general storage register
33		value, PERS_GLOB_GEN_STORAGE{0:3}.
34		Persistent global general storage register that
35		can be used by system to pass information between
36		masters.
37
38		This register is only reset by the power-on reset
39		and maintains its value through a system reset.
40		Four registers are used by the FSBL and other Xilinx
41		software products: PERS_GLOB_GEN_STORAGE{4:7}.
42		Register is reset only by a POR reset.
43
44		Usage::
45
46		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47		    # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
48
49		Example::
50
51		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
52		    # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
53
54Users:		Xilinx
55
56What:		/sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope
57Date:		March 2020
58KernelVersion:	5.6
59Contact:	"Jolly Shah" <jollys@xilinx.com>
60Description:
61		This sysfs interface allows to set the shutdown scope for the
62		next shutdown request. When the next shutdown is performed, the
63		platform specific portion of PSCI-system_off can use the chosen
64		shutdown scope.
65
66		Following are available shutdown scopes(subtypes):
67
68		subsystem:
69				Only the APU along with all of its peripherals
70				not used by other processing units will be
71				shut down. This may result in the FPD power
72				domain being shut down provided that no other
73				processing unit uses FPD peripherals or DRAM.
74		ps_only:
75				The complete PS will be shut down, including the
76				RPU, PMU, etc.  Only the PL domain (FPGA)
77				remains untouched.
78		system:
79				The complete system/device is shut down.
80
81		Usage::
82
83		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope
84		    # echo <scope> > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope
85
86		Example::
87
88		    # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope
89		    # echo "subsystem" > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope
90
91Users:		Xilinx
92
93What:		/sys/devices/platform/firmware\:zynqmp-firmware/health_status
94Date:		March 2020
95KernelVersion:	5.6
96Contact:	"Jolly Shah" <jollys@xilinx.com>
97Description:
98		This sysfs interface allows to set the health status. If PMUFW
99		is compiled with CHECK_HEALTHY_BOOT, it will check the healthy
100		bit on FPD WDT expiration. If healthy bit is set by a user
101		application running in Linux, PMUFW will do APU only restart. If
102		healthy bit is not set during FPD WDT expiration, PMUFW will do
103		system restart.
104
105		Usage:
106
107		Set healthy bit::
108
109		    # echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status
110
111		Unset healthy bit::
112
113		    # echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status
114
115Users:		Xilinx
116