1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_I2C_I2C_H 17 #define _SYS_I2C_I2C_H 18 19 /* 20 * General i2c definitions that should be shared between both userland and the 21 * kernel. Kernel device drivers include <sys/i2c/controller.h>, 22 * <sys/i2c/mux.h>, or <sys/i2c/client.h> depending on the type of device they 23 * are. Userland should generally use <libi2c.h> or <sys/i2c/ui2c.h> if it's the 24 * implementation of libi2c. 25 */ 26 27 #include <sys/stdint.h> 28 #include <sys/stdbool.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Different allowed values for I2C and SMBus speeds. In the future, we'll 36 * determine how I3C based options like different supported clock rates and 37 * SDR/DDR fit in here. 38 */ 39 typedef enum { 40 /* 41 * 100 kHz Standard operation. 42 */ 43 I2C_SPEED_STD = 1 << 0, 44 /* 45 * 400 kHz Fast-mode operation. 46 */ 47 I2C_SPEED_FAST = 1 << 1, 48 /* 49 * 1000 MHz Fast-mode plus operation. 50 */ 51 I2C_SPEED_FPLUS = 1 << 2, 52 /* 53 * 3400 MHz High-speed mode operation. 54 */ 55 I2C_SPEED_HIGH = 1 << 3, 56 /* 57 * 5000 MHz Ultra-Fast mode operation. 58 */ 59 I2C_SPEED_ULTRA = 1 << 4 60 } i2c_speed_t; 61 62 /* 63 * Different types of controllers. 64 */ 65 typedef enum { 66 I2C_CTRL_TYPE_I2C = 1, 67 I2C_CTRL_TYPE_I3C, 68 I2C_CTRL_TYPE_SMBUS 69 } i2c_ctrl_type_t; 70 71 /* 72 * This represents the series of errors that can be generated by the various I2C 73 * APIs. These are grouped into several different units that cover behavior 74 * specific to the core (impacting everything) to properties, user-specific 75 * behavior, kernel driver clients, etc. 76 */ 77 typedef enum { 78 I2C_CORE_E_OK = 0, 79 /* 80 * Indicates that the controller I/O failed. The reason is specified in 81 * the controller error. 82 */ 83 I2C_CORE_E_CONTROLLER, 84 /* 85 * The following pair indicate that a given address class or value for 86 * an address within a valid address class are wrong. 87 */ 88 I2C_CORE_E_BAD_ADDR_TYPE, 89 I2C_CORE_E_BAD_ADDR, 90 /* 91 * This indicates that the requested address type, while valid, is not 92 * supported. For example, trying to send to a 10-bit address on a 93 * controller that does not support it. 94 */ 95 I2C_CORE_E_UNSUP_ADDR_TYPE, 96 /* 97 * Indicates that the address in question is reserved by a corresponding 98 * specification. 99 */ 100 I2C_CORE_E_ADDR_RSVD, 101 /* 102 * Indicates that the address in question is already in use and 103 * therefore cannot be used. 104 */ 105 I2C_CORE_E_ADDR_IN_USE, 106 /* 107 * Indicates that the address could be used, but it has exceeded the 108 * per-address usage count. This usually represents a place where the 109 * kernel can be improved. 110 */ 111 I2C_CORE_E_ADDR_REFCNT, 112 /* 113 * Indicates that there is no device with the specified address. 114 */ 115 I2C_CORE_E_UNKNOWN_ADDR, 116 /* 117 * Indicates that the request type can't be translated to something the 118 * underlying controller actually supports. For example, this would 119 * cover trying to translate certain kinds of I2C requests to an SMBus 120 * controller that supports limited types of operations or vice versa. 121 */ 122 I2C_CORE_E_CANT_XLATE_REQ, 123 /* 124 * This indicates that a request had neither a read nor a write and 125 * therefore cannot continue. This constraint on I/O may be lifted in 126 * the future. 127 */ 128 I2C_CORE_E_NEED_READ_OR_WRITE, 129 /* 130 * These indicate that invalid flags values, an invalid read length, or 131 * invalid write length was encountered. 132 */ 133 I2C_CORE_E_BAD_I2C_REQ_FLAGS, 134 I2C_CORE_E_BAD_I2C_REQ_READ_LEN, 135 I2C_CORE_E_BAD_I2C_REQ_WRITE_LEN, 136 /* 137 * These indicate similar situations in the SMBus request field. 138 */ 139 I2C_CORE_E_BAD_SMBUS_REQ_FLAGS, 140 I2C_CORE_E_BAD_SMBUS_READ_LEN, 141 I2C_CORE_E_BAD_SMBUS_WRITE_LEN, 142 I2C_CORE_E_BAD_SMBUS_OP, 143 /* 144 * Indicates that the controller does not support the requested SMBus 145 * operation. 146 */ 147 I2C_CORE_E_UNSUP_SMBUS_OP, 148 /* 149 * Indicates that the controller is already owned by someone and the 150 * caller asked not to block. 151 */ 152 I2C_CORE_E_LOCK_WOULD_BLOCK, 153 /* 154 * Indicates that the caller took a signal while waiting to acquire the 155 * controller. 156 */ 157 I2C_CORE_E_LOCK_WAIT_SIGNAL, 158 /* 159 * Indicates that a passed in nvlist was larger than the maximum value. 160 */ 161 I2C_IOCTL_E_NVL_TOO_BIG = 0x1000, 162 /* 163 * Indicates that the nvlist was not parseable. 164 */ 165 I2C_IOCTL_E_NVL_INVALID, 166 /* 167 * Indicates that the nvlist contained missing keys, keys that we don't 168 * know how to handle, and keys that are the wrong type. If this gets 169 * much more complex, the interface should change to the kgpio error 170 * style where there is an additional nvlist there. 171 */ 172 I2C_IOCTL_E_NVL_KEY_MISSING, 173 I2C_IOCTL_E_NVL_KEY_UNKNOWN, 174 I2C_IOCTL_E_NVL_KEY_BAD_TYPE, 175 /* 176 * Indicates that a pointer to user data inside of an ioctl (not the 177 * overall ioctl itself) was not valid and generated a fault. 178 */ 179 I2C_IOCTL_E_BAD_USER_DATA, 180 /* 181 * Indicates that there was no kernel memory available for the request. 182 */ 183 I2C_IOCTL_E_NO_KERN_MEM, 184 /* 185 * Indicates that a string that is being used for a device name or 186 * compatible array contains illegal characters or is too long. 187 */ 188 I2C_IOCTL_E_BAD_DEV_NAME, 189 /* 190 * Indicates that the length of the compatible range is longer than the 191 * system will allow to be set. 192 */ 193 I2C_IOCTL_E_COMPAT_LEN_RANGE, 194 /* 195 * Indicates that something went wrong with trying to deal with nexus 196 * related operations on a child. 197 */ 198 I2C_IOCTL_E_NEXUS, 199 /* 200 * Indicates that a nexus operations was attempted while trying to hold 201 * a bus lock. 202 */ 203 I2C_IOCTL_E_NO_BUS_LOCK_NEXUS, 204 /* 205 * Indicates that an ioctl operation could not be started because the 206 * client in question already has one in flight that requires the 207 * controller lock. 208 */ 209 I2C_IOCTL_E_IN_PROGRESS, 210 /* 211 * Indicates that the passed dev_info_t does not correspond to an i2c 212 * device. 213 */ 214 I2C_CLIENT_E_BAD_DIP = 0x2000, 215 /* 216 * Indicates that the regs[] index is invalid for the device. 217 */ 218 I2C_CLIENT_E_BAD_REG_IDX, 219 /* 220 * Indicates that the specific set of flags are invalid. 221 */ 222 I2C_CLIENT_E_BAD_CLAIM_FLAGS, 223 I2C_CLIENT_E_BAD_IO_FLAGS, 224 I2C_CLIENT_E_BAD_LOCK_FLAGS, 225 /* 226 * Indicates that the caller was interrupted while trying to get access 227 * to the client for I/O. 228 */ 229 I2C_CLIENT_E_SIGNAL, 230 /* 231 * Thee indicate that there are invalid values in the various register 232 * access attributes. 233 */ 234 I2C_CLIENT_E_BAD_REG_ATTR_VERS, 235 I2C_CLIENT_E_BAD_REG_ATTR_FLAGS, 236 I2C_CLIENT_E_BAD_REG_ATTR_RLEN, 237 I2C_CLIENT_E_BAD_REG_ATTR_ALEN, 238 I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN, 239 I2C_CLIENT_E_BAD_REG_ATTR_MAX, 240 /* 241 * Indicates that while the register attributes are supported, the 242 * underlying hardware cannot support them. 243 */ 244 I2C_CLIENT_E_REG_ALEN_UNSUP_BY_CTRL, 245 /* 246 * These indicate that I2C register operations were passed invalid 247 * values or that these values would lead to an overflow. 248 */ 249 I2C_CLIENT_E_BAD_REG_ADDR, 250 I2C_CLIENT_E_BAD_REG_COUNT, 251 I2C_CLIENT_E_REG_ADDR_OVERFLOW, 252 I2C_CLIENT_E_REG_IO_TOO_LARGE, 253 /* 254 * Indicates that the size in bytes is a partial number of registers. 255 */ 256 I2C_CLIENT_E_PARTIAL_REG, 257 /* 258 * Indicates that the client has tried to claim a shared address, but 259 * they actually own the address directly. 260 */ 261 I2C_CLIENT_E_CLAIM_OWNED_ADDR, 262 /* 263 * These two indicate that the property is unsupported by the device or 264 * a property ID that is unknown by the system. 265 */ 266 I2C_PROP_E_UNSUP = 0x3000, 267 I2C_PROP_E_UNKNOWN, 268 /* 269 * Indicates that the property can't be written to because it is 270 * read-only. 271 */ 272 I2C_PROP_E_READ_ONLY, 273 /* 274 * Indicates that the property buffer is too small. The second indicates 275 * that the property buffer is too large and doesn't make sense for the 276 * property. The latter is only relevant when setting a property. The 277 * former can be triggered in all property interfaces. 278 */ 279 I2C_PROP_E_SMALL_BUF, 280 I2C_PROP_E_TOO_BIG_BUF, 281 /* 282 * Indicates that the property value is invalid. 283 */ 284 I2C_PROP_E_BAD_VAL, 285 /* 286 * Indicates that the controller doesn't support setting properties. 287 */ 288 I2C_PROP_E_SET_UNSUP, 289 /* 290 * Indicates that the mux flag is unknown. 291 */ 292 I2C_MUX_E_BAD_FLAG = 0x4000 293 } i2c_errno_t; 294 295 /* 296 * These represent errors that the controller generates and/or detects while 297 * attempting to perform I/O. Some controllers provide relatively rich 298 * diagnostics as to what went wrong. Others, provide only generic classes of 299 * errors. Try to use the most specific error possible. 300 */ 301 typedef enum { 302 I2C_CTRL_E_OK = 0, 303 /* 304 * This is a generic class that represents something happened internal 305 * to the controller. In general, this should be used sparingly and only 306 * for something that only makes semantic sense on a single controller. 307 * This should not be a property of something related to I2C/SMBus/I3C 308 * directly. 309 */ 310 I2C_CTRL_E_INTERNAL, 311 /* 312 * This is a variant of the above that indicates a driver programming 313 * error violated a controller condition. 314 */ 315 I2C_CTRL_E_DRIVER, 316 /* 317 * Indicates that the controller was given a type of command that it 318 * does not support. For example, an SMBus 1.0 controller given an SMBus 319 * 2.0 command. The framework generally is the only tying that will 320 * return this error as drivers should not have to encounter them. 321 */ 322 I2C_CTRL_E_UNSUP_CMD, 323 /* 324 * Indicates that prior to trying to perform the operation, the 325 * controller detected that the bus was busy and after a timeout was 326 * unable to get control of the bus. 327 */ 328 I2C_CTRL_E_BUS_BUSY, 329 /* 330 * This error indicates that there was a no acknowledgement condition. 331 * This should be used both for 7-bit and 10-bit cases. Similarly, for 332 * now this should also be used for cases where no one acknowledges a 333 * general call. 334 */ 335 I2C_CTRL_E_ADDR_NACK, 336 /* 337 * This is a variant on the address NACK. This is used when the address 338 * has been acknowledged, but subsequent data has not been. Some devices 339 * may not be able to make the distinction. If they cannot, use the 340 * catch-all NACK below. 341 */ 342 I2C_CTRL_E_DATA_NACK, 343 /* 344 * This is a case where no NACK occurred, but the controller cannot be 345 * more specific as to where in the process it occurred. 346 */ 347 I2C_CTRL_E_NACK, 348 /* 349 * Indicates that the controller lost arbitration on the bus. A common 350 * cause for this is a data collision. 351 */ 352 I2C_CTRL_E_ARB_LOST, 353 /* 354 * Indicates that a device incorrectly issued an ACK when it was not 355 * expected in the operation. 356 */ 357 I2C_CTRL_E_BAD_ACK, 358 /* 359 * Indicates that the controller failed to successfully finish 360 * transmitting the command within the default request timeout. This 361 * results in the controller aborting the command. Callers cannot assume 362 * anything about the number of bytes that made it out onto the bus. 363 */ 364 I2C_CTRL_E_REQ_TO, 365 /* 366 * Indicates that an SMBus device returned a block read length that 367 * could not be supported by the device or is illegal according to the 368 * specification. For example, a 0 byte length or a length exceeding 32 369 * bytes for an SMBus 2.0 controller. 370 */ 371 I2C_CTRL_E_BAD_SMBUS_RLEN, 372 /* 373 * Indicates that an SMBus device held the clock low for too long to 374 * effectively trime out the transaction. This is different from the 375 * request timeout as it indicates something the target did. 376 */ 377 I2C_CTRL_E_SMBUS_CLOCK_LOW 378 } i2c_ctrl_error_t; 379 380 typedef struct { 381 i2c_errno_t i2c_error; 382 i2c_ctrl_error_t i2c_ctrl; 383 } i2c_error_t; 384 385 /* 386 * General maximum length for an i2c related name, including the NUL. 387 */ 388 #define I2C_NAME_MAX 32 389 390 typedef enum i2c_addr_type { 391 I2C_ADDR_7BIT = 0, 392 I2C_ADDR_10BIT 393 } i2c_addr_type_t; 394 395 /* 396 * This represents the general form of our i2c addresses and what the nexus will 397 * give client devices and drivers in the form of regs[]. 398 */ 399 typedef struct i2c_addr { 400 uint16_t ia_type; 401 uint16_t ia_addr; 402 } i2c_addr_t; 403 404 /* 405 * This indicates where an address came from. 406 */ 407 typedef enum i2c_addr_source { 408 /* 409 * Indicates that this came from the devices reg[] array. It was either 410 * put there as part of discovering information about the system by the 411 * platform (e.g. ACPI, device tree, etc.) or based on a user's specific 412 * device creation. 413 */ 414 I2C_ADDR_SOURCE_REG = 1, 415 /* 416 * Indicates that the address was one that the driver claimed. 417 */ 418 I2C_ADDR_SOURCE_CLAIMED, 419 /* 420 * Indicates that the address was one that the driver claimed and is 421 * shared across multiple instances. 422 */ 423 I2C_ADDR_SOURCE_SHARED 424 } i2c_addr_source_t; 425 426 /* 427 * Well-known and other special addresses. I2C reserves several addresses for 428 * special purposes. SMBus has a more extensive of nominal assignments, but 429 * things definitely stomp in that space. 430 */ 431 typedef enum { 432 I2C_RSVD_ADDR_GEN_CALL = 0x00, 433 I2C_RSVD_ADDR_C_BUS = 0x01, 434 I2C_RSVD_ADDR_DIFF_BUS = 0x02, 435 I2C_RSVD_ADDR_FUTURE = 0x03, 436 I2C_RSVD_ADDR_HS_0 = 0x04, 437 I2C_RSVD_ADDR_HS_1 = 0x05, 438 I2C_RSVD_ADDR_HS_2 = 0x06, 439 I2C_RSVD_ADDR_HS_3 = 0x07, 440 I2C_RSVD_ADDR_10B_0 = 0x78, 441 I2C_RSVD_ADDR_10B_1 = 0x79, 442 I2C_RSVD_ADDR_10B_2 = 0x7a, 443 I2C_RSVD_ADDR_10B_3 = 0x7b, 444 I2C_RSVD_ADDR_DID_0 = 0x7c, 445 I2C_RSVD_ADDR_DID_1 = 0x7d, 446 I2C_RSVD_ADDR_DID_2 = 0x7e, 447 I2C_RSVD_ADDR_DID_3 = 0x7f 448 } i2c_rsvd_addr_t; 449 450 /* 451 * SMBus 2.0 controllers have a maximum byte size of 32 bytes. SMBus 3.0 452 * increases that to a maximum of 255 bytes. As such we size our maximum request 453 * sizes at 256 bytes in our structures. 454 */ 455 #define SMBUS_V2_MAX_BLOCK 32 456 #define SMBUS_V3_MAX_BLOCK 255 457 #define I2C_REQ_MAX 256 458 459 typedef enum smbus_op { 460 SMBUS_OP_QUICK_COMMAND, 461 SMBUS_OP_SEND_BYTE, 462 SMBUS_OP_RECV_BYTE, 463 SMBUS_OP_WRITE_BYTE, 464 SMBUS_OP_READ_BYTE, 465 SMBUS_OP_WRITE_WORD, 466 SMBUS_OP_READ_WORD, 467 SMBUS_OP_PROCESS_CALL, 468 SMBUS_OP_WRITE_BLOCK, 469 SMBUS_OP_READ_BLOCK, 470 /* Added in SMBUS 2.0 */ 471 SMBUS_OP_HOST_NOTIFY, 472 SMBUS_OP_BLOCK_PROCESS_CALL, 473 /* Added in SMBUS 3.x */ 474 SMBUS_OP_WRITE_U32, 475 SMBUS_OP_READ_U32, 476 SMBUS_OP_WRITE_U64, 477 SMBUS_OP_READ_U64, 478 /* I2C Compatibility */ 479 SMBUS_OP_I2C_WRITE_BLOCK, 480 SMBUS_OP_I2C_READ_BLOCK 481 } smbus_op_t; 482 483 typedef enum { 484 /* 485 * Indicates that regardless of whether or not interrupts are supported, 486 * this request should be polled. 487 */ 488 I2C_IO_REQ_F_POLL = 1 << 0, 489 /* 490 * Indicates that this zero-byte I/O quick command is a write. If this 491 * flag is not set then a quick command is a read. 492 */ 493 I2C_IO_REQ_F_QUICK_WRITE = 1 << 1, 494 } i2c_req_flags_t; 495 496 typedef struct smbus_req { 497 i2c_error_t smbr_error; 498 smbus_op_t smbr_op; 499 i2c_req_flags_t smbr_flags; 500 i2c_addr_t smbr_addr; 501 uint16_t smbr_wlen; 502 uint16_t smbr_rlen; 503 uint8_t smbr_cmd; 504 uint8_t smbr_wdata[I2C_REQ_MAX]; 505 uint8_t smbr_rdata[I2C_REQ_MAX]; 506 } smbus_req_t; 507 508 typedef struct i2c_req { 509 i2c_error_t ir_error; 510 i2c_req_flags_t ir_flags; 511 i2c_addr_t ir_addr; 512 uint16_t ir_wlen; 513 uint16_t ir_rlen; 514 uint8_t ir_wdata[I2C_REQ_MAX]; 515 uint8_t ir_rdata[I2C_REQ_MAX]; 516 } i2c_req_t; 517 518 typedef enum i2c_prop_type { 519 /* 520 * A property that is a standard, scalar uint32_t. 521 */ 522 I2C_PROP_TYPE_U32, 523 /* 524 * A property that fits in a uint32_t, but represents a bitfield of 525 * values. 526 */ 527 I2C_PROP_TYPE_BIT32 528 } i2c_prop_type_t; 529 530 typedef enum i2c_prop_perm { 531 I2C_PROP_PERM_RO, 532 I2C_PROP_PERM_RW 533 } i2c_prop_perm_t; 534 535 typedef struct i2c_prop_u32_range { 536 uint32_t ipur_min; 537 uint32_t ipur_max; 538 } i2c_prop_u32_range_t; 539 540 typedef union i2c_prop_val_range { 541 uint32_t ipvr_bit32; 542 i2c_prop_u32_range_t ipvr_u32; 543 } i2c_prop_val_range_t; 544 545 typedef struct i2c_prop_range { 546 uint32_t ipr_count; 547 i2c_prop_type_t ipr_type; 548 i2c_prop_val_range_t ipr_range[]; 549 } i2c_prop_range_t; 550 551 /* 552 * This enumeration contains a list of the properties that are supported. 553 * 554 * In earlier designs we had an initial set of properties for setup and hold 555 * time related aspects, but controllers don't really have a uniform design 556 * here. Some offer different values for RX and TX. Some offer only a single 557 * value. 558 */ 559 typedef enum i2c_prop { 560 /* 561 * This is a uint32_t that is covered by the i2c_speed_t. 562 */ 563 I2C_PROP_BUS_SPEED = 0, 564 /* 565 * This is a uint32_t that indicates the number of ports the device has. 566 */ 567 I2C_PROP_NPORTS, 568 /* 569 * This indicates the controller's type, which is covered by the 570 * i2c_ctrl_type_t. 571 */ 572 I2C_PROP_TYPE, 573 /* 574 * SMBus operations that are supported by the controller. This is a 575 * uint32_t that covers smbus_prop_op_t. 576 */ 577 SMBUS_PROP_SUP_OPS, 578 /* 579 * Maximum sizes that a controller can support for performing different 580 * kinds of I/O. We expect that most I2C controllers will only support a 581 * 582 * single read/write buffer. For SMBus controllers, they should specify 583 * the maximum block size. This covers block reads, writes, and calls. 584 * If a controller supports an I2C mode with a different maximum, then 585 * it can additionally specify the I2c properties. 586 */ 587 I2C_PROP_MAX_READ, 588 I2C_PROP_MAX_WRITE, 589 SMBUS_PROP_MAX_BLOCK, 590 /* 591 * Properties for different timing parameters in I2C devices. These are 592 * all uint32_t values generally in clock cycles. 593 */ 594 I2C_PROP_STD_SCL_HIGH, 595 I2C_PROP_STD_SCL_LOW, 596 I2C_PROP_FAST_SCL_HIGH, 597 I2C_PROP_FAST_SCL_LOW, 598 I2C_PROP_HIGH_SCL_HIGH, 599 I2C_PROP_HIGH_SCL_LOW 600 } i2c_prop_t; 601 602 typedef enum smbus_prop_op { 603 SMBUS_PROP_OP_QUICK_COMMAND = 1 << SMBUS_OP_QUICK_COMMAND, 604 SMBUS_PROP_OP_SEND_BYTE = 1 << SMBUS_OP_SEND_BYTE, 605 SMBUS_PROP_OP_RECV_BYTE = 1 << SMBUS_OP_RECV_BYTE, 606 SMBUS_PROP_OP_WRITE_BYTE = 1 << SMBUS_OP_WRITE_BYTE, 607 SMBUS_PROP_OP_READ_BYTE = 1 << SMBUS_OP_READ_BYTE, 608 SMBUS_PROP_OP_WRITE_WORD = 1 << SMBUS_OP_WRITE_WORD, 609 SMBUS_PROP_OP_READ_WORD = 1 << SMBUS_OP_READ_WORD, 610 SMBUS_PROP_OP_PROCESS_CALL = 1 << SMBUS_OP_PROCESS_CALL, 611 SMBUS_PROP_OP_WRITE_BLOCK = 1 << SMBUS_OP_WRITE_BLOCK, 612 SMBUS_PROP_OP_READ_BLOCK = 1 << SMBUS_OP_READ_BLOCK, 613 SMBUS_PROP_OP_HOST_NOTIFY = 1 << SMBUS_OP_HOST_NOTIFY, 614 SMBUS_PROP_OP_BLOCK_PROCESS_CALL = 1 << SMBUS_OP_BLOCK_PROCESS_CALL, 615 SMBUS_PROP_OP_WRITE_U32 = 1 << SMBUS_OP_WRITE_U32, 616 SMBUS_PROP_OP_READ_U32 = 1 << SMBUS_OP_READ_U32, 617 SMBUS_PROP_OP_WRITE_U64 = 1 << SMBUS_OP_WRITE_U64, 618 SMBUS_PROP_OP_READ_U64 = 1 << SMBUS_OP_READ_U64, 619 SMBUS_PROP_OP_I2C_WRITE_BLOCK = 1 << SMBUS_OP_I2C_WRITE_BLOCK, 620 SMBUS_PROP_OP_I2C_READ_BLOCK = 1 << SMBUS_OP_I2C_READ_BLOCK 621 } smbus_prop_op_t; 622 623 /* 624 * The size in bytes of the maximum property name (including the NUL) and the 625 * largest data size. 626 */ 627 #define I2C_PROP_NAME_MAX 32 628 #define I2C_PROP_SIZE_MAX 256 629 630 #ifdef __cplusplus 631 } 632 #endif 633 634 #endif /* _SYS_I2C_I2C_H */ 635