1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_GPIO_ZEN_GPIO_H 17 #define _SYS_GPIO_ZEN_GPIO_H 18 19 /* 20 * AMD Zen GPIO attribute definitions. 21 * 22 * This covers most attributes for Zen 1 - 4 based GPIOs (and possibly earlier 23 * families). Most attributes are passed through for user consumption with a few 24 * exceptions right now around interrupt and wake control as those are not 25 * things that we expect to be manipulated. 26 */ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * These five attributes are used to communicate basic identifying information 34 * about the GPIO. 35 * 36 * KGPIO_ATTR_NAME -- ro 37 * string 38 * 39 * This contains the GPIO's name. This is the GPIO portion of the name that the 40 * PPR uses. 41 * 42 * ZEN_GPIO_ATTR_PAD_NAME -- ro 43 * string 44 * 45 * This contains the name of the pad that the GPIO uses according to the PPR. 46 * This may match the GPIO's name, but may be different. 47 * 48 * ZEN_GPIO_ATTR_PAD_TYPE -- ro 49 * uint32_t -- zen_gpio_pad_type_t 50 * 51 * This describes the type of pad that we have. 52 * 53 * ZEN_GPIO_ATTR_PIN -- ro 54 * string 55 * 56 * This contains the name of the pin on the socket. 57 * 58 * ZEN_GPIO_ATTR_CAPS -- ro 59 * 60 * This contains some of the internal notes on the capabilities the pin 61 * theoretially has. 62 */ 63 #define ZEN_GPIO_ATTR_PAD_NAME "zen:pad_name" 64 #define ZEN_GPIO_ATTR_PAD_TYPE "zen:pad_type" 65 #define ZEN_GPIO_ATTR_PIN "zen:pin" 66 #define ZEN_GPIO_ATTR_CAPS "zen:caps" 67 68 typedef enum { 69 ZEN_GPIO_PAD_TYPE_GPIO, 70 ZEN_GPIO_PAD_TYPE_SD, 71 ZEN_GPIO_PAD_TYPE_I2C, 72 ZEN_GPIO_PAD_TYPE_I3C 73 } zen_gpio_pad_type_t; 74 75 typedef enum { 76 /* 77 * Indicates that the GPIO supports interrupts. 78 */ 79 ZEN_GPIO_C_AGPIO = 1 << 0, 80 /* 81 * Indicates that the GPIO is part of a remote block, which 82 * means more shenanigans to get it to work. 83 */ 84 ZEN_GPIO_C_REMOTE = 1 << 1 85 } zen_gpio_cap_t; 86 87 /* 88 * ZEN_GPIO_ATTR_OUTPUT_DRIVER -- ro 89 * uint32_t -- zen_gpio_driver_mode_t 90 * 91 * This describes the mode of the output driver for a given GPIO. Note, in Zen 4 92 * this is configurable for I3C based GPIOs. 93 */ 94 #define ZEN_GPIO_ATTR_OUTPUT_DRIVER "zen:output_driver" 95 typedef enum { 96 ZEN_GPIO_DRIVER_UNKNOWN, 97 ZEN_GPIO_DRIVER_PUSH_PULL, 98 ZEN_GPIO_DRIVER_OPEN_DRAIN 99 } zen_gpio_driver_mode_t; 100 101 /* 102 * ZEN_GPIO_ATTR_OUTPUT -- rw 103 * uint32_t -- zen_gpio_output_t 104 * 105 * This controls what the GPIO's output is. For open-drain style pins, the only 106 * options that are valid are disabled and low. 107 */ 108 #define ZEN_GPIO_ATTR_OUTPUT "zen:output" 109 typedef enum { 110 ZEN_GPIO_OUTPUT_DISABLED, 111 ZEN_GPIO_OUTPUT_LOW, 112 ZEN_GPIO_OUTPUT_HIGH 113 } zen_gpio_output_t; 114 115 /* 116 * ZEN_GPIO_ATTR_INPUT -- ro 117 * uint32_t -- zen_gpio_input_t 118 * 119 * This describes the current input value of the pin. 120 */ 121 #define ZEN_GPIO_ATTR_INPUT "zen:input" 122 typedef enum { 123 ZEN_GPIO_INPUT_LOW, 124 ZEN_GPIO_INPUT_HIGH 125 } zen_gpio_input_t; 126 127 /* 128 * ZEN_GPIO_ATTR_VOLTAGE -- ro 129 * zen_gpio_voltage_t 130 * 131 * This describes the different type of voltages that a given pin supports. 132 * Note, all the pad registers are not driven as part of the GPIO driver and 133 * therefore changes to this are not supported (today). 134 */ 135 #define ZEN_GPIO_ATTR_VOLTAGE "zen:voltage" 136 137 typedef enum { 138 ZEN_GPIO_V_UNKNOWN = 0, 139 ZEN_GPIO_V_1P1_S3 = 1 << 0, 140 ZEN_GPIO_V_1P8_S5 = 1 << 1, 141 ZEN_GPIO_V_1P8_S0 = 1 << 2, 142 ZEN_GPIO_V_3P3_S5 = 1 << 3, 143 ZEN_GPIO_V_3P3_S0 = 1 << 4 144 } zen_gpio_voltage_t; 145 146 /* 147 * ZEN_GPIO_ATTR_PULL -- rw 148 * uint32_t -- zen_gpio_pull_t 149 * 150 * This controls the pull and strength of a GPIO. Note, some pins require a 151 * strength to be specified where as others do not support this. This varies 152 * based on the specific chip and socket. 153 */ 154 #define ZEN_GPIO_ATTR_PULL "zen:pull" 155 156 typedef enum { 157 ZEN_GPIO_PULL_DISABLED = 0, 158 ZEN_GPIO_PULL_DOWN, 159 ZEN_GPIO_PULL_UP_4K, 160 ZEN_GPIO_PULL_UP_8K, 161 ZEN_GPIO_PULL_UP, 162 /* 163 * The following are possible values, but not ones that we allow to be 164 * set. That is, these are illegal combinations, but there is nothing 165 * that stops hardware from being able to shout them at us. 166 */ 167 ZEN_GPIO_PULL_DOWN_UP, 168 ZEN_GPIO_PULL_DOWN_UP_4K, 169 ZEN_GPIO_PULL_DOWN_UP_8K 170 } zen_gpio_pull_t; 171 172 /* 173 * ZEN_GPIO_ATTR_DRIVE_STRENGTH -- rw 174 * uint32_t -- zen_gpio_drive_strength_t 175 */ 176 #define ZEN_GPIO_ATTR_DRIVE_STRENGTH "zen:drive_strength" 177 178 typedef enum { 179 ZEN_GPIO_DRIVE_UNKNOWN, 180 ZEN_GPIO_DRIVE_40R, 181 ZEN_GPIO_DRIVE_60R, 182 ZEN_GPIO_DRIVE_80R 183 } zen_gpio_drive_strength_t; 184 185 /* 186 * These three attributes are used to control the debounce configuration which 187 * ties into interrupt generation. 188 * 189 * ZEN_GPIO_ATTR_DEBOUNCE_MODE -- rw 190 * uint32 -- zen_gpio_debounce_mode_t 191 * 192 * This controls how the debounce logic works internally and what actions should 193 * be taken. 194 * 195 * ZEN_GPIO_ATTR_DEBOUNCE_UNIT -- rw 196 * uint32_t -- zen_gpio_debounce_unit_t 197 * 198 * This controls the unit and graunlarity. This is phrased in terms of units of 199 * the RTC clock and translates into 61 us, 244 us, 15.6 ms, and 62.5 ms. 200 * 201 * ZEN_GPIO_ATTR_DEBOUNCE_COUNT -- rw 202 * uint32_t 203 * 204 * This is the number of debounce count units should be used. This is capped to 205 * a 4-bit value. 206 */ 207 #define ZEN_GPIO_ATTR_DEBOUNCE_MODE "zen:debounce_mode" 208 #define ZEN_GPIO_ATTR_DEBOUNCE_UNIT "zen:debounce_unit" 209 #define ZEN_GPIO_ATTR_DEBOUNCE_COUNT "zen:debounce_count" 210 211 typedef enum { 212 ZEN_GPIO_DEBOUNCE_MODE_NONE = 0, 213 ZEN_GPIO_DEBOUNCE_MODE_KEEP_LOW, 214 ZEN_GPIO_DEBOUNCE_MODE_KEEP_HIGH, 215 ZEN_GPIO_DEBOUNCE_MODE_REMOVE, 216 } zen_gpio_debounce_mode_t; 217 218 typedef enum { 219 ZEN_GPIO_DEBOUNCE_UNIT_2RTC = 0, 220 ZEN_GPIO_DEBOUNCE_UNIT_8RTC, 221 ZEN_GPIO_DEBOUNCE_UNIT_512RTC, 222 ZEN_GPIO_DEBOUNCE_UNIT_2048RTC, 223 } zen_gpio_debounce_unit_t; 224 225 /* 226 * ZEN_GPIO_ATTR_TRIGGER_MODE -- rw -- uint32_t zen_gpio_trigger_t enum 227 * 228 * This attribute controls how the device generates interrupts. In particular, 229 * this covers whether it's edge or level triggered and what constitutes and 230 * edge. Debounce logic still applies. 231 */ 232 #define ZEN_GPIO_ATTR_TRIGGER_MODE "zen:trigger_mode" 233 234 typedef enum { 235 ZEN_GPIO_TRIGGER_UNKNOWN = 0, 236 ZEN_GPIO_TRIGGER_EDGE_HIGH, 237 ZEN_GPIO_TRIGGER_EDGE_LOW, 238 ZEN_GPIO_TRIGGER_EDGE_BOTH, 239 ZEN_GPIO_TRIGGER_LEVEL_HIGH, 240 ZEN_GPIO_TRIGGER_LEVEL_LOW 241 } zen_gpio_trigger_t; 242 243 /* 244 * ZEN_GPIO_ATTR_STATUS -- ro 245 * uint32_t -- zen_gpio_status_t 246 * 247 * This enumeration is a bitfield of status flags that the gpio has. 248 */ 249 #define ZEN_GPIO_ATTR_STATUS "zen:status" 250 251 typedef enum { 252 ZEN_GPIO_STATUS_WAKE = 1 << 0, 253 ZEN_GPIO_STATUS_INTR = 1 << 1, 254 } zen_gpio_status_t; 255 256 /* 257 * ZEN_GPIO_ATTR_RAW_REG -- ro 258 * uint32_t 259 * 260 * This is an attribute which includes the raw register value for the gpio 261 * register. This is here for debugging purposes. 262 */ 263 #define ZEN_GPIO_ATTR_RAW_REG "zen:raw_reg" 264 265 #ifdef __cplusplus 266 } 267 #endif 268 269 #endif /* _SYS_GPIO_ZEN_GPIO_H */ 270