1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_SW_H 29 #define _IXGBE_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/bitmap.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/disp.h> 71 #include <sys/fm/io/ddi.h> 72 #include "ixgbe_api.h" 73 74 #define MODULE_NAME "ixgbe" /* module name */ 75 76 #define IXGBE_FAILURE DDI_FAILURE 77 78 #define IXGBE_UNKNOWN 0x00 79 #define IXGBE_INITIALIZED 0x01 80 #define IXGBE_STARTED 0x02 81 #define IXGBE_SUSPENDED 0x04 82 #define IXGBE_STALL 0x08 83 #define IXGBE_ERROR 0x80 84 85 #define MAX_NUM_UNICAST_ADDRESSES 0x10 86 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 87 #define IXGBE_INTR_NONE 0 88 #define IXGBE_INTR_MSIX 1 89 #define IXGBE_INTR_MSI 2 90 #define IXGBE_INTR_LEGACY 3 91 92 #define IXGBE_POLL_NULL -1 93 94 #define MAX_COOKIE 18 95 #define MIN_NUM_TX_DESC 2 96 97 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 98 99 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 100 101 #define IXGBE_RX_STOPPED 0x1 102 103 /* 104 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 105 * supported silicon types. 106 */ 107 #define MAX_TX_QUEUE_NUM 128 108 #define MAX_RX_QUEUE_NUM 128 109 #define MAX_INTR_VECTOR 64 110 111 /* 112 * Maximum values for user configurable parameters 113 */ 114 #define MAX_RX_GROUP_NUM 1 115 #define MAX_TX_RING_SIZE 4096 116 #define MAX_RX_RING_SIZE 4096 117 118 #define MAX_RX_LIMIT_PER_INTR 4096 119 120 #define MAX_RX_COPY_THRESHOLD 9216 121 #define MAX_TX_COPY_THRESHOLD 9216 122 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 123 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 124 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 125 126 /* 127 * Minimum values for user configurable parameters 128 */ 129 #define MIN_RX_GROUP_NUM 1 130 #define MIN_TX_RING_SIZE 64 131 #define MIN_RX_RING_SIZE 64 132 133 #define MIN_MTU ETHERMIN 134 #define MIN_RX_LIMIT_PER_INTR 16 135 #define MIN_TX_COPY_THRESHOLD 0 136 #define MIN_RX_COPY_THRESHOLD 0 137 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 138 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 139 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 140 141 /* 142 * Default values for user configurable parameters 143 */ 144 #define DEFAULT_RX_GROUP_NUM 1 145 #define DEFAULT_TX_RING_SIZE 1024 146 #define DEFAULT_RX_RING_SIZE 1024 147 148 #define DEFAULT_MTU ETHERMTU 149 #define DEFAULT_RX_LIMIT_PER_INTR 256 150 #define DEFAULT_RX_COPY_THRESHOLD 128 151 #define DEFAULT_TX_COPY_THRESHOLD 512 152 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 153 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 154 #define DEFAULT_TX_RESCHED_THRESHOLD 128 155 #define DEFAULT_FCRTH 0x20000 156 #define DEFAULT_FCRTL 0x10000 157 #define DEFAULT_FCPAUSE 0xFFFF 158 159 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 160 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 161 #define DEFAULT_LSO_ENABLE B_TRUE 162 #define DEFAULT_MR_ENABLE B_TRUE 163 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 164 165 #define IXGBE_LSO_MAXLEN 65535 166 167 #define TX_DRAIN_TIME 200 168 #define RX_DRAIN_TIME 200 169 170 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 171 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 172 173 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */ 174 175 /* 176 * Extra register bit masks for 82598 177 */ 178 #define IXGBE_PCS1GANA_FDC 0x20 179 #define IXGBE_PCS1GANLP_LPFD 0x20 180 #define IXGBE_PCS1GANLP_LPHD 0x40 181 182 /* 183 * Defined for IP header alignment. 184 */ 185 #define IPHDR_ALIGN_ROOM 2 186 187 /* 188 * Bit flags for attach_progress 189 */ 190 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 191 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 192 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 193 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 194 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 195 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 196 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 197 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 198 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 199 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 200 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 201 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 202 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */ 203 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */ 204 205 #define PROP_DEFAULT_MTU "default_mtu" 206 #define PROP_FLOW_CONTROL "flow_control" 207 #define PROP_TX_QUEUE_NUM "tx_queue_number" 208 #define PROP_TX_RING_SIZE "tx_ring_size" 209 #define PROP_RX_QUEUE_NUM "rx_queue_number" 210 #define PROP_RX_RING_SIZE "rx_ring_size" 211 #define PROP_RX_GROUP_NUM "rx_group_number" 212 213 #define PROP_INTR_FORCE "intr_force" 214 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 215 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 216 #define PROP_LSO_ENABLE "lso_enable" 217 #define PROP_MR_ENABLE "mr_enable" 218 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 219 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 220 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 221 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 222 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 223 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 224 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 225 #define PROP_INTR_THROTTLING "intr_throttling" 226 #define PROP_FM_CAPABLE "fm_capable" 227 228 #define IXGBE_LB_NONE 0 229 #define IXGBE_LB_EXTERNAL 1 230 #define IXGBE_LB_INTERNAL_MAC 2 231 #define IXGBE_LB_INTERNAL_PHY 3 232 #define IXGBE_LB_INTERNAL_SERDES 4 233 234 /* 235 * capability/feature flags 236 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 237 * Separately, the flag named _ENABLED is set when the feature is enabled. 238 */ 239 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 240 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 241 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 242 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 243 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 244 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 245 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 246 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 247 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 248 249 /* adapter-specific info for each supported device type */ 250 typedef struct adapter_info { 251 uint32_t max_rx_que_num; /* maximum number of rx queues */ 252 uint32_t min_rx_que_num; /* minimum number of rx queues */ 253 uint32_t def_rx_que_num; /* default number of rx queues */ 254 uint32_t max_tx_que_num; /* maximum number of tx queues */ 255 uint32_t min_tx_que_num; /* minimum number of tx queues */ 256 uint32_t def_tx_que_num; /* default number of tx queues */ 257 uint32_t max_mtu; /* maximum MTU size */ 258 /* 259 * Interrupt throttling is in unit of 256 nsec 260 */ 261 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 262 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 263 uint32_t def_intr_throttle; /* default interrupt throttle */ 264 265 uint32_t max_msix_vect; /* maximum total msix vectors */ 266 uint32_t max_ring_vect; /* maximum number of ring vectors */ 267 uint32_t max_other_vect; /* maximum number of other vectors */ 268 uint32_t other_intr; /* "other" interrupt types handled */ 269 uint32_t flags; /* capability flags */ 270 } adapter_info_t; 271 272 /* bits representing all interrupt types other than tx & rx */ 273 #define IXGBE_OTHER_INTR 0x3ff00000 274 #define IXGBE_82599_OTHER_INTR 0x86100000 275 276 enum ioc_reply { 277 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 278 IOC_DONE, /* OK, reply sent */ 279 IOC_ACK, /* OK, just send ACK */ 280 IOC_REPLY /* OK, just send reply */ 281 }; 282 283 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 284 0, 0, (flag))) 285 286 /* 287 * Defined for ring index operations 288 * ASSERT(index < limit) 289 * ASSERT(step < limit) 290 * ASSERT(index1 < limit) 291 * ASSERT(index2 < limit) 292 */ 293 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 294 (index) + (step) : (index) + (step) - (limit)) 295 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 296 (index) - (step) : (index) + (limit) - (step)) 297 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 298 (index2) - (index1) : (index2) + (limit) - (index1)) 299 300 #define LINK_LIST_INIT(_LH) \ 301 (_LH)->head = (_LH)->tail = NULL 302 303 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 304 305 #define LIST_POP_HEAD(_LH) \ 306 (single_link_t *)(_LH)->head; \ 307 { \ 308 if ((_LH)->head != NULL) { \ 309 (_LH)->head = (_LH)->head->link; \ 310 if ((_LH)->head == NULL) \ 311 (_LH)->tail = NULL; \ 312 } \ 313 } 314 315 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 316 317 #define LIST_PUSH_TAIL(_LH, _E) \ 318 if ((_LH)->tail != NULL) { \ 319 (_LH)->tail->link = (single_link_t *)(_E); \ 320 (_LH)->tail = (single_link_t *)(_E); \ 321 } else { \ 322 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 323 } \ 324 (_E)->link = NULL; 325 326 #define LIST_GET_NEXT(_LH, _E) \ 327 (((_LH)->tail == (single_link_t *)(_E)) ? \ 328 NULL : ((single_link_t *)(_E))->link) 329 330 331 typedef struct single_link { 332 struct single_link *link; 333 } single_link_t; 334 335 typedef struct link_list { 336 single_link_t *head; 337 single_link_t *tail; 338 } link_list_t; 339 340 /* 341 * Property lookups 342 */ 343 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 344 DDI_PROP_DONTPASS, (n)) 345 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 346 DDI_PROP_DONTPASS, (n), -1) 347 348 349 typedef union ixgbe_ether_addr { 350 struct { 351 uint32_t high; 352 uint32_t low; 353 } reg; 354 struct { 355 uint8_t set; 356 uint8_t redundant; 357 uint8_t addr[ETHERADDRL]; 358 } mac; 359 } ixgbe_ether_addr_t; 360 361 typedef enum { 362 USE_NONE, 363 USE_COPY, 364 USE_DMA 365 } tx_type_t; 366 367 typedef struct ixgbe_tx_context { 368 uint32_t hcksum_flags; 369 uint32_t ip_hdr_len; 370 uint32_t mac_hdr_len; 371 uint32_t l4_proto; 372 uint32_t mss; 373 uint32_t l4_hdr_len; 374 boolean_t lso_flag; 375 } ixgbe_tx_context_t; 376 377 /* 378 * Hold address/length of each DMA segment 379 */ 380 typedef struct sw_desc { 381 uint64_t address; 382 size_t length; 383 } sw_desc_t; 384 385 /* 386 * Handles and addresses of DMA buffer 387 */ 388 typedef struct dma_buffer { 389 caddr_t address; /* Virtual address */ 390 uint64_t dma_address; /* DMA (Hardware) address */ 391 ddi_acc_handle_t acc_handle; /* Data access handle */ 392 ddi_dma_handle_t dma_handle; /* DMA handle */ 393 size_t size; /* Buffer size */ 394 size_t len; /* Data length in the buffer */ 395 } dma_buffer_t; 396 397 /* 398 * Tx Control Block 399 */ 400 typedef struct tx_control_block { 401 single_link_t link; 402 uint32_t last_index; /* last descriptor of the pkt */ 403 uint32_t frag_num; 404 uint32_t desc_num; 405 mblk_t *mp; 406 tx_type_t tx_type; 407 ddi_dma_handle_t tx_dma_handle; 408 dma_buffer_t tx_buf; 409 sw_desc_t desc[MAX_COOKIE]; 410 } tx_control_block_t; 411 412 /* 413 * RX Control Block 414 */ 415 typedef struct rx_control_block { 416 mblk_t *mp; 417 uint32_t ref_cnt; 418 dma_buffer_t rx_buf; 419 frtn_t free_rtn; 420 struct ixgbe_rx_data *rx_data; 421 } rx_control_block_t; 422 423 /* 424 * Software Data Structure for Tx Ring 425 */ 426 typedef struct ixgbe_tx_ring { 427 uint32_t index; /* Ring index */ 428 uint32_t intr_vector; /* Interrupt vector index */ 429 uint32_t vect_bit; /* vector's bit in register */ 430 431 /* 432 * Mutexes 433 */ 434 kmutex_t tx_lock; 435 kmutex_t recycle_lock; 436 kmutex_t tcb_head_lock; 437 kmutex_t tcb_tail_lock; 438 439 /* 440 * Tx descriptor ring definitions 441 */ 442 dma_buffer_t tbd_area; 443 union ixgbe_adv_tx_desc *tbd_ring; 444 uint32_t tbd_head; /* Index of next tbd to recycle */ 445 uint32_t tbd_tail; /* Index of next tbd to transmit */ 446 uint32_t tbd_free; /* Number of free tbd */ 447 448 /* 449 * Tx control block list definitions 450 */ 451 tx_control_block_t *tcb_area; 452 tx_control_block_t **work_list; 453 tx_control_block_t **free_list; 454 uint32_t tcb_head; /* Head index of free list */ 455 uint32_t tcb_tail; /* Tail index of free list */ 456 uint32_t tcb_free; /* Number of free tcb in free list */ 457 458 uint32_t *tbd_head_wb; /* Head write-back */ 459 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 460 461 /* 462 * s/w context structure for TCP/UDP checksum offload 463 * and LSO. 464 */ 465 ixgbe_tx_context_t tx_context; 466 467 /* 468 * Tx ring settings and status 469 */ 470 uint32_t ring_size; /* Tx descriptor ring size */ 471 uint32_t free_list_size; /* Tx free list size */ 472 473 boolean_t reschedule; 474 uint32_t recycle_fail; 475 uint32_t stall_watchdog; 476 477 #ifdef IXGBE_DEBUG 478 /* 479 * Debug statistics 480 */ 481 uint32_t stat_overload; 482 uint32_t stat_fail_no_tbd; 483 uint32_t stat_fail_no_tcb; 484 uint32_t stat_fail_dma_bind; 485 uint32_t stat_reschedule; 486 uint32_t stat_break_tbd_limit; 487 uint32_t stat_lso_header_fail; 488 #endif 489 490 mac_ring_handle_t ring_handle; 491 492 /* 493 * Pointer to the ixgbe struct 494 */ 495 struct ixgbe *ixgbe; 496 } ixgbe_tx_ring_t; 497 498 /* 499 * Software Receive Ring 500 */ 501 typedef struct ixgbe_rx_data { 502 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 503 504 /* 505 * Rx descriptor ring definitions 506 */ 507 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 508 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 509 uint32_t rbd_next; /* Index of next rx desc */ 510 511 /* 512 * Rx control block list definitions 513 */ 514 rx_control_block_t *rcb_area; 515 rx_control_block_t **work_list; /* Work list of rcbs */ 516 rx_control_block_t **free_list; /* Free list of rcbs */ 517 uint32_t rcb_head; /* Index of next free rcb */ 518 uint32_t rcb_tail; /* Index to put recycled rcb */ 519 uint32_t rcb_free; /* Number of free rcbs */ 520 521 /* 522 * Rx sw ring settings and status 523 */ 524 uint32_t ring_size; /* Rx descriptor ring size */ 525 uint32_t free_list_size; /* Rx free list size */ 526 527 uint32_t rcb_pending; 528 uint32_t flag; 529 530 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 531 } ixgbe_rx_data_t; 532 533 /* 534 * Software Data Structure for Rx Ring 535 */ 536 typedef struct ixgbe_rx_ring { 537 uint32_t index; /* Ring index */ 538 uint32_t intr_vector; /* Interrupt vector index */ 539 uint32_t vect_bit; /* vector's bit in register */ 540 541 ixgbe_rx_data_t *rx_data; /* Rx software ring */ 542 543 kmutex_t rx_lock; /* Rx access lock */ 544 545 #ifdef IXGBE_DEBUG 546 /* 547 * Debug statistics 548 */ 549 uint32_t stat_frame_error; 550 uint32_t stat_cksum_error; 551 uint32_t stat_exceed_pkt; 552 #endif 553 554 mac_ring_handle_t ring_handle; 555 uint64_t ring_gen_num; 556 557 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 558 } ixgbe_rx_ring_t; 559 /* 560 * Software Receive Ring Group 561 */ 562 typedef struct ixgbe_rx_group { 563 uint32_t index; /* Group index */ 564 mac_group_handle_t group_handle; /* call back group handle */ 565 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 566 } ixgbe_rx_group_t; 567 568 /* 569 * structure to map interrupt cleanup to msi-x vector 570 */ 571 typedef struct ixgbe_intr_vector { 572 struct ixgbe *ixgbe; /* point to my adapter */ 573 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 574 int rxr_cnt; /* count rx rings */ 575 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 576 int txr_cnt; /* count tx rings */ 577 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 578 int other_cnt; /* count other interrupt */ 579 } ixgbe_intr_vector_t; 580 581 /* 582 * Software adapter state 583 */ 584 typedef struct ixgbe { 585 int instance; 586 mac_handle_t mac_hdl; 587 dev_info_t *dip; 588 struct ixgbe_hw hw; 589 struct ixgbe_osdep osdep; 590 591 adapter_info_t *capab; /* adapter hardware capabilities */ 592 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */ 593 uint32_t eims; /* interrupt mask setting */ 594 uint32_t eimc; /* interrupt mask clear */ 595 uint32_t eicr; /* interrupt cause reg */ 596 597 uint32_t ixgbe_state; 598 link_state_t link_state; 599 uint32_t link_speed; 600 uint32_t link_duplex; 601 uint32_t link_down_timeout; 602 603 uint32_t reset_count; 604 uint32_t attach_progress; 605 uint32_t loopback_mode; 606 uint32_t default_mtu; 607 uint32_t max_frame_size; 608 609 uint32_t rcb_pending; 610 611 /* 612 * Each msi-x vector: map vector to interrupt cleanup 613 */ 614 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 615 616 /* 617 * Receive Rings 618 */ 619 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 620 uint32_t num_rx_rings; /* Number of rx rings in use */ 621 uint32_t rx_ring_size; /* Rx descriptor ring size */ 622 uint32_t rx_buf_size; /* Rx buffer size */ 623 624 /* 625 * Receive Groups 626 */ 627 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 628 uint32_t num_rx_groups; /* Number of rx groups in use */ 629 630 /* 631 * Transmit Rings 632 */ 633 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 634 uint32_t num_tx_rings; /* Number of tx rings in use */ 635 uint32_t tx_ring_size; /* Tx descriptor ring size */ 636 uint32_t tx_buf_size; /* Tx buffer size */ 637 638 boolean_t tx_ring_init; 639 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 640 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 641 boolean_t lso_enable; /* Large Segment Offload */ 642 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 643 uint32_t tx_copy_thresh; /* Tx copy threshold */ 644 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 645 uint32_t tx_overload_thresh; /* Tx overload threshold */ 646 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 647 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 648 uint32_t rx_copy_thresh; /* Rx copy threshold */ 649 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 650 uint32_t intr_throttling[MAX_INTR_VECTOR]; 651 uint32_t intr_force; 652 int fm_capabilities; /* FMA capabilities */ 653 654 int intr_type; 655 int intr_cnt; 656 int intr_cap; 657 size_t intr_size; 658 uint_t intr_pri; 659 ddi_intr_handle_t *htable; 660 uint32_t eims_mask; 661 662 kmutex_t gen_lock; /* General lock for device access */ 663 kmutex_t watchdog_lock; 664 kmutex_t rx_pending_lock; 665 666 boolean_t watchdog_enable; 667 boolean_t watchdog_start; 668 timeout_id_t watchdog_tid; 669 670 boolean_t unicst_init; 671 uint32_t unicst_avail; 672 uint32_t unicst_total; 673 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 674 uint32_t mcast_count; 675 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 676 677 ulong_t sys_page_size; 678 679 boolean_t link_check_complete; 680 hrtime_t link_check_hrtime; 681 ddi_periodic_t periodic_id; /* for link check timer func */ 682 683 /* 684 * Kstat definitions 685 */ 686 kstat_t *ixgbe_ks; 687 688 uint32_t param_en_10000fdx_cap:1, 689 param_en_1000fdx_cap:1, 690 param_en_100fdx_cap:1, 691 param_adv_10000fdx_cap:1, 692 param_adv_1000fdx_cap:1, 693 param_adv_100fdx_cap:1, 694 param_pause_cap:1, 695 param_asym_pause_cap:1, 696 param_rem_fault:1, 697 param_adv_autoneg_cap:1, 698 param_adv_pause_cap:1, 699 param_adv_asym_pause_cap:1, 700 param_adv_rem_fault:1, 701 param_lp_10000fdx_cap:1, 702 param_lp_1000fdx_cap:1, 703 param_lp_100fdx_cap:1, 704 param_lp_autoneg_cap:1, 705 param_lp_pause_cap:1, 706 param_lp_asym_pause_cap:1, 707 param_lp_rem_fault:1, 708 param_pad_to_32:12; 709 } ixgbe_t; 710 711 typedef struct ixgbe_stat { 712 kstat_named_t link_speed; /* Link Speed */ 713 714 kstat_named_t reset_count; /* Reset Count */ 715 716 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 717 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 718 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 719 720 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 721 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 722 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 723 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 724 kstat_named_t tx_reschedule; /* Tx Reschedule */ 725 726 kstat_named_t gprc; /* Good Packets Received Count */ 727 kstat_named_t gptc; /* Good Packets Xmitted Count */ 728 kstat_named_t gor; /* Good Octets Received Count */ 729 kstat_named_t got; /* Good Octets Xmitd Count */ 730 kstat_named_t prc64; /* Packets Received - 64b */ 731 kstat_named_t prc127; /* Packets Received - 65-127b */ 732 kstat_named_t prc255; /* Packets Received - 127-255b */ 733 kstat_named_t prc511; /* Packets Received - 256-511b */ 734 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 735 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 736 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 737 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 738 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 739 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 740 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 741 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 742 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 743 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 744 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 745 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 746 747 kstat_named_t crcerrs; /* CRC Error Count */ 748 kstat_named_t illerrc; /* Illegal Byte Error Count */ 749 kstat_named_t errbc; /* Error Byte Count */ 750 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 751 kstat_named_t mpc; /* Missed Packets Count */ 752 kstat_named_t mlfc; /* MAC Local Fault Count */ 753 kstat_named_t mrfc; /* MAC Remote Fault Count */ 754 kstat_named_t rlec; /* Receive Length Error Count */ 755 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 756 kstat_named_t lxonrxc; /* Link XON Received Count */ 757 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 758 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 759 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 760 kstat_named_t mprc; /* Multicast Pkts Received Count */ 761 kstat_named_t rnbc; /* Receive No Buffers Count */ 762 kstat_named_t ruc; /* Receive Undersize Count */ 763 kstat_named_t rfc; /* Receive Frag Count */ 764 kstat_named_t roc; /* Receive Oversize Count */ 765 kstat_named_t rjc; /* Receive Jabber Count */ 766 kstat_named_t tor; /* Total Octets Recvd Count */ 767 kstat_named_t tot; /* Total Octets Xmitted Count */ 768 kstat_named_t tpr; /* Total Packets Received */ 769 kstat_named_t tpt; /* Total Packets Xmitted */ 770 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 771 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 772 } ixgbe_stat_t; 773 774 /* 775 * Function prototypes in ixgbe_buf.c 776 */ 777 int ixgbe_alloc_dma(ixgbe_t *); 778 void ixgbe_free_dma(ixgbe_t *); 779 void ixgbe_set_fma_flags(int); 780 void ixgbe_free_dma_buffer(dma_buffer_t *); 781 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 782 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 783 784 /* 785 * Function prototypes in ixgbe_main.c 786 */ 787 int ixgbe_start(ixgbe_t *, boolean_t); 788 void ixgbe_stop(ixgbe_t *, boolean_t); 789 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 790 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 791 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 792 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 793 794 void ixgbe_enable_watchdog_timer(ixgbe_t *); 795 void ixgbe_disable_watchdog_timer(ixgbe_t *); 796 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 797 798 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 799 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 800 void ixgbe_fm_ereport(ixgbe_t *, char *); 801 802 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 803 mac_ring_info_t *, mac_ring_handle_t); 804 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 805 mac_group_info_t *, mac_group_handle_t); 806 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 807 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 808 809 /* 810 * Function prototypes in ixgbe_gld.c 811 */ 812 int ixgbe_m_start(void *); 813 void ixgbe_m_stop(void *); 814 int ixgbe_m_promisc(void *, boolean_t); 815 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 816 int ixgbe_m_stat(void *, uint_t, uint64_t *); 817 void ixgbe_m_resources(void *); 818 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 819 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 820 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 821 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, 822 uint_t, uint_t, void *, uint_t *); 823 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 824 int ixgbe_get_priv_prop(ixgbe_t *, const char *, 825 uint_t, uint_t, void *, uint_t *); 826 boolean_t ixgbe_param_locked(mac_prop_id_t); 827 828 /* 829 * Function prototypes in ixgbe_rx.c 830 */ 831 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 832 void ixgbe_rx_recycle(caddr_t arg); 833 mblk_t *ixgbe_ring_rx_poll(void *, int); 834 835 /* 836 * Function prototypes in ixgbe_tx.c 837 */ 838 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 839 void ixgbe_free_tcb(tx_control_block_t *); 840 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 841 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 842 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 843 844 /* 845 * Function prototypes in ixgbe_log.c 846 */ 847 void ixgbe_notice(void *, const char *, ...); 848 void ixgbe_log(void *, const char *, ...); 849 void ixgbe_error(void *, const char *, ...); 850 851 /* 852 * Function prototypes in ixgbe_stat.c 853 */ 854 int ixgbe_init_stats(ixgbe_t *); 855 856 #ifdef __cplusplus 857 } 858 #endif 859 860 #endif /* _IXGBE_SW_H */ 861