xref: /illumos-gate/usr/src/uts/common/io/ixgbe/ixgbe_sw.h (revision 633c5e5c7668b9d33284a5bcc15b3de163de5641)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24  */
25 
26 /*
27  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28  * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29  * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30  * Copyright 2019 Joyent, Inc.
31  * Copyright 2020 Oxide Computer Company
32  */
33 
34 #ifndef	_IXGBE_SW_H
35 #define	_IXGBE_SW_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 #include <sys/types.h>
42 #include <sys/conf.h>
43 #include <sys/debug.h>
44 #include <sys/stropts.h>
45 #include <sys/stream.h>
46 #include <sys/strsun.h>
47 #include <sys/strlog.h>
48 #include <sys/kmem.h>
49 #include <sys/stat.h>
50 #include <sys/kstat.h>
51 #include <sys/modctl.h>
52 #include <sys/errno.h>
53 #include <sys/dlpi.h>
54 #include <sys/mac_provider.h>
55 #include <sys/mac_ether.h>
56 #include <sys/vlan.h>
57 #include <sys/ddi.h>
58 #include <sys/sunddi.h>
59 #include <sys/pci.h>
60 #include <sys/pcie.h>
61 #include <sys/sdt.h>
62 #include <sys/ethernet.h>
63 #include <sys/pattr.h>
64 #include <sys/strsubr.h>
65 #include <sys/netlb.h>
66 #include <sys/random.h>
67 #include <inet/common.h>
68 #include <inet/tcp.h>
69 #include <inet/ip.h>
70 #include <inet/mi.h>
71 #include <inet/nd.h>
72 #include <sys/bitmap.h>
73 #include <sys/ddifm.h>
74 #include <sys/fm/protocol.h>
75 #include <sys/fm/util.h>
76 #include <sys/disp.h>
77 #include <sys/fm/io/ddi.h>
78 #include <sys/ddi_ufm.h>
79 #include "ixgbe_api.h"
80 
81 #define	MODULE_NAME			"ixgbe"	/* module name */
82 
83 #define	IXGBE_FAILURE			DDI_FAILURE
84 
85 #define	IXGBE_UNKNOWN			0x00
86 #define	IXGBE_INITIALIZED		0x01
87 #define	IXGBE_STARTED			0x02
88 #define	IXGBE_SUSPENDED			0x04
89 #define	IXGBE_STALL			0x08
90 #define	IXGBE_OVERTEMP			0x20
91 #define	IXGBE_INTR_ADJUST		0x40
92 #define	IXGBE_ERROR			0x80
93 
94 #define	MAX_NUM_UNICAST_ADDRESSES	0x80
95 #define	MAX_NUM_MULTICAST_ADDRESSES	0x1000
96 #define	MAX_NUM_VLAN_FILTERS		0x40
97 
98 #define	IXGBE_INTR_NONE			0
99 #define	IXGBE_INTR_MSIX			1
100 #define	IXGBE_INTR_MSI			2
101 #define	IXGBE_INTR_LEGACY		3
102 
103 #define	IXGBE_POLL_NULL			-1
104 
105 #define	MAX_COOKIE			18
106 #define	MIN_NUM_TX_DESC			2
107 
108 #define	IXGBE_TX_DESC_LIMIT		32	/* tx desc limitation	*/
109 
110 #define	IXGBE_ADAPTER_REGSET		1	/* map adapter registers */
111 
112 #define	IXGBE_RX_STOPPED		0x1
113 
114 #define	IXGBE_PKG_BUF_16k		16384
115 
116 /*
117  * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
118  * supported silicon types.
119  */
120 #define	MAX_TX_QUEUE_NUM		128
121 #define	MAX_RX_QUEUE_NUM		128
122 #define	MAX_INTR_VECTOR			64
123 
124 /*
125  * Maximum values for user configurable parameters
126  */
127 #define	MAX_TX_RING_SIZE		4096
128 #define	MAX_RX_RING_SIZE		4096
129 
130 #define	MAX_RX_LIMIT_PER_INTR		4096
131 
132 #define	MAX_RX_COPY_THRESHOLD		9216
133 #define	MAX_TX_COPY_THRESHOLD		9216
134 #define	MAX_TX_RECYCLE_THRESHOLD	DEFAULT_TX_RING_SIZE
135 #define	MAX_TX_OVERLOAD_THRESHOLD	DEFAULT_TX_RING_SIZE
136 #define	MAX_TX_RESCHED_THRESHOLD	DEFAULT_TX_RING_SIZE
137 
138 /*
139  * Minimum values for user configurable parameters
140  */
141 #define	MIN_TX_RING_SIZE		64
142 #define	MIN_RX_RING_SIZE		64
143 
144 #define	MIN_MTU				ETHERMIN
145 #define	MIN_RX_LIMIT_PER_INTR		16
146 #define	MIN_TX_COPY_THRESHOLD		0
147 #define	MIN_RX_COPY_THRESHOLD		0
148 #define	MIN_TX_RECYCLE_THRESHOLD	MIN_NUM_TX_DESC
149 #define	MIN_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
150 #define	MIN_TX_RESCHED_THRESHOLD	MIN_NUM_TX_DESC
151 
152 /*
153  * Default values for user configurable parameters
154  */
155 #define	DEFAULT_TX_RING_SIZE		1024
156 #define	DEFAULT_RX_RING_SIZE		1024
157 
158 #define	DEFAULT_MTU			ETHERMTU
159 #define	DEFAULT_RX_LIMIT_PER_INTR	256
160 #define	DEFAULT_RX_COPY_THRESHOLD	128
161 #define	DEFAULT_TX_COPY_THRESHOLD	512
162 #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
163 #define	DEFAULT_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
164 #define	DEFAULT_TX_RESCHED_THRESHOLD	128
165 #define	DEFAULT_FCRTH			0x20000
166 #define	DEFAULT_FCRTL			0x10000
167 #define	DEFAULT_FCPAUSE			0xFFFF
168 
169 #define	DEFAULT_TX_HCKSUM_ENABLE	B_TRUE
170 #define	DEFAULT_RX_HCKSUM_ENABLE	B_TRUE
171 #define	DEFAULT_LSO_ENABLE		B_TRUE
172 #define	DEFAULT_LRO_ENABLE		B_FALSE
173 #define	DEFAULT_MR_ENABLE		B_TRUE
174 #define	DEFAULT_TX_HEAD_WB_ENABLE	B_TRUE
175 #define	DEFAULT_RELAX_ORDER_ENABLE	B_TRUE
176 #define	DEFAULT_ALLOW_UNSUPPORTED_SFP	B_FALSE
177 
178 #define	IXGBE_LSO_MAXLEN		65535
179 
180 #define	TX_DRAIN_TIME			200
181 #define	RX_DRAIN_TIME			200
182 
183 #define	STALL_WATCHDOG_TIMEOUT		8	/* 8 seconds */
184 #define	MAX_LINK_DOWN_TIMEOUT		8	/* 8 seconds */
185 
186 #define	IXGBE_CYCLIC_PERIOD		(1000000000)	/* 1s */
187 
188 /*
189  * Extra register bit masks for 82598
190  */
191 #define	IXGBE_PCS1GANA_FDC	0x20
192 #define	IXGBE_PCS1GANLP_LPFD	0x20
193 #define	IXGBE_PCS1GANLP_LPHD	0x40
194 
195 /*
196  * Defined for IP header alignment.
197  */
198 #define	IPHDR_ALIGN_ROOM		2
199 
200 /*
201  * Bit flags for attach_progress
202  */
203 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
204 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
205 #define	ATTACH_PROGRESS_PROPS		0x0004	/* Properties initialized */
206 #define	ATTACH_PROGRESS_ALLOC_INTR	0x0008	/* Interrupts allocated */
207 #define	ATTACH_PROGRESS_ALLOC_RINGS	0x0010	/* Rings allocated */
208 #define	ATTACH_PROGRESS_ADD_INTR	0x0020	/* Intr handlers added */
209 #define	ATTACH_PROGRESS_LOCKS		0x0040	/* Locks initialized */
210 #define	ATTACH_PROGRESS_INIT		0x0080	/* Device initialized */
211 #define	ATTACH_PROGRESS_STATS		0x0200	/* Kstats created */
212 #define	ATTACH_PROGRESS_MAC		0x0800	/* MAC registered */
213 #define	ATTACH_PROGRESS_ENABLE_INTR	0x1000	/* DDI interrupts enabled */
214 #define	ATTACH_PROGRESS_FM_INIT		0x2000	/* FMA initialized */
215 #define	ATTACH_PROGRESS_SFP_TASKQ	0x4000	/* SFP taskq created */
216 #define	ATTACH_PROGRESS_LINK_TIMER	0x8000	/* link check timer */
217 #define	ATTACH_PROGRESS_OVERTEMP_TASKQ	0x10000 /* Over-temp taskq created */
218 #define	ATTACH_PROGRESS_PHY_TASKQ	0x20000 /* Ext. PHY taskq created */
219 #define	ATTACH_PROGRESS_UFM		0x40000	/* UFM support */
220 
221 #define	PROP_DEFAULT_MTU		"default_mtu"
222 #define	PROP_FLOW_CONTROL		"flow_control"
223 #define	PROP_TX_QUEUE_NUM		"tx_queue_number"
224 #define	PROP_TX_RING_SIZE		"tx_ring_size"
225 #define	PROP_RX_QUEUE_NUM		"rx_queue_number"
226 #define	PROP_RX_RING_SIZE		"rx_ring_size"
227 #define	PROP_RX_GROUP_NUM		"rx_group_number"
228 
229 #define	PROP_INTR_FORCE			"intr_force"
230 #define	PROP_TX_HCKSUM_ENABLE		"tx_hcksum_enable"
231 #define	PROP_RX_HCKSUM_ENABLE		"rx_hcksum_enable"
232 #define	PROP_LSO_ENABLE			"lso_enable"
233 #define	PROP_LRO_ENABLE			"lro_enable"
234 #define	PROP_MR_ENABLE			"mr_enable"
235 #define	PROP_RELAX_ORDER_ENABLE		"relax_order_enable"
236 #define	PROP_TX_HEAD_WB_ENABLE		"tx_head_wb_enable"
237 #define	PROP_TX_COPY_THRESHOLD		"tx_copy_threshold"
238 #define	PROP_TX_RECYCLE_THRESHOLD	"tx_recycle_threshold"
239 #define	PROP_TX_OVERLOAD_THRESHOLD	"tx_overload_threshold"
240 #define	PROP_TX_RESCHED_THRESHOLD	"tx_resched_threshold"
241 #define	PROP_RX_COPY_THRESHOLD		"rx_copy_threshold"
242 #define	PROP_RX_LIMIT_PER_INTR		"rx_limit_per_intr"
243 #define	PROP_INTR_THROTTLING		"intr_throttling"
244 #define	PROP_FM_CAPABLE			"fm_capable"
245 #define	PROP_ALLOW_UNSUPPORTED_SFP	"allow_unsupported_sfp"
246 
247 #define	IXGBE_LB_NONE			0
248 #define	IXGBE_LB_EXTERNAL		1
249 #define	IXGBE_LB_INTERNAL_MAC		2
250 #define	IXGBE_LB_INTERNAL_PHY		3
251 #define	IXGBE_LB_INTERNAL_SERDES	4
252 
253 /*
254  * capability/feature flags
255  * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
256  * Separately, the flag named _ENABLED is set when the feature is enabled.
257  */
258 #define	IXGBE_FLAG_DCA_ENABLED		(u32)(1)
259 #define	IXGBE_FLAG_DCA_CAPABLE		(u32)(1 << 1)
260 #define	IXGBE_FLAG_DCB_ENABLED		(u32)(1 << 2)
261 #define	IXGBE_FLAG_DCB_CAPABLE		(u32)(1 << 4)
262 #define	IXGBE_FLAG_RSS_ENABLED		(u32)(1 << 4)
263 #define	IXGBE_FLAG_RSS_CAPABLE		(u32)(1 << 5)
264 #define	IXGBE_FLAG_VMDQ_CAPABLE		(u32)(1 << 6)
265 #define	IXGBE_FLAG_VMDQ_ENABLED		(u32)(1 << 7)
266 #define	IXGBE_FLAG_FAN_FAIL_CAPABLE	(u32)(1 << 8)
267 #define	IXGBE_FLAG_RSC_CAPABLE		(u32)(1 << 9)
268 #define	IXGBE_FLAG_SFP_PLUG_CAPABLE	(u32)(1 << 10)
269 #define	IXGBE_FLAG_TEMP_SENSOR_CAPABLE	(u32)(1 << 11)
270 
271 /*
272  * Classification mode
273  */
274 #define	IXGBE_CLASSIFY_NONE		0
275 #define	IXGBE_CLASSIFY_RSS		1
276 #define	IXGBE_CLASSIFY_VMDQ		2
277 #define	IXGBE_CLASSIFY_VMDQ_RSS		3
278 
279 /* adapter-specific info for each supported device type */
280 typedef struct adapter_info {
281 	uint32_t	max_rx_que_num; /* maximum number of rx queues */
282 	uint32_t	min_rx_que_num; /* minimum number of rx queues */
283 	uint32_t	def_rx_que_num; /* default number of rx queues */
284 	uint32_t	max_rx_grp_num; /* maximum number of rx groups */
285 	uint32_t	min_rx_grp_num; /* minimum number of rx groups */
286 	uint32_t	def_rx_grp_num; /* default number of rx groups */
287 	uint32_t	max_tx_que_num;	/* maximum number of tx queues */
288 	uint32_t	min_tx_que_num;	/* minimum number of tx queues */
289 	uint32_t	def_tx_que_num;	/* default number of tx queues */
290 	uint32_t	max_mtu;	/* maximum MTU size */
291 	/*
292 	 * Interrupt throttling is in unit of 256 nsec
293 	 */
294 	uint32_t	max_intr_throttle; /* maximum interrupt throttle */
295 	uint32_t	min_intr_throttle; /* minimum interrupt throttle */
296 	uint32_t	def_intr_throttle; /* default interrupt throttle */
297 
298 	uint32_t	max_msix_vect;	/* maximum total msix vectors */
299 	uint32_t	max_ring_vect;	/* maximum number of ring vectors */
300 	uint32_t	max_other_vect;	/* maximum number of other vectors */
301 	uint32_t	other_intr;	/* "other" interrupt types handled */
302 	uint32_t	other_gpie;	/* "other" interrupt types enabling */
303 	uint32_t	flags;		/* capability flags */
304 } adapter_info_t;
305 
306 /* bits representing all interrupt types other than tx & rx */
307 #define	IXGBE_OTHER_INTR	0x3ff00000
308 #define	IXGBE_82599_OTHER_INTR	0x86100000
309 
310 enum ioc_reply {
311 	IOC_INVAL = -1,	/* bad, NAK with EINVAL */
312 	IOC_DONE,	/* OK, reply sent */
313 	IOC_ACK,	/* OK, just send ACK */
314 	IOC_REPLY	/* OK, just send reply */
315 };
316 
317 #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area)->dma_handle, \
318 				    0, 0, (flag)))
319 
320 /*
321  * Defined for ring index operations
322  * ASSERT(index < limit)
323  * ASSERT(step < limit)
324  * ASSERT(index1 < limit)
325  * ASSERT(index2 < limit)
326  */
327 #define	NEXT_INDEX(index, step, limit)	(((index) + (step)) < (limit) ? \
328 	(index) + (step) : (index) + (step) - (limit))
329 #define	PREV_INDEX(index, step, limit)	((index) >= (step) ? \
330 	(index) - (step) : (index) + (limit) - (step))
331 #define	OFFSET(index1, index2, limit)	((index1) <= (index2) ? \
332 	(index2) - (index1) : (index2) + (limit) - (index1))
333 
334 #define	LINK_LIST_INIT(_LH)	\
335 	(_LH)->head = (_LH)->tail = NULL
336 
337 #define	LIST_GET_HEAD(_LH)	((single_link_t *)((_LH)->head))
338 
339 #define	LIST_POP_HEAD(_LH)	\
340 	(single_link_t *)(_LH)->head; \
341 	{ \
342 		if ((_LH)->head != NULL) { \
343 			(_LH)->head = (_LH)->head->link; \
344 			if ((_LH)->head == NULL) \
345 				(_LH)->tail = NULL; \
346 		} \
347 	}
348 
349 #define	LIST_GET_TAIL(_LH)	((single_link_t *)((_LH)->tail))
350 
351 #define	LIST_PUSH_TAIL(_LH, _E)	\
352 	if ((_LH)->tail != NULL) { \
353 		(_LH)->tail->link = (single_link_t *)(_E); \
354 		(_LH)->tail = (single_link_t *)(_E); \
355 	} else { \
356 		(_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
357 	} \
358 	(_E)->link = NULL;
359 
360 #define	LIST_GET_NEXT(_LH, _E)		\
361 	(((_LH)->tail == (single_link_t *)(_E)) ? \
362 	NULL : ((single_link_t *)(_E))->link)
363 
364 
365 typedef struct single_link {
366 	struct single_link	*link;
367 } single_link_t;
368 
369 typedef struct link_list {
370 	single_link_t		*head;
371 	single_link_t		*tail;
372 } link_list_t;
373 
374 /*
375  * Property lookups
376  */
377 #define	IXGBE_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
378 				    DDI_PROP_DONTPASS, (n))
379 #define	IXGBE_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
380 				    DDI_PROP_DONTPASS, (n), -1)
381 
382 
383 typedef union ixgbe_ether_addr {
384 	struct {
385 		uint32_t	high;
386 		uint32_t	low;
387 	} reg;
388 	struct {
389 		uint8_t		set;
390 		uint8_t		group_index;
391 		uint8_t		addr[ETHERADDRL];
392 	} mac;
393 } ixgbe_ether_addr_t;
394 
395 /*
396  * The list of VLANs an Rx group will accept.
397  */
398 typedef struct ixgbe_vlan {
399 	list_node_t		ixvl_link;
400 	uint16_t		ixvl_vid;   /* The VLAN ID */
401 	uint_t			ixvl_refs;  /* Number of users of this VLAN */
402 } ixgbe_vlan_t;
403 
404 typedef enum {
405 	USE_NONE,
406 	USE_COPY,
407 	USE_DMA
408 } tx_type_t;
409 
410 typedef struct ixgbe_tx_context {
411 	uint32_t		hcksum_flags;
412 	uint32_t		ip_hdr_len;
413 	uint32_t		mac_hdr_len;
414 	uint32_t		l3_proto;
415 	uint32_t		l4_proto;
416 	uint32_t		mss;
417 	uint32_t		l4_hdr_len;
418 	boolean_t		lso_flag;
419 } ixgbe_tx_context_t;
420 
421 /*
422  * Hold address/length of each DMA segment
423  */
424 typedef struct sw_desc {
425 	uint64_t		address;
426 	size_t			length;
427 } sw_desc_t;
428 
429 /*
430  * Handles and addresses of DMA buffer
431  */
432 typedef struct dma_buffer {
433 	caddr_t			address;	/* Virtual address */
434 	uint64_t		dma_address;	/* DMA (Hardware) address */
435 	ddi_acc_handle_t	acc_handle;	/* Data access handle */
436 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
437 	size_t			size;		/* Buffer size */
438 	size_t			len;		/* Data length in the buffer */
439 } dma_buffer_t;
440 
441 /*
442  * Tx Control Block
443  */
444 typedef struct tx_control_block {
445 	single_link_t		link;
446 	uint32_t		last_index; /* last descriptor of the pkt */
447 	uint32_t		frag_num;
448 	uint32_t		desc_num;
449 	mblk_t			*mp;
450 	tx_type_t		tx_type;
451 	ddi_dma_handle_t	tx_dma_handle;
452 	dma_buffer_t		tx_buf;
453 	sw_desc_t		desc[MAX_COOKIE];
454 } tx_control_block_t;
455 
456 /*
457  * RX Control Block
458  */
459 typedef struct rx_control_block {
460 	mblk_t			*mp;
461 	uint32_t		ref_cnt;
462 	dma_buffer_t		rx_buf;
463 	frtn_t			free_rtn;
464 	struct ixgbe_rx_data	*rx_data;
465 	int			lro_next;	/* Index of next rcb */
466 	int			lro_prev;	/* Index of previous rcb */
467 	boolean_t		lro_pkt;	/* Flag for LRO rcb */
468 } rx_control_block_t;
469 
470 /*
471  * Software Data Structure for Tx Ring
472  */
473 typedef struct ixgbe_tx_ring {
474 	uint32_t		index;	/* Ring index */
475 	uint32_t		intr_vector;	/* Interrupt vector index */
476 	uint32_t		vect_bit;	/* vector's bit in register */
477 
478 	/*
479 	 * Mutexes
480 	 */
481 	kmutex_t		tx_lock;
482 	kmutex_t		recycle_lock;
483 	kmutex_t		tcb_head_lock;
484 	kmutex_t		tcb_tail_lock;
485 
486 	/*
487 	 * Tx descriptor ring definitions
488 	 */
489 	dma_buffer_t		tbd_area;
490 	union ixgbe_adv_tx_desc	*tbd_ring;
491 	uint32_t		tbd_head; /* Index of next tbd to recycle */
492 	uint32_t		tbd_tail; /* Index of next tbd to transmit */
493 	uint32_t		tbd_free; /* Number of free tbd */
494 
495 	/*
496 	 * Tx control block list definitions
497 	 */
498 	tx_control_block_t	*tcb_area;
499 	tx_control_block_t	**work_list;
500 	tx_control_block_t	**free_list;
501 	uint32_t		tcb_head; /* Head index of free list */
502 	uint32_t		tcb_tail; /* Tail index of free list */
503 	uint32_t		tcb_free; /* Number of free tcb in free list */
504 
505 	uint32_t		*tbd_head_wb; /* Head write-back */
506 	uint32_t		(*tx_recycle)(struct ixgbe_tx_ring *);
507 
508 	/*
509 	 * s/w context structure for TCP/UDP checksum offload
510 	 * and LSO.
511 	 */
512 	ixgbe_tx_context_t	tx_context;
513 
514 	/*
515 	 * Tx ring settings and status
516 	 */
517 	uint32_t		ring_size; /* Tx descriptor ring size */
518 	uint32_t		free_list_size;	/* Tx free list size */
519 
520 	boolean_t		reschedule;
521 	uint32_t		recycle_fail;
522 	uint32_t		stall_watchdog;
523 
524 	uint32_t		stat_overload;
525 	uint32_t		stat_fail_no_tbd;
526 	uint32_t		stat_fail_no_tcb;
527 	uint32_t		stat_fail_dma_bind;
528 	uint32_t		stat_reschedule;
529 	uint32_t		stat_break_tbd_limit;
530 	uint32_t		stat_lso_header_fail;
531 
532 	uint64_t		stat_obytes;
533 	uint64_t		stat_opackets;
534 
535 	mac_ring_handle_t	ring_handle;
536 
537 	/*
538 	 * Pointer to the ixgbe struct
539 	 */
540 	struct ixgbe		*ixgbe;
541 } ixgbe_tx_ring_t;
542 
543 /*
544  * Software Receive Ring
545  */
546 typedef struct ixgbe_rx_data {
547 	kmutex_t		recycle_lock;	/* Recycle lock, for rcb_tail */
548 
549 	/*
550 	 * Rx descriptor ring definitions
551 	 */
552 	dma_buffer_t		rbd_area;	/* DMA buffer of rx desc ring */
553 	union ixgbe_adv_rx_desc	*rbd_ring;	/* Rx desc ring */
554 	uint32_t		rbd_next;	/* Index of next rx desc */
555 
556 	/*
557 	 * Rx control block list definitions
558 	 */
559 	rx_control_block_t	*rcb_area;
560 	rx_control_block_t	**work_list;	/* Work list of rcbs */
561 	rx_control_block_t	**free_list;	/* Free list of rcbs */
562 	uint32_t		rcb_head;	/* Index of next free rcb */
563 	uint32_t		rcb_tail;	/* Index to put recycled rcb */
564 	uint32_t		rcb_free;	/* Number of free rcbs */
565 
566 	/*
567 	 * Rx sw ring settings and status
568 	 */
569 	uint32_t		ring_size;	/* Rx descriptor ring size */
570 	uint32_t		free_list_size;	/* Rx free list size */
571 
572 	uint32_t		rcb_pending;
573 	uint32_t		flag;
574 
575 	uint32_t		lro_num;	/* Number of rcbs of one LRO */
576 	uint32_t		lro_first;	/* Index of first LRO rcb */
577 
578 	struct ixgbe_rx_ring	*rx_ring;	/* Pointer to rx ring */
579 } ixgbe_rx_data_t;
580 
581 /*
582  * Software Data Structure for Rx Ring
583  */
584 typedef struct ixgbe_rx_ring {
585 	uint32_t		index;		/* Ring index */
586 	uint32_t		group_index;	/* Group index */
587 	uint32_t		hw_index;	/* h/w ring index */
588 	uint32_t		intr_vector;	/* Interrupt vector index */
589 	uint32_t		vect_bit;	/* vector's bit in register */
590 
591 	ixgbe_rx_data_t		*rx_data;	/* Rx software ring */
592 
593 	kmutex_t		rx_lock;	/* Rx access lock */
594 
595 	uint32_t		stat_frame_error;
596 	uint32_t		stat_cksum_error;
597 	uint32_t		stat_exceed_pkt;
598 
599 	uint64_t		stat_rbytes;
600 	uint64_t		stat_ipackets;
601 
602 	mac_ring_handle_t	ring_handle;
603 	uint64_t		ring_gen_num;
604 
605 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
606 } ixgbe_rx_ring_t;
607 
608 /*
609  * Software Receive Ring Group
610  */
611 typedef struct ixgbe_rx_group {
612 	uint32_t		index;		/* Group index */
613 	mac_group_handle_t	group_handle;   /* call back group handle */
614 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
615 	boolean_t		aupe;		/* AUPE bit */
616 	list_t			vlans;		/* list of VLANs to allow */
617 } ixgbe_rx_group_t;
618 
619 /*
620  * structure to map interrupt cleanup to msi-x vector
621  */
622 typedef struct ixgbe_intr_vector {
623 	struct ixgbe *ixgbe;	/* point to my adapter */
624 	ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)];	/* bitmap of rx rings */
625 	int	rxr_cnt;	/* count rx rings */
626 	ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)];	/* bitmap of tx rings */
627 	int	txr_cnt;	/* count tx rings */
628 	ulong_t other_map[BT_BITOUL(2)];		/* bitmap of other */
629 	int	other_cnt;	/* count other interrupt */
630 } ixgbe_intr_vector_t;
631 
632 /*
633  * Software adapter state
634  */
635 typedef struct ixgbe {
636 	int			instance;
637 	mac_handle_t		mac_hdl;
638 	dev_info_t		*dip;
639 	struct ixgbe_hw		hw;
640 	struct ixgbe_osdep	osdep;
641 
642 	adapter_info_t		*capab;	/* adapter hardware capabilities */
643 	ddi_taskq_t		*sfp_taskq;	/* sfp-change taskq */
644 	ddi_taskq_t		*overtemp_taskq; /* overtemp taskq */
645 	ddi_taskq_t		*phy_taskq;	/* external PHY taskq */
646 	uint32_t		eims;		/* interrupt mask setting */
647 	uint32_t		eimc;		/* interrupt mask clear */
648 	uint32_t		eicr;		/* interrupt cause reg */
649 
650 	uint32_t		ixgbe_state;
651 	link_state_t		link_state;
652 	uint32_t		link_speed;
653 	uint32_t		link_duplex;
654 
655 	uint32_t		reset_count;
656 	uint32_t		attach_progress;
657 	uint32_t		loopback_mode;
658 	uint32_t		default_mtu;
659 	uint32_t		max_frame_size;
660 	ixgbe_link_speed	speeds_supported;
661 	uint64_t		phys_supported;
662 
663 	uint32_t		rcb_pending;
664 
665 	/*
666 	 * Each msi-x vector: map vector to interrupt cleanup
667 	 */
668 	ixgbe_intr_vector_t	vect_map[MAX_INTR_VECTOR];
669 
670 	/*
671 	 * Receive Rings
672 	 */
673 	ixgbe_rx_ring_t		*rx_rings;	/* Array of rx rings */
674 	uint32_t		num_rx_rings;	/* Number of rx rings in use */
675 	uint32_t		rx_ring_size;	/* Rx descriptor ring size */
676 	uint32_t		rx_buf_size;	/* Rx buffer size */
677 	boolean_t		lro_enable;	/* Large Receive Offload */
678 	uint64_t		lro_pkt_count;	/* LRO packet count */
679 	/*
680 	 * Receive Groups
681 	 */
682 	ixgbe_rx_group_t	*rx_groups;	/* Array of rx groups */
683 	uint32_t		num_rx_groups;	/* Number of rx groups in use */
684 	uint32_t		rx_def_group;	/* Default Rx group index */
685 
686 	/*
687 	 * Transmit Rings
688 	 */
689 	ixgbe_tx_ring_t		*tx_rings;	/* Array of tx rings */
690 	uint32_t		num_tx_rings;	/* Number of tx rings in use */
691 	uint32_t		tx_ring_size;	/* Tx descriptor ring size */
692 	uint32_t		tx_buf_size;	/* Tx buffer size */
693 
694 	boolean_t		tx_ring_init;
695 	boolean_t		tx_head_wb_enable; /* Tx head wrtie-back */
696 	boolean_t		tx_hcksum_enable; /* Tx h/w cksum offload */
697 	boolean_t		lso_enable;	/* Large Segment Offload */
698 	boolean_t		mr_enable;	/* Multiple Tx and Rx Ring */
699 	boolean_t		relax_order_enable; /* Relax Order */
700 	uint32_t		classify_mode;	/* Classification mode */
701 	uint32_t		tx_copy_thresh;	/* Tx copy threshold */
702 	uint32_t		tx_recycle_thresh; /* Tx recycle threshold */
703 	uint32_t		tx_overload_thresh; /* Tx overload threshold */
704 	uint32_t		tx_resched_thresh; /* Tx reschedule threshold */
705 	boolean_t		rx_hcksum_enable; /* Rx h/w cksum offload */
706 	uint32_t		rx_copy_thresh; /* Rx copy threshold */
707 	uint32_t		rx_limit_per_intr; /* Rx pkts per interrupt */
708 	uint32_t		intr_throttling[MAX_INTR_VECTOR];
709 	uint32_t		intr_force;
710 	int			fm_capabilities; /* FMA capabilities */
711 
712 	int			intr_type;
713 	int			intr_cnt;
714 	uint32_t		intr_cnt_max;
715 	uint32_t		intr_cnt_min;
716 	int			intr_cap;
717 	size_t			intr_size;
718 	uint_t			intr_pri;
719 	ddi_intr_handle_t	*htable;
720 	uint32_t		eims_mask;
721 	ddi_cb_handle_t		cb_hdl;		/* Interrupt callback handle */
722 
723 	kmutex_t		gen_lock; /* General lock for device access */
724 	kmutex_t		watchdog_lock;
725 	kmutex_t		rx_pending_lock;
726 
727 	boolean_t		watchdog_enable;
728 	boolean_t		watchdog_start;
729 	timeout_id_t		watchdog_tid;
730 
731 	boolean_t		unicst_init;
732 	uint32_t		unicst_avail;
733 	uint32_t		unicst_total;
734 	ixgbe_ether_addr_t	unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
735 	uint32_t		mcast_count;
736 	struct ether_addr	mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
737 
738 	boolean_t		vlft_enabled; /* VLAN filtering enabled? */
739 	boolean_t		vlft_init;    /* VLAN filtering initialized? */
740 
741 	ulong_t			sys_page_size;
742 
743 	boolean_t		link_check_complete;
744 	hrtime_t		link_check_hrtime;
745 	ddi_periodic_t		periodic_id; /* for link check timer func */
746 
747 	/*
748 	 * LED related constants.
749 	 */
750 	boolean_t		ixgbe_led_active;
751 	boolean_t		ixgbe_led_blink;
752 	uint32_t		ixgbe_led_reg;
753 	uint32_t		ixgbe_led_index;
754 
755 	/*
756 	 * UFM state
757 	 */
758 	ddi_ufm_handle_t	*ixgbe_ufmh;
759 
760 	/*
761 	 * Kstat definitions
762 	 */
763 	kstat_t			*ixgbe_ks;
764 
765 	uint32_t		param_en_10000fdx_cap:1,
766 				param_en_5000fdx_cap:1,
767 				param_en_2500fdx_cap:1,
768 				param_en_1000fdx_cap:1,
769 				param_en_100fdx_cap:1,
770 				param_adv_10000fdx_cap:1,
771 				param_adv_5000fdx_cap:1,
772 				param_adv_2500fdx_cap:1,
773 				param_adv_1000fdx_cap:1,
774 				param_adv_100fdx_cap:1,
775 				param_pause_cap:1,
776 				param_asym_pause_cap:1,
777 				param_rem_fault:1,
778 				param_adv_autoneg_cap:1,
779 				param_adv_pause_cap:1,
780 				param_adv_asym_pause_cap:1,
781 				param_adv_rem_fault:1,
782 				param_lp_10000fdx_cap:1,
783 				param_lp_5000fdx_cap:1,
784 				param_lp_2500fdx_cap:1,
785 				param_lp_1000fdx_cap:1,
786 				param_lp_100fdx_cap:1,
787 				param_lp_autoneg_cap:1,
788 				param_lp_pause_cap:1,
789 				param_lp_asym_pause_cap:1,
790 				param_lp_rem_fault:1,
791 				param_pad_to_32:6;
792 } ixgbe_t;
793 
794 typedef struct ixgbe_stat {
795 	kstat_named_t link_speed;	/* Link Speed */
796 
797 	kstat_named_t reset_count;	/* Reset Count */
798 
799 	kstat_named_t rx_frame_error;	/* Rx Error in Packet */
800 	kstat_named_t rx_cksum_error;	/* Rx Checksum Error */
801 	kstat_named_t rx_exceed_pkt;	/* Rx Exceed Max Pkt Count */
802 
803 	kstat_named_t tx_overload;	/* Tx Desc Ring Overload */
804 	kstat_named_t tx_fail_no_tcb;	/* Tx Fail Freelist Empty */
805 	kstat_named_t tx_fail_no_tbd;	/* Tx Fail Desc Ring Empty */
806 	kstat_named_t tx_fail_dma_bind;	/* Tx Fail DMA bind */
807 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
808 	kstat_named_t tx_break_tbd_limit; /* Reached single xmit desc limit */
809 	kstat_named_t tx_lso_header_fail; /* New mblk for last LSO hdr frag */
810 
811 	kstat_named_t gprc;	/* Good Packets Received Count */
812 	kstat_named_t gptc;	/* Good Packets Xmitted Count */
813 	kstat_named_t gor;	/* Good Octets Received Count */
814 	kstat_named_t got;	/* Good Octets Xmitd Count */
815 	kstat_named_t qor;	/* Queue Octets Received */
816 	kstat_named_t qot;	/* Queue Octets Transmitted */
817 	kstat_named_t qpr;	/* Queue Packets Received */
818 	kstat_named_t qpt;	/* Queue Packets Transmitted */
819 	kstat_named_t prc64;	/* Packets Received - 64b */
820 	kstat_named_t prc127;	/* Packets Received - 65-127b */
821 	kstat_named_t prc255;	/* Packets Received - 127-255b */
822 	kstat_named_t prc511;	/* Packets Received - 256-511b */
823 	kstat_named_t prc1023;	/* Packets Received - 511-1023b */
824 	kstat_named_t prc1522;	/* Packets Received - 1024-1522b */
825 	kstat_named_t ptc64;	/* Packets Xmitted (64b) */
826 	kstat_named_t ptc127;	/* Packets Xmitted (64-127b) */
827 	kstat_named_t ptc255;	/* Packets Xmitted (128-255b) */
828 	kstat_named_t ptc511;	/* Packets Xmitted (255-511b) */
829 	kstat_named_t ptc1023;	/* Packets Xmitted (512-1023b) */
830 	kstat_named_t ptc1522;	/* Packets Xmitted (1024-1522b */
831 
832 	kstat_named_t crcerrs;	/* CRC Error Count */
833 	kstat_named_t illerrc;	/* Illegal Byte Error Count */
834 	kstat_named_t errbc;	/* Error Byte Count */
835 	kstat_named_t mspdc;	/* MAC Short Packet Discard Count */
836 	kstat_named_t mpc;	/* Missed Packets Count */
837 	kstat_named_t mlfc;	/* MAC Local Fault Count */
838 	kstat_named_t mrfc;	/* MAC Remote Fault Count */
839 	kstat_named_t rlec;	/* Receive Length Error Count */
840 	kstat_named_t lxontxc;	/* Link XON Transmitted Count */
841 	kstat_named_t lxonrxc;	/* Link XON Received Count */
842 	kstat_named_t lxofftxc;	/* Link XOFF Transmitted Count */
843 	kstat_named_t lxoffrxc;	/* Link XOFF Received Count */
844 	kstat_named_t bprc;	/* Broadcasts Pkts Received Count */
845 	kstat_named_t mprc;	/* Multicast Pkts Received Count */
846 	kstat_named_t rnbc;	/* Receive No Buffers Count */
847 	kstat_named_t ruc;	/* Receive Undersize Count */
848 	kstat_named_t rfc;	/* Receive Frag Count */
849 	kstat_named_t roc;	/* Receive Oversize Count */
850 	kstat_named_t rjc;	/* Receive Jabber Count */
851 	kstat_named_t tor;	/* Total Octets Recvd Count */
852 	kstat_named_t tot;	/* Total Octets Xmitted Count */
853 	kstat_named_t tpr;	/* Total Packets Received */
854 	kstat_named_t tpt;	/* Total Packets Xmitted */
855 	kstat_named_t mptc;	/* Multicast Packets Xmited Count */
856 	kstat_named_t bptc;	/* Broadcast Packets Xmited Count */
857 	kstat_named_t lroc;	/* LRO Packets Received Count */
858 	kstat_named_t dev_gone;	/* Number of device gone events encountered */
859 } ixgbe_stat_t;
860 
861 /*
862  * Function prototypes in ixgbe_buf.c
863  */
864 int ixgbe_alloc_dma(ixgbe_t *);
865 void ixgbe_free_dma(ixgbe_t *);
866 void ixgbe_set_fma_flags(int);
867 void ixgbe_free_dma_buffer(dma_buffer_t *);
868 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
869 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
870 
871 /*
872  * Function prototypes in ixgbe_main.c
873  */
874 int ixgbe_start(ixgbe_t *, boolean_t);
875 void ixgbe_stop(ixgbe_t *, boolean_t);
876 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
877 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
878 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
879 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
880 
881 void ixgbe_enable_watchdog_timer(ixgbe_t *);
882 void ixgbe_disable_watchdog_timer(ixgbe_t *);
883 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
884 
885 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
886 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
887 void ixgbe_fm_ereport(ixgbe_t *, char *);
888 
889 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
890     mac_ring_info_t *, mac_ring_handle_t);
891 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
892     mac_group_info_t *, mac_group_handle_t);
893 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
894 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
895 
896 int ixgbe_transceiver_info(void *, uint_t, mac_transceiver_info_t *);
897 int ixgbe_transceiver_read(void *, uint_t, uint_t, void *, size_t, off_t,
898     size_t *);
899 mac_ether_media_t ixgbe_phy_to_media(ixgbe_t *);
900 
901 /*
902  * Function prototypes in ixgbe_gld.c
903  */
904 int ixgbe_m_start(void *);
905 void ixgbe_m_stop(void *);
906 int ixgbe_m_promisc(void *, boolean_t);
907 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
908 void ixgbe_m_resources(void *);
909 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
910 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
911 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
912 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
913 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
914     mac_prop_info_handle_t);
915 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
916 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
917 boolean_t ixgbe_param_locked(mac_prop_id_t);
918 
919 /*
920  * Function prototypes in ixgbe_rx.c
921  */
922 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
923 void ixgbe_rx_recycle(caddr_t arg);
924 mblk_t *ixgbe_ring_rx_poll(void *, int);
925 
926 /*
927  * Function prototypes in ixgbe_tx.c
928  */
929 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
930 void ixgbe_free_tcb(tx_control_block_t *);
931 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
932 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
933 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
934 
935 /*
936  * Function prototypes in ixgbe_log.c
937  */
938 void ixgbe_notice(void *, const char *, ...);
939 void ixgbe_log(void *, const char *, ...);
940 void ixgbe_error(void *, const char *, ...);
941 
942 /*
943  * Function prototypes in ixgbe_stat.c
944  */
945 int ixgbe_init_stats(ixgbe_t *);
946 int ixgbe_m_stat(void *, uint_t, uint64_t *);
947 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
948 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
949 
950 #ifdef __cplusplus
951 }
952 #endif
953 
954 #endif /* _IXGBE_SW_H */
955