1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 #ifndef _IXGBE_SW_H 32 #define _IXGBE_SW_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac_provider.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/tcp.h> 66 #include <inet/ip.h> 67 #include <inet/mi.h> 68 #include <inet/nd.h> 69 #include <sys/bitmap.h> 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 #include "ixgbe_api.h" 75 76 #define MODULE_NAME "ixgbe" /* module name */ 77 78 #define IXGBE_FAILURE DDI_FAILURE 79 80 #define IXGBE_UNKNOWN 0x00 81 #define IXGBE_INITIALIZED 0x01 82 #define IXGBE_STARTED 0x02 83 #define IXGBE_SUSPENDED 0x04 84 85 #define MAX_NUM_UNICAST_ADDRESSES 0x10 86 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 87 #define IXGBE_INTR_NONE 0 88 #define IXGBE_INTR_MSIX 1 89 #define IXGBE_INTR_MSI 2 90 #define IXGBE_INTR_LEGACY 3 91 92 #define IXGBE_POLL_NULL -1 93 94 #define MAX_COOKIE 18 95 #define MIN_NUM_TX_DESC 2 96 97 /* 98 * Maximum values for user configurable parameters 99 */ 100 101 /* 102 * MAX_xx_QUEUE_NUM values need to be the maximum of all supported 103 * silicon types. 104 */ 105 #define MAX_TX_QUEUE_NUM 32 106 #define MAX_RX_QUEUE_NUM 64 107 #define MAX_RX_GROUP_NUM 1 108 109 #define MAX_TX_RING_SIZE 4096 110 #define MAX_RX_RING_SIZE 4096 111 112 #define MAX_MTU 16366 113 #define MAX_RX_LIMIT_PER_INTR 4096 114 #define MAX_INTR_THROTTLING 65535 115 116 #define MAX_RX_COPY_THRESHOLD 9216 117 #define MAX_TX_COPY_THRESHOLD 9216 118 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 119 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 120 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 121 122 /* 123 * Minimum values for user configurable parameters 124 */ 125 #define MIN_TX_QUEUE_NUM 1 126 #define MIN_RX_QUEUE_NUM 1 127 #define MIN_RX_GROUP_NUM 1 128 #define MIN_TX_RING_SIZE 64 129 #define MIN_RX_RING_SIZE 64 130 131 #define MIN_MTU ETHERMIN 132 #define MIN_RX_LIMIT_PER_INTR 16 133 #define MIN_INTR_THROTTLING 0 134 #define MIN_TX_COPY_THRESHOLD 0 135 #define MIN_RX_COPY_THRESHOLD 0 136 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 137 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 138 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 139 140 /* 141 * Default values for user configurable parameters 142 */ 143 #define DEFAULT_TX_QUEUE_NUM 8 144 #define DEFAULT_RX_QUEUE_NUM 8 145 #define DEFAULT_RX_GROUP_NUM 1 146 #define DEFAULT_TX_RING_SIZE 1024 147 #define DEFAULT_RX_RING_SIZE 1024 148 149 #define DEFAULT_MTU ETHERMTU 150 #define DEFAULT_RX_LIMIT_PER_INTR 256 151 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 152 #define DEFAULT_RX_COPY_THRESHOLD 128 153 #define DEFAULT_TX_COPY_THRESHOLD 512 154 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 155 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 156 #define DEFAULT_TX_RESCHED_THRESHOLD 128 157 #define DEFAULT_FCRTH 0x20000 158 #define DEFAULT_FCRTL 0x10000 159 #define DEFAULT_FCPAUSE 0xFFFF 160 161 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 162 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 163 #define DEFAULT_LSO_ENABLE B_TRUE 164 #define DEFAULT_MR_ENABLE B_TRUE 165 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 166 167 #define IXGBE_LSO_MAXLEN 65535 168 169 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 170 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 171 #define DEFAULT_LSO_ENABLE B_TRUE 172 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 173 174 #define IXGBE_LSO_MAXLEN 65535 175 176 #define TX_DRAIN_TIME 200 177 #define RX_DRAIN_TIME 200 178 179 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 180 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 181 182 /* 183 * Limits on msi-x vectors for 82598 184 */ 185 #define IXGBE_MAX_INTR_VECTOR 18 186 #define IXGBE_MAX_OTHER_VECTOR 1 187 #define IXGBE_MAX_TCP_TIMER_VECTOR 1 188 #define IXGBE_MAX_RING_VECTOR 16 189 190 /* 191 * Extra register bit masks for 82598 192 */ 193 #define IXGBE_PCS1GANA_FDC 0x20 194 #define IXGBE_PCS1GANLP_LPFD 0x20 195 #define IXGBE_PCS1GANLP_LPHD 0x40 196 197 /* 198 * Defined for IP header alignment. 199 */ 200 #define IPHDR_ALIGN_ROOM 2 201 202 /* 203 * Bit flags for attach_progress 204 */ 205 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 206 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 207 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 208 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 209 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 210 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 211 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 212 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 213 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 214 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 215 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 216 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 217 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 218 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 219 220 #define PROP_DEFAULT_MTU "default_mtu" 221 #define PROP_FLOW_CONTROL "flow_control" 222 #define PROP_TX_QUEUE_NUM "tx_queue_number" 223 #define PROP_TX_RING_SIZE "tx_ring_size" 224 #define PROP_RX_QUEUE_NUM "rx_queue_number" 225 #define PROP_RX_RING_SIZE "rx_ring_size" 226 #define PROP_RX_GROUP_NUM "rx_group_number" 227 228 #define PROP_INTR_FORCE "intr_force" 229 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 230 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 231 #define PROP_LSO_ENABLE "lso_enable" 232 #define PROP_MR_ENABLE "mr_enable" 233 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 234 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 235 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 236 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 237 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 238 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 239 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 240 #define PROP_INTR_THROTTLING "intr_throttling" 241 #define PROP_FM_CAPABLE "fm_capable" 242 243 #define IXGBE_LB_NONE 0 244 #define IXGBE_LB_EXTERNAL 1 245 #define IXGBE_LB_INTERNAL_MAC 2 246 #define IXGBE_LB_INTERNAL_PHY 3 247 #define IXGBE_LB_INTERNAL_SERDES 4 248 249 /* 250 * Shorthand for the NDD parameters 251 */ 252 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 253 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 254 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 255 #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 256 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 257 #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 258 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 259 260 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 261 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 262 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 263 #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 264 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 265 #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 266 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 267 268 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 269 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 270 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 271 #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 272 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 273 #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 274 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 275 276 enum ioc_reply { 277 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 278 IOC_DONE, /* OK, reply sent */ 279 IOC_ACK, /* OK, just send ACK */ 280 IOC_REPLY /* OK, just send reply */ 281 }; 282 283 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 284 0, 0, (flag))) 285 286 /* 287 * Defined for ring index operations 288 * ASSERT(index < limit) 289 * ASSERT(step < limit) 290 * ASSERT(index1 < limit) 291 * ASSERT(index2 < limit) 292 */ 293 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 294 (index) + (step) : (index) + (step) - (limit)) 295 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 296 (index) - (step) : (index) + (limit) - (step)) 297 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 298 (index2) - (index1) : (index2) + (limit) - (index1)) 299 300 #define LINK_LIST_INIT(_LH) \ 301 (_LH)->head = (_LH)->tail = NULL 302 303 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 304 305 #define LIST_POP_HEAD(_LH) \ 306 (single_link_t *)(_LH)->head; \ 307 { \ 308 if ((_LH)->head != NULL) { \ 309 (_LH)->head = (_LH)->head->link; \ 310 if ((_LH)->head == NULL) \ 311 (_LH)->tail = NULL; \ 312 } \ 313 } 314 315 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 316 317 #define LIST_PUSH_TAIL(_LH, _E) \ 318 if ((_LH)->tail != NULL) { \ 319 (_LH)->tail->link = (single_link_t *)(_E); \ 320 (_LH)->tail = (single_link_t *)(_E); \ 321 } else { \ 322 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 323 } \ 324 (_E)->link = NULL; 325 326 #define LIST_GET_NEXT(_LH, _E) \ 327 (((_LH)->tail == (single_link_t *)(_E)) ? \ 328 NULL : ((single_link_t *)(_E))->link) 329 330 331 typedef struct single_link { 332 struct single_link *link; 333 } single_link_t; 334 335 typedef struct link_list { 336 single_link_t *head; 337 single_link_t *tail; 338 } link_list_t; 339 340 /* 341 * Property lookups 342 */ 343 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 344 DDI_PROP_DONTPASS, (n)) 345 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 346 DDI_PROP_DONTPASS, (n), -1) 347 348 349 /* 350 * Named Data (ND) Parameter Management Structure 351 */ 352 typedef struct { 353 struct ixgbe *private; 354 uint32_t info; 355 uint32_t min; 356 uint32_t max; 357 uint32_t val; 358 char *name; 359 } nd_param_t; 360 361 /* 362 * NDD parameter indexes, divided into: 363 * 364 * read-only parameters describing the hardware's capabilities 365 * read-write parameters controlling the advertised capabilities 366 * read-only parameters describing the partner's capabilities 367 * read-write parameters controlling the force speed and duplex 368 * read-only parameters describing the link state 369 * read-only parameters describing the driver properties 370 * read-write parameters controlling the driver properties 371 */ 372 enum { 373 PARAM_AUTONEG_CAP, 374 PARAM_PAUSE_CAP, 375 PARAM_ASYM_PAUSE_CAP, 376 PARAM_10000FDX_CAP, 377 PARAM_1000FDX_CAP, 378 PARAM_100FDX_CAP, 379 PARAM_REM_FAULT, 380 381 PARAM_ADV_AUTONEG_CAP, 382 PARAM_ADV_PAUSE_CAP, 383 PARAM_ADV_ASYM_PAUSE_CAP, 384 PARAM_ADV_10000FDX_CAP, 385 PARAM_ADV_1000FDX_CAP, 386 PARAM_ADV_100FDX_CAP, 387 PARAM_ADV_REM_FAULT, 388 389 PARAM_LP_AUTONEG_CAP, 390 PARAM_LP_PAUSE_CAP, 391 PARAM_LP_ASYM_PAUSE_CAP, 392 PARAM_LP_10000FDX_CAP, 393 PARAM_LP_1000FDX_CAP, 394 PARAM_LP_100FDX_CAP, 395 PARAM_LP_REM_FAULT, 396 397 PARAM_LINK_STATUS, 398 PARAM_LINK_SPEED, 399 PARAM_LINK_DUPLEX, 400 401 PARAM_COUNT 402 }; 403 404 typedef union ixgbe_ether_addr { 405 struct { 406 uint32_t high; 407 uint32_t low; 408 } reg; 409 struct { 410 uint8_t set; 411 uint8_t redundant; 412 uint8_t addr[ETHERADDRL]; 413 } mac; 414 } ixgbe_ether_addr_t; 415 416 typedef enum { 417 USE_NONE, 418 USE_COPY, 419 USE_DMA 420 } tx_type_t; 421 422 typedef enum { 423 RCB_FREE, 424 RCB_SENDUP 425 } rcb_state_t; 426 427 typedef struct ixgbe_tx_context { 428 uint32_t hcksum_flags; 429 uint32_t ip_hdr_len; 430 uint32_t mac_hdr_len; 431 uint32_t l4_proto; 432 uint32_t mss; 433 uint32_t l4_hdr_len; 434 boolean_t lso_flag; 435 } ixgbe_tx_context_t; 436 437 /* 438 * Hold address/length of each DMA segment 439 */ 440 typedef struct sw_desc { 441 uint64_t address; 442 size_t length; 443 } sw_desc_t; 444 445 /* 446 * Handles and addresses of DMA buffer 447 */ 448 typedef struct dma_buffer { 449 caddr_t address; /* Virtual address */ 450 uint64_t dma_address; /* DMA (Hardware) address */ 451 ddi_acc_handle_t acc_handle; /* Data access handle */ 452 ddi_dma_handle_t dma_handle; /* DMA handle */ 453 size_t size; /* Buffer size */ 454 size_t len; /* Data length in the buffer */ 455 } dma_buffer_t; 456 457 /* 458 * Tx Control Block 459 */ 460 typedef struct tx_control_block { 461 single_link_t link; 462 uint32_t frag_num; 463 uint32_t desc_num; 464 mblk_t *mp; 465 tx_type_t tx_type; 466 ddi_dma_handle_t tx_dma_handle; 467 dma_buffer_t tx_buf; 468 sw_desc_t desc[MAX_COOKIE]; 469 } tx_control_block_t; 470 471 /* 472 * RX Control Block 473 */ 474 typedef struct rx_control_block { 475 mblk_t *mp; 476 rcb_state_t state; 477 dma_buffer_t rx_buf; 478 frtn_t free_rtn; 479 struct ixgbe_rx_ring *rx_ring; 480 } rx_control_block_t; 481 482 /* 483 * Software Data Structure for Tx Ring 484 */ 485 typedef struct ixgbe_tx_ring { 486 uint32_t index; /* Ring index */ 487 uint32_t intr_vector; /* Interrupt vector index */ 488 uint32_t vect_bit; /* vector's bit in register */ 489 490 /* 491 * Mutexes 492 */ 493 kmutex_t tx_lock; 494 kmutex_t recycle_lock; 495 kmutex_t tcb_head_lock; 496 kmutex_t tcb_tail_lock; 497 498 /* 499 * Tx descriptor ring definitions 500 */ 501 dma_buffer_t tbd_area; 502 union ixgbe_adv_tx_desc *tbd_ring; 503 uint32_t tbd_head; /* Index of next tbd to recycle */ 504 uint32_t tbd_tail; /* Index of next tbd to transmit */ 505 uint32_t tbd_free; /* Number of free tbd */ 506 507 /* 508 * Tx control block list definitions 509 */ 510 tx_control_block_t *tcb_area; 511 tx_control_block_t **work_list; 512 tx_control_block_t **free_list; 513 uint32_t tcb_head; /* Head index of free list */ 514 uint32_t tcb_tail; /* Tail index of free list */ 515 uint32_t tcb_free; /* Number of free tcb in free list */ 516 517 uint32_t *tbd_head_wb; /* Head write-back */ 518 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 519 520 /* 521 * s/w context structure for TCP/UDP checksum offload 522 * and LSO. 523 */ 524 ixgbe_tx_context_t tx_context; 525 526 /* 527 * Tx ring settings and status 528 */ 529 uint32_t ring_size; /* Tx descriptor ring size */ 530 uint32_t free_list_size; /* Tx free list size */ 531 uint32_t copy_thresh; 532 uint32_t recycle_thresh; 533 uint32_t overload_thresh; 534 uint32_t resched_thresh; 535 536 boolean_t reschedule; 537 uint32_t recycle_fail; 538 uint32_t stall_watchdog; 539 540 #ifdef IXGBE_DEBUG 541 /* 542 * Debug statistics 543 */ 544 uint32_t stat_overload; 545 uint32_t stat_fail_no_tbd; 546 uint32_t stat_fail_no_tcb; 547 uint32_t stat_fail_dma_bind; 548 uint32_t stat_reschedule; 549 uint32_t stat_lso_header_fail; 550 #endif 551 552 mac_ring_handle_t ring_handle; 553 554 /* 555 * Pointer to the ixgbe struct 556 */ 557 struct ixgbe *ixgbe; 558 } ixgbe_tx_ring_t; 559 560 /* 561 * Software Receive Ring 562 */ 563 typedef struct ixgbe_rx_ring { 564 uint32_t index; /* Ring index */ 565 uint32_t intr_vector; /* Interrupt vector index */ 566 uint32_t vect_bit; /* vector's bit in register */ 567 568 /* 569 * Mutexes 570 */ 571 kmutex_t rx_lock; /* Rx access lock */ 572 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 573 574 /* 575 * Rx descriptor ring definitions 576 */ 577 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 578 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 579 uint32_t rbd_next; /* Index of next rx desc */ 580 581 /* 582 * Rx control block list definitions 583 */ 584 rx_control_block_t *rcb_area; 585 rx_control_block_t **work_list; /* Work list of rcbs */ 586 rx_control_block_t **free_list; /* Free list of rcbs */ 587 uint32_t rcb_head; /* Index of next free rcb */ 588 uint32_t rcb_tail; /* Index to put recycled rcb */ 589 uint32_t rcb_free; /* Number of free rcbs */ 590 591 /* 592 * Rx ring settings and status 593 */ 594 uint32_t ring_size; /* Rx descriptor ring size */ 595 uint32_t free_list_size; /* Rx free list size */ 596 uint32_t limit_per_intr; /* Max packets per interrupt */ 597 uint32_t copy_thresh; 598 599 #ifdef IXGBE_DEBUG 600 /* 601 * Debug statistics 602 */ 603 uint32_t stat_frame_error; 604 uint32_t stat_cksum_error; 605 uint32_t stat_exceed_pkt; 606 #endif 607 608 mac_ring_handle_t ring_handle; 609 uint64_t ring_gen_num; 610 611 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 612 } ixgbe_rx_ring_t; 613 614 /* 615 * Software Receive Ring Group 616 */ 617 typedef struct ixgbe_rx_group { 618 uint32_t index; /* Group index */ 619 mac_group_handle_t group_handle; /* call back group handle */ 620 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 621 } ixgbe_rx_group_t; 622 623 /* 624 * structure to map ring cleanup to msi-x vector 625 */ 626 typedef struct ixgbe_ring_vector { 627 struct ixgbe *ixgbe; /* point to my adapter */ 628 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 629 int rxr_cnt; /* count rx rings */ 630 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 631 int txr_cnt; /* count tx rings */ 632 } ixgbe_ring_vector_t; 633 634 /* 635 * Software adapter state 636 */ 637 typedef struct ixgbe { 638 int instance; 639 mac_handle_t mac_hdl; 640 dev_info_t *dip; 641 struct ixgbe_hw hw; 642 struct ixgbe_osdep osdep; 643 644 uint32_t ixgbe_state; 645 link_state_t link_state; 646 uint32_t link_speed; 647 uint32_t link_duplex; 648 uint32_t link_down_timeout; 649 650 uint32_t reset_count; 651 uint32_t attach_progress; 652 uint32_t loopback_mode; 653 uint32_t default_mtu; 654 uint32_t max_frame_size; 655 656 /* 657 * Each msi-x vector: map vector to ring cleanup 658 */ 659 ixgbe_ring_vector_t vect_map[IXGBE_MAX_RING_VECTOR]; 660 661 /* 662 * Receive Rings 663 */ 664 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 665 uint32_t num_rx_rings; /* Number of rx rings in use */ 666 uint32_t rx_ring_size; /* Rx descriptor ring size */ 667 uint32_t rx_buf_size; /* Rx buffer size */ 668 669 /* 670 * Receive Groups 671 */ 672 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 673 uint32_t num_rx_groups; /* Number of rx groups in use */ 674 675 /* 676 * Transmit Rings 677 */ 678 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 679 uint32_t num_tx_rings; /* Number of tx rings in use */ 680 uint32_t tx_ring_size; /* Tx descriptor ring size */ 681 uint32_t tx_buf_size; /* Tx buffer size */ 682 683 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 684 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 685 boolean_t lso_enable; /* Large Segment Offload */ 686 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 687 uint32_t tx_copy_thresh; /* Tx copy threshold */ 688 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 689 uint32_t tx_overload_thresh; /* Tx overload threshold */ 690 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 691 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 692 uint32_t rx_copy_thresh; /* Rx copy threshold */ 693 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 694 uint32_t intr_throttling[IXGBE_MAX_RING_VECTOR]; 695 uint32_t intr_force; 696 int fm_capabilities; /* FMA capabilities */ 697 698 int intr_type; 699 int intr_cnt; 700 int intr_cap; 701 size_t intr_size; 702 uint_t intr_pri; 703 ddi_intr_handle_t *htable; 704 uint32_t eims_mask; 705 706 kmutex_t gen_lock; /* General lock for device access */ 707 kmutex_t watchdog_lock; 708 709 boolean_t watchdog_enable; 710 boolean_t watchdog_start; 711 timeout_id_t watchdog_tid; 712 713 boolean_t unicst_init; 714 uint32_t unicst_avail; 715 uint32_t unicst_total; 716 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 717 uint32_t mcast_count; 718 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 719 720 ulong_t sys_page_size; 721 722 /* 723 * Kstat definitions 724 */ 725 kstat_t *ixgbe_ks; 726 727 /* 728 * NDD definitions 729 */ 730 caddr_t nd_data; 731 nd_param_t nd_params[PARAM_COUNT]; 732 } ixgbe_t; 733 734 typedef struct ixgbe_stat { 735 kstat_named_t link_speed; /* Link Speed */ 736 737 kstat_named_t reset_count; /* Reset Count */ 738 739 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 740 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 741 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 742 743 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 744 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 745 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 746 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 747 kstat_named_t tx_reschedule; /* Tx Reschedule */ 748 749 kstat_named_t gprc; /* Good Packets Received Count */ 750 kstat_named_t gptc; /* Good Packets Xmitted Count */ 751 kstat_named_t gor; /* Good Octets Received Count */ 752 kstat_named_t got; /* Good Octets Xmitd Count */ 753 kstat_named_t prc64; /* Packets Received - 64b */ 754 kstat_named_t prc127; /* Packets Received - 65-127b */ 755 kstat_named_t prc255; /* Packets Received - 127-255b */ 756 kstat_named_t prc511; /* Packets Received - 256-511b */ 757 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 758 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 759 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 760 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 761 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 762 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 763 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 764 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 765 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 766 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 767 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 768 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 769 770 kstat_named_t crcerrs; /* CRC Error Count */ 771 kstat_named_t illerrc; /* Illegal Byte Error Count */ 772 kstat_named_t errbc; /* Error Byte Count */ 773 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 774 kstat_named_t mpc; /* Missed Packets Count */ 775 kstat_named_t mlfc; /* MAC Local Fault Count */ 776 kstat_named_t mrfc; /* MAC Remote Fault Count */ 777 kstat_named_t rlec; /* Receive Length Error Count */ 778 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 779 kstat_named_t lxonrxc; /* Link XON Received Count */ 780 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 781 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 782 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 783 kstat_named_t mprc; /* Multicast Pkts Received Count */ 784 kstat_named_t rnbc; /* Receive No Buffers Count */ 785 kstat_named_t ruc; /* Receive Undersize Count */ 786 kstat_named_t rfc; /* Receive Frag Count */ 787 kstat_named_t roc; /* Receive Oversize Count */ 788 kstat_named_t rjc; /* Receive Jabber Count */ 789 kstat_named_t tor; /* Total Octets Recvd Count */ 790 kstat_named_t tot; /* Total Octets Xmitted Count */ 791 kstat_named_t tpr; /* Total Packets Received */ 792 kstat_named_t tpt; /* Total Packets Xmitted */ 793 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 794 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 795 } ixgbe_stat_t; 796 797 /* 798 * Function prototypes in ixgbe_buf.c 799 */ 800 int ixgbe_alloc_dma(ixgbe_t *); 801 void ixgbe_free_dma(ixgbe_t *); 802 void ixgbe_set_fma_flags(int, int); 803 804 /* 805 * Function prototypes in ixgbe_main.c 806 */ 807 int ixgbe_start(ixgbe_t *); 808 void ixgbe_stop(ixgbe_t *); 809 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 810 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 811 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 812 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 813 814 void ixgbe_enable_watchdog_timer(ixgbe_t *); 815 void ixgbe_disable_watchdog_timer(ixgbe_t *); 816 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 817 818 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 819 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 820 void ixgbe_fm_ereport(ixgbe_t *, char *); 821 822 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 823 mac_ring_info_t *, mac_ring_handle_t); 824 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 825 mac_group_info_t *, mac_group_handle_t); 826 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 827 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 828 829 /* 830 * Function prototypes in ixgbe_gld.c 831 */ 832 int ixgbe_m_start(void *); 833 void ixgbe_m_stop(void *); 834 int ixgbe_m_promisc(void *, boolean_t); 835 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 836 int ixgbe_m_stat(void *, uint_t, uint64_t *); 837 void ixgbe_m_resources(void *); 838 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 839 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 840 841 /* 842 * Function prototypes in ixgbe_rx.c 843 */ 844 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 845 void ixgbe_rx_recycle(caddr_t arg); 846 mblk_t *ixgbe_ring_rx_poll(void *, int); 847 848 /* 849 * Function prototypes in ixgbe_tx.c 850 */ 851 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 852 void ixgbe_free_tcb(tx_control_block_t *); 853 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 854 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 855 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 856 857 /* 858 * Function prototypes in ixgbe_log.c 859 */ 860 void ixgbe_notice(void *, const char *, ...); 861 void ixgbe_log(void *, const char *, ...); 862 void ixgbe_error(void *, const char *, ...); 863 864 /* 865 * Function prototypes in ixgbe_ndd.c 866 */ 867 int ixgbe_nd_init(ixgbe_t *); 868 void ixgbe_nd_cleanup(ixgbe_t *); 869 enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 870 871 /* 872 * Function prototypes in ixgbe_stat.c 873 */ 874 int ixgbe_init_stats(ixgbe_t *); 875 876 #ifdef __cplusplus 877 } 878 #endif 879 880 #endif /* _IXGBE_SW_H */ 881