1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 * Copyright 2014 Pluribus Networks Inc. 29 * Copyright (c) 2017, Joyent, Inc. 30 * Copyright 2020 Oxide Computer Company 31 */ 32 33 #ifndef _IGB_SW_H 34 #define _IGB_SW_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include <sys/types.h> 41 #include <sys/conf.h> 42 #include <sys/debug.h> 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/strsun.h> 46 #include <sys/strlog.h> 47 #include <sys/kmem.h> 48 #include <sys/stat.h> 49 #include <sys/kstat.h> 50 #include <sys/modctl.h> 51 #include <sys/errno.h> 52 #include <sys/dlpi.h> 53 #include <sys/mac_provider.h> 54 #include <sys/mac_ether.h> 55 #include <sys/vlan.h> 56 #include <sys/ddi.h> 57 #include <sys/sunddi.h> 58 #include <sys/pci.h> 59 #include <sys/pcie.h> 60 #include <sys/sdt.h> 61 #include <sys/ethernet.h> 62 #include <sys/pattr.h> 63 #include <sys/strsubr.h> 64 #include <sys/netlb.h> 65 #include <sys/random.h> 66 #include <inet/common.h> 67 #include <inet/tcp.h> 68 #include <inet/ip.h> 69 #include <inet/mi.h> 70 #include <inet/nd.h> 71 #include <sys/ddifm.h> 72 #include <sys/fm/protocol.h> 73 #include <sys/fm/util.h> 74 #include <sys/fm/io/ddi.h> 75 #include <sys/ddi_ufm.h> 76 #include "e1000_api.h" 77 #include "e1000_82575.h" 78 79 80 #define MODULE_NAME "igb" /* module name */ 81 82 #define IGB_SUCCESS DDI_SUCCESS 83 #define IGB_FAILURE DDI_FAILURE 84 85 #define IGB_UNKNOWN 0x00 86 #define IGB_INITIALIZED 0x01 87 #define IGB_STARTED 0x02 88 #define IGB_SUSPENDED 0x04 89 #define IGB_STALL 0x08 90 #define IGB_ERROR 0x80 91 92 #define IGB_RX_STOPPED 0x1 93 94 #define IGB_INTR_NONE 0 95 #define IGB_INTR_MSIX 1 96 #define IGB_INTR_MSI 2 97 #define IGB_INTR_LEGACY 3 98 99 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 100 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 101 102 #define IGB_NO_POLL -1 103 #define IGB_NO_FREE_SLOT -1 104 105 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 106 #define MCAST_ALLOC_COUNT 256 107 #define MAX_COOKIE 18 108 #define MIN_NUM_TX_DESC 2 109 110 /* 111 * Number of settings for interrupt throttle rate (ITR). There is one of 112 * these per msi-x vector and it needs to be the maximum of all silicon 113 * types supported by this driver. 114 */ 115 #define MAX_NUM_EITR 25 116 117 /* 118 * Maximum values for user configurable parameters 119 */ 120 #define MAX_TX_RING_SIZE 4096 121 #define MAX_RX_RING_SIZE 4096 122 #define MAX_RX_GROUP_NUM 4 123 124 #define MAX_MTU 9000 125 #define MAX_RX_LIMIT_PER_INTR 4096 126 127 #define MAX_RX_COPY_THRESHOLD 9216 128 #define MAX_TX_COPY_THRESHOLD 9216 129 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 130 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 131 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 132 #define MAX_MCAST_NUM 8192 133 134 /* 135 * Minimum values for user configurable parameters 136 */ 137 #define MIN_TX_RING_SIZE 64 138 #define MIN_RX_RING_SIZE 64 139 #define MIN_RX_GROUP_NUM 1 140 141 #define MIN_MTU ETHERMIN 142 #define MIN_RX_LIMIT_PER_INTR 16 143 144 #define MIN_RX_COPY_THRESHOLD 0 145 #define MIN_TX_COPY_THRESHOLD 0 146 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 147 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 148 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 149 #define MIN_MCAST_NUM 8 150 151 /* 152 * Default values for user configurable parameters 153 */ 154 #define DEFAULT_TX_RING_SIZE 512 155 #define DEFAULT_RX_RING_SIZE 512 156 #define DEFAULT_RX_GROUP_NUM 1 157 158 #define DEFAULT_MTU ETHERMTU 159 #define DEFAULT_RX_LIMIT_PER_INTR 256 160 161 #define DEFAULT_RX_COPY_THRESHOLD 128 162 #define DEFAULT_TX_COPY_THRESHOLD 512 163 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 164 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 165 #define DEFAULT_TX_RESCHED_THRESHOLD 128 166 #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32 167 #define DEFAULT_MCAST_NUM 4096 168 169 #define IGB_LSO_MAXLEN 65535 170 171 #define TX_DRAIN_TIME 200 172 #define RX_DRAIN_TIME 200 173 174 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 175 176 /* 177 * Defined for IP header alignment. 178 */ 179 #define IPHDR_ALIGN_ROOM 2 180 181 /* 182 * Bit flags for attach_progress 183 */ 184 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 185 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 186 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 187 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 188 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 189 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 190 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 191 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 192 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 193 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 194 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 195 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 196 #define ATTACH_PROGRESS_UFM 0x4000 /* UFM enabled */ 197 198 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 199 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 200 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 201 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 202 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 203 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 204 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 205 #define PROP_DEFAULT_MTU "default_mtu" 206 #define PROP_FLOW_CONTROL "flow_control" 207 #define PROP_TX_RING_SIZE "tx_ring_size" 208 #define PROP_RX_RING_SIZE "rx_ring_size" 209 #define PROP_MR_ENABLE "mr_enable" 210 #define PROP_RX_GROUP_NUM "rx_group_number" 211 212 #define PROP_INTR_FORCE "intr_force" 213 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 214 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 215 #define PROP_LSO_ENABLE "lso_enable" 216 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 217 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 218 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 219 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 220 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 221 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 222 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 223 #define PROP_INTR_THROTTLING "intr_throttling" 224 #define PROP_MCAST_MAX_NUM "mcast_max_num" 225 226 #define IGB_LB_NONE 0 227 #define IGB_LB_EXTERNAL 1 228 #define IGB_LB_INTERNAL_PHY 3 229 #define IGB_LB_INTERNAL_SERDES 4 230 231 enum ioc_reply { 232 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 233 IOC_DONE, /* OK, reply sent */ 234 IOC_ACK, /* OK, just send ACK */ 235 IOC_REPLY /* OK, just send reply */ 236 }; 237 238 /* 239 * For s/w context extraction from a tx frame 240 */ 241 #define TX_CXT_SUCCESS 0 242 #define TX_CXT_E_LSO_CSUM (-1) 243 #define TX_CXT_E_ETHER_TYPE (-2) 244 245 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 246 0, 0, (flag))) 247 248 /* 249 * Defined for ring index operations 250 * ASSERT(index < limit) 251 * ASSERT(step < limit) 252 * ASSERT(index1 < limit) 253 * ASSERT(index2 < limit) 254 */ 255 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 256 (index) + (step) : (index) + (step) - (limit)) 257 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 258 (index) - (step) : (index) + (limit) - (step)) 259 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 260 (index2) - (index1) : (index2) + (limit) - (index1)) 261 262 #define LINK_LIST_INIT(_LH) \ 263 (_LH)->head = (_LH)->tail = NULL 264 265 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 266 267 #define LIST_POP_HEAD(_LH) \ 268 (single_link_t *)(_LH)->head; \ 269 { \ 270 if ((_LH)->head != NULL) { \ 271 (_LH)->head = (_LH)->head->link; \ 272 if ((_LH)->head == NULL) \ 273 (_LH)->tail = NULL; \ 274 } \ 275 } 276 277 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 278 279 #define LIST_PUSH_TAIL(_LH, _E) \ 280 if ((_LH)->tail != NULL) { \ 281 (_LH)->tail->link = (single_link_t *)(_E); \ 282 (_LH)->tail = (single_link_t *)(_E); \ 283 } else { \ 284 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 285 } \ 286 (_E)->link = NULL; 287 288 #define LIST_GET_NEXT(_LH, _E) \ 289 (((_LH)->tail == (single_link_t *)(_E)) ? \ 290 NULL : ((single_link_t *)(_E))->link) 291 292 293 typedef struct single_link { 294 struct single_link *link; 295 } single_link_t; 296 297 typedef struct link_list { 298 single_link_t *head; 299 single_link_t *tail; 300 } link_list_t; 301 302 /* 303 * Property lookups 304 */ 305 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 306 DDI_PROP_DONTPASS, (n)) 307 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 308 DDI_PROP_DONTPASS, (n), -1) 309 310 311 /* capability/feature flags */ 312 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 313 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 314 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 315 316 /* function pointer for nic-specific functions */ 317 typedef void (*igb_nic_func_t)(struct igb *); 318 319 /* adapter-specific info for each supported device type */ 320 typedef struct adapter_info { 321 /* limits */ 322 uint32_t max_rx_que_num; /* maximum number of rx queues */ 323 uint32_t min_rx_que_num; /* minimum number of rx queues */ 324 uint32_t def_rx_que_num; /* default number of rx queues */ 325 uint32_t max_tx_que_num; /* maximum number of tx queues */ 326 uint32_t min_tx_que_num; /* minimum number of tx queues */ 327 uint32_t def_tx_que_num; /* default number of tx queues */ 328 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 329 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 330 uint32_t def_intr_throttle; /* default interrupt throttle */ 331 /* function pointers */ 332 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 333 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 334 /* capabilities */ 335 uint32_t flags; /* capability flags */ 336 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 337 } adapter_info_t; 338 339 typedef union igb_ether_addr { 340 struct { 341 uint32_t high; 342 uint32_t low; 343 } reg; 344 struct { 345 uint8_t set; 346 uint8_t group_index; 347 uint8_t addr[ETHERADDRL]; 348 } mac; 349 } igb_ether_addr_t; 350 351 typedef enum { 352 USE_NONE, 353 USE_COPY, 354 USE_DMA 355 } tx_type_t; 356 357 typedef struct tx_context { 358 uint32_t hcksum_flags; 359 uint32_t ip_hdr_len; 360 uint32_t mac_hdr_len; 361 uint32_t l3_proto; 362 uint32_t l4_proto; 363 uint32_t mss; 364 uint32_t l4_hdr_len; 365 boolean_t lso_flag; 366 } tx_context_t; 367 368 /* Hold address/length of each DMA segment */ 369 typedef struct sw_desc { 370 uint64_t address; 371 size_t length; 372 } sw_desc_t; 373 374 /* Handles and addresses of DMA buffer */ 375 typedef struct dma_buffer { 376 caddr_t address; /* Virtual address */ 377 uint64_t dma_address; /* DMA (Hardware) address */ 378 ddi_acc_handle_t acc_handle; /* Data access handle */ 379 ddi_dma_handle_t dma_handle; /* DMA handle */ 380 size_t size; /* Buffer size */ 381 size_t len; /* Data length in the buffer */ 382 } dma_buffer_t; 383 384 /* 385 * Tx Control Block 386 */ 387 typedef struct tx_control_block { 388 single_link_t link; 389 uint32_t last_index; 390 uint32_t frag_num; 391 uint32_t desc_num; 392 mblk_t *mp; 393 tx_type_t tx_type; 394 ddi_dma_handle_t tx_dma_handle; 395 dma_buffer_t tx_buf; 396 sw_desc_t desc[MAX_COOKIE]; 397 } tx_control_block_t; 398 399 /* 400 * RX Control Block 401 */ 402 typedef struct rx_control_block { 403 mblk_t *mp; 404 uint32_t ref_cnt; 405 dma_buffer_t rx_buf; 406 frtn_t free_rtn; 407 struct igb_rx_data *rx_data; 408 } rx_control_block_t; 409 410 /* 411 * Software Data Structure for Tx Ring 412 */ 413 typedef struct igb_tx_ring { 414 uint32_t index; /* Ring index */ 415 uint32_t intr_vector; /* Interrupt vector index */ 416 417 /* 418 * Mutexes 419 */ 420 kmutex_t tx_lock; 421 kmutex_t recycle_lock; 422 kmutex_t tcb_head_lock; 423 kmutex_t tcb_tail_lock; 424 425 /* 426 * Tx descriptor ring definitions 427 */ 428 dma_buffer_t tbd_area; 429 union e1000_adv_tx_desc *tbd_ring; 430 uint32_t tbd_head; /* Index of next tbd to recycle */ 431 uint32_t tbd_tail; /* Index of next tbd to transmit */ 432 uint32_t tbd_free; /* Number of free tbd */ 433 434 /* 435 * Tx control block list definitions 436 */ 437 tx_control_block_t *tcb_area; 438 tx_control_block_t **work_list; 439 tx_control_block_t **free_list; 440 uint32_t tcb_head; /* Head index of free list */ 441 uint32_t tcb_tail; /* Tail index of free list */ 442 uint32_t tcb_free; /* Number of free tcb in free list */ 443 444 uint32_t *tbd_head_wb; /* Head write-back */ 445 uint32_t (*tx_recycle)(struct igb_tx_ring *); 446 447 /* 448 * s/w context structure for TCP/UDP checksum offload and LSO. 449 */ 450 tx_context_t tx_context; 451 452 /* 453 * Tx ring settings and status 454 */ 455 uint32_t ring_size; /* Tx descriptor ring size */ 456 uint32_t free_list_size; /* Tx free list size */ 457 458 boolean_t reschedule; 459 uint32_t recycle_fail; 460 uint32_t stall_watchdog; 461 462 /* 463 * Per-ring statistics 464 */ 465 uint64_t tx_pkts; /* Packets Transmitted Count */ 466 uint64_t tx_bytes; /* Bytes Transmitted Count */ 467 468 #ifdef IGB_DEBUG 469 /* 470 * Debug statistics 471 */ 472 uint32_t stat_overload; 473 uint32_t stat_fail_no_tbd; 474 uint32_t stat_fail_no_tcb; 475 uint32_t stat_fail_dma_bind; 476 uint32_t stat_reschedule; 477 uint32_t stat_pkt_cnt; 478 #endif 479 480 /* 481 * Pointer to the igb struct 482 */ 483 struct igb *igb; 484 mac_ring_handle_t ring_handle; /* call back ring handle */ 485 } igb_tx_ring_t; 486 487 /* 488 * Software Receive Ring 489 */ 490 typedef struct igb_rx_data { 491 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 492 493 /* 494 * Rx descriptor ring definitions 495 */ 496 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 497 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 498 uint32_t rbd_next; /* Index of next rx desc */ 499 500 /* 501 * Rx control block list definitions 502 */ 503 rx_control_block_t *rcb_area; 504 rx_control_block_t **work_list; /* Work list of rcbs */ 505 rx_control_block_t **free_list; /* Free list of rcbs */ 506 uint32_t rcb_head; /* Index of next free rcb */ 507 uint32_t rcb_tail; /* Index to put recycled rcb */ 508 uint32_t rcb_free; /* Number of free rcbs */ 509 510 /* 511 * Rx sw ring settings and status 512 */ 513 uint32_t ring_size; /* Rx descriptor ring size */ 514 uint32_t free_list_size; /* Rx free list size */ 515 516 uint32_t rcb_pending; 517 uint32_t flag; 518 519 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 520 } igb_rx_data_t; 521 522 /* 523 * Software Data Structure for Rx Ring 524 */ 525 typedef struct igb_rx_ring { 526 uint32_t index; /* Ring index */ 527 uint32_t intr_vector; /* Interrupt vector index */ 528 529 igb_rx_data_t *rx_data; /* Rx software ring */ 530 531 kmutex_t rx_lock; /* Rx access lock */ 532 533 /* 534 * Per-ring statistics 535 */ 536 uint64_t rx_pkts; /* Packets Received Count */ 537 uint64_t rx_bytes; /* Bytes Received Count */ 538 539 #ifdef IGB_DEBUG 540 /* 541 * Debug statistics 542 */ 543 uint32_t stat_frame_error; 544 uint32_t stat_cksum_error; 545 uint32_t stat_exceed_pkt; 546 uint32_t stat_pkt_cnt; 547 #endif 548 549 struct igb *igb; /* Pointer to igb struct */ 550 mac_ring_handle_t ring_handle; /* call back ring handle */ 551 uint32_t group_index; /* group index */ 552 uint64_t ring_gen_num; 553 } igb_rx_ring_t; 554 555 /* 556 * Software Receive Ring Group 557 */ 558 typedef struct igb_rx_group { 559 uint32_t index; /* Group index */ 560 mac_group_handle_t group_handle; /* call back group handle */ 561 struct igb *igb; /* Pointer to igb struct */ 562 } igb_rx_group_t; 563 564 typedef enum { 565 IGB_ETS_INDEX_INTERNAL = 0, 566 IGB_ETS_INDEX_EXTERNAL_1 = 1, 567 IGB_ETS_INDEX_EXTERNAL_2 = 2, 568 IGB_ETS_INDEX_EXTERNAL_3 = 3 569 } igb_ets_index_t; 570 571 typedef enum { 572 IGB_ETS_LOC_NA = 0, 573 IGB_ETS_LOC_HOT_SPOT = 2, 574 IGB_ETS_LOC_PCIE = 3, 575 IGB_ETS_LOC_BULKHEAD = 4, 576 IGB_ETS_LOC_BOARD = 5, 577 IGB_ETS_LOC_INLET = 7 578 } igb_ets_loc_t; 579 580 /* 581 * Sensor data 582 */ 583 typedef struct igb_ets { 584 igb_ets_index_t iet_index; 585 igb_ets_loc_t iet_loc; 586 uint8_t iet_thresh; 587 id_t iet_ksensor; 588 } igb_ets_t; 589 590 /* 591 * There are only four words defined for sensors. 592 */ 593 #define IGB_ETS_MAX 4 594 595 typedef struct igb_sensors { 596 boolean_t isn_valid; 597 id_t isn_reg_ksensor; 598 uint_t isn_nents; 599 igb_ets_t isn_ets[IGB_ETS_MAX]; 600 } igb_sensors_t; 601 602 typedef struct igb { 603 int instance; 604 mac_handle_t mac_hdl; 605 dev_info_t *dip; 606 struct e1000_hw hw; 607 struct igb_osdep osdep; 608 609 adapter_info_t *capab; /* adapter capabilities */ 610 611 uint32_t igb_state; 612 link_state_t link_state; 613 uint32_t link_speed; 614 uint32_t link_duplex; 615 boolean_t link_complete; 616 timeout_id_t link_tid; 617 618 uint32_t reset_count; 619 uint32_t attach_progress; 620 uint32_t loopback_mode; 621 uint32_t default_mtu; 622 uint32_t max_frame_size; 623 uint32_t dout_sync; 624 625 uint32_t rcb_pending; 626 627 uint32_t mr_enable; /* Enable multiple rings */ 628 uint32_t vmdq_mode; /* Mode of VMDq */ 629 630 /* 631 * Receive Rings and Groups 632 */ 633 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 634 uint32_t num_rx_rings; /* Number of rx rings in use */ 635 uint32_t rx_ring_size; /* Rx descriptor ring size */ 636 uint32_t rx_buf_size; /* Rx buffer size */ 637 igb_rx_group_t *rx_groups; /* Array of rx groups */ 638 uint32_t num_rx_groups; /* Number of rx groups in use */ 639 640 /* 641 * Transmit Rings 642 */ 643 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 644 uint32_t num_tx_rings; /* Number of tx rings in use */ 645 uint32_t tx_ring_size; /* Tx descriptor ring size */ 646 uint32_t tx_buf_size; /* Tx buffer size */ 647 648 boolean_t tx_ring_init; 649 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 650 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 651 boolean_t lso_enable; /* Large Segment Offload */ 652 uint32_t tx_copy_thresh; /* Tx copy threshold */ 653 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 654 uint32_t tx_overload_thresh; /* Tx overload threshold */ 655 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 656 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 657 uint32_t rx_copy_thresh; /* Rx copy threshold */ 658 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 659 660 uint32_t intr_throttling[MAX_NUM_EITR]; 661 uint32_t intr_force; 662 663 int intr_type; 664 int intr_cnt; 665 int intr_cap; 666 size_t intr_size; 667 uint_t intr_pri; 668 ddi_intr_handle_t *htable; 669 uint32_t eims_mask; 670 uint32_t ims_mask; 671 672 kmutex_t gen_lock; /* General lock for device access */ 673 kmutex_t watchdog_lock; 674 kmutex_t link_lock; 675 kmutex_t rx_pending_lock; 676 677 boolean_t watchdog_enable; 678 boolean_t watchdog_start; 679 timeout_id_t watchdog_tid; 680 681 boolean_t unicst_init; 682 uint32_t unicst_avail; 683 uint32_t unicst_total; 684 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 685 uint32_t mcast_count; 686 uint32_t mcast_alloc_count; 687 uint32_t mcast_max_num; 688 struct ether_addr *mcast_table; 689 690 /* 691 * LED related functions 692 */ 693 boolean_t igb_led_setup; 694 695 /* 696 * Kstat definitions 697 */ 698 kstat_t *igb_ks; 699 700 /* 701 * Backing store for MAC stats. These are reported via GLDv3, instead 702 * of via our private kstat structure. 703 */ 704 uint64_t stat_tor; /* rbytes */ 705 uint64_t stat_tpr; /* rpackets */ 706 uint64_t stat_tot; /* obytes */ 707 uint64_t stat_tpt; /* opackets */ 708 uint64_t stat_colc; /* collisions */ 709 uint64_t stat_mcc; /* multi colls */ 710 uint64_t stat_scc; /* single colls */ 711 uint64_t stat_ecol; /* excessive colls */ 712 uint64_t stat_latecol; /* late colls */ 713 uint64_t stat_bptc; /* xmit bcast */ 714 uint64_t stat_mptc; /* xmit bcast */ 715 uint64_t stat_bprc; /* recv bcast */ 716 uint64_t stat_mprc; /* recv mcast */ 717 uint64_t stat_rnbc; /* recv nobuf */ 718 uint64_t stat_roc; /* recv toolong */ 719 uint64_t stat_sec; /* sqe errors */ 720 uint64_t stat_dc; /* defer */ 721 uint64_t stat_algnerrc; /* align errors */ 722 uint64_t stat_crcerrs; /* crc errors */ 723 uint64_t stat_cexterr; /* carrier extension errors */ 724 uint64_t stat_ruc; /* recv tooshort */ 725 uint64_t stat_rjc; /* recv jabber */ 726 uint64_t stat_rxerrc; /* recv errors */ 727 728 uint32_t param_en_1000fdx_cap:1, 729 param_en_1000hdx_cap:1, 730 param_en_100t4_cap:1, 731 param_en_100fdx_cap:1, 732 param_en_100hdx_cap:1, 733 param_en_10fdx_cap:1, 734 param_en_10hdx_cap:1, 735 param_1000fdx_cap:1, 736 param_1000hdx_cap:1, 737 param_100t4_cap:1, 738 param_100fdx_cap:1, 739 param_100hdx_cap:1, 740 param_10fdx_cap:1, 741 param_10hdx_cap:1, 742 param_autoneg_cap:1, 743 param_pause_cap:1, 744 param_asym_pause_cap:1, 745 param_rem_fault:1, 746 param_adv_1000fdx_cap:1, 747 param_adv_1000hdx_cap:1, 748 param_adv_100t4_cap:1, 749 param_adv_100fdx_cap:1, 750 param_adv_100hdx_cap:1, 751 param_adv_10fdx_cap:1, 752 param_adv_10hdx_cap:1, 753 param_adv_autoneg_cap:1, 754 param_adv_pause_cap:1, 755 param_adv_asym_pause_cap:1, 756 param_adv_rem_fault:1, 757 param_lp_1000fdx_cap:1, 758 param_lp_1000hdx_cap:1, 759 param_lp_100t4_cap:1; 760 761 uint32_t param_lp_100fdx_cap:1, 762 param_lp_100hdx_cap:1, 763 param_lp_10fdx_cap:1, 764 param_lp_10hdx_cap:1, 765 param_lp_autoneg_cap:1, 766 param_lp_pause_cap:1, 767 param_lp_asym_pause_cap:1, 768 param_lp_rem_fault:1, 769 param_pad_to_32:24; 770 771 /* 772 * FMA capabilities 773 */ 774 int fm_capabilities; 775 776 ulong_t page_size; 777 ddi_ufm_handle_t *igb_ufmh; 778 igb_sensors_t igb_sensors; 779 } igb_t; 780 781 typedef struct igb_stat { 782 783 kstat_named_t reset_count; /* Reset Count */ 784 kstat_named_t dout_sync; /* DMA out of sync */ 785 #ifdef IGB_DEBUG 786 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 787 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 788 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 789 790 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 791 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 792 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 793 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 794 kstat_named_t tx_reschedule; /* Tx Reschedule */ 795 796 kstat_named_t gprc; /* Good Packets Received Count */ 797 kstat_named_t gptc; /* Good Packets Xmitted Count */ 798 kstat_named_t gor; /* Good Octets Received Count */ 799 kstat_named_t got; /* Good Octets Xmitd Count */ 800 kstat_named_t prc64; /* Packets Received - 64b */ 801 kstat_named_t prc127; /* Packets Received - 65-127b */ 802 kstat_named_t prc255; /* Packets Received - 127-255b */ 803 kstat_named_t prc511; /* Packets Received - 256-511b */ 804 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 805 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 806 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 807 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 808 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 809 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 810 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 811 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 812 #endif 813 kstat_named_t symerrs; /* Symbol Error Count */ 814 kstat_named_t mpc; /* Missed Packet Count */ 815 kstat_named_t rlec; /* Receive Length Error Count */ 816 kstat_named_t xonrxc; /* XON Received Count */ 817 kstat_named_t xontxc; /* XON Xmitted Count */ 818 kstat_named_t xoffrxc; /* XOFF Received Count */ 819 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 820 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 821 kstat_named_t rfc; /* Receive Frag Count */ 822 kstat_named_t tncrs; /* Transmit with no CRS */ 823 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 824 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 825 } igb_stat_t; 826 827 /* 828 * Function prototypes in e1000_osdep.c 829 */ 830 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 831 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 832 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 833 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 834 void e1000_rar_clear(struct e1000_hw *, uint32_t); 835 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 836 uint32_t, uint8_t); 837 838 /* 839 * Function prototypes in igb_buf.c 840 */ 841 int igb_alloc_dma(igb_t *); 842 void igb_free_dma(igb_t *); 843 void igb_free_dma_buffer(dma_buffer_t *); 844 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 845 void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 846 847 /* 848 * Function prototypes in igb_main.c 849 */ 850 int igb_start(igb_t *, boolean_t); 851 void igb_stop(igb_t *, boolean_t); 852 int igb_setup_link(igb_t *, boolean_t); 853 int igb_unicst_find(igb_t *, const uint8_t *); 854 int igb_unicst_set(igb_t *, const uint8_t *, int); 855 int igb_multicst_add(igb_t *, const uint8_t *); 856 int igb_multicst_remove(igb_t *, const uint8_t *); 857 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 858 void igb_enable_watchdog_timer(igb_t *); 859 void igb_disable_watchdog_timer(igb_t *); 860 int igb_atomic_reserve(uint32_t *, uint32_t); 861 int igb_check_acc_handle(ddi_acc_handle_t); 862 int igb_check_dma_handle(ddi_dma_handle_t); 863 void igb_fm_ereport(igb_t *, char *); 864 void igb_set_fma_flags(int); 865 866 /* 867 * Function prototypes in igb_gld.c 868 */ 869 int igb_m_start(void *); 870 void igb_m_stop(void *); 871 int igb_m_promisc(void *, boolean_t); 872 int igb_m_multicst(void *, boolean_t, const uint8_t *); 873 int igb_m_unicst(void *, const uint8_t *); 874 int igb_m_stat(void *, uint_t, uint64_t *); 875 void igb_m_resources(void *); 876 void igb_m_ioctl(void *, queue_t *, mblk_t *); 877 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 878 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 879 mac_ring_info_t *, mac_ring_handle_t); 880 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 881 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 882 void igb_m_propinfo(void *, const char *, mac_prop_id_t, 883 mac_prop_info_handle_t); 884 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 885 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 886 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 887 boolean_t igb_param_locked(mac_prop_id_t); 888 void igb_fill_group(void *arg, mac_ring_type_t, const int, 889 mac_group_info_t *, mac_group_handle_t); 890 int igb_rx_ring_intr_enable(mac_intr_handle_t); 891 int igb_rx_ring_intr_disable(mac_intr_handle_t); 892 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 893 894 /* 895 * Function prototypes in igb_rx.c 896 */ 897 mblk_t *igb_rx(igb_rx_ring_t *, int); 898 void igb_rx_recycle(caddr_t arg); 899 900 /* 901 * Function prototypes in igb_tx.c 902 */ 903 void igb_free_tcb(tx_control_block_t *); 904 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 905 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 906 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 907 908 /* 909 * Function prototypes in igb_stat.c 910 */ 911 int igb_init_stats(igb_t *); 912 913 mblk_t *igb_rx_ring_poll(void *, int); 914 mblk_t *igb_tx_ring_send(void *, mblk_t *); 915 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 916 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 917 918 /* 919 * Function prootypes in igb_sesnor.c 920 */ 921 void igb_init_sensors(igb_t *); 922 void igb_fini_sensors(igb_t *); 923 924 #ifdef __cplusplus 925 } 926 #endif 927 928 #endif /* _IGB_SW_H */ 929