xref: /illumos-gate/usr/src/uts/common/io/igb/igb_sw.h (revision 42b53e0fbc5c05289c3d334bb864b784fafe5ce4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24  */
25 
26 /*
27  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28  * Copyright 2014 Pluribus Networks Inc.
29  * Copyright (c) 2017, Joyent, Inc.
30  * Copyright 2020 Oxide Computer Company
31  */
32 
33 #ifndef	_IGB_SW_H
34 #define	_IGB_SW_H
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #include <sys/types.h>
41 #include <sys/conf.h>
42 #include <sys/debug.h>
43 #include <sys/stropts.h>
44 #include <sys/stream.h>
45 #include <sys/strsun.h>
46 #include <sys/strlog.h>
47 #include <sys/kmem.h>
48 #include <sys/stat.h>
49 #include <sys/kstat.h>
50 #include <sys/modctl.h>
51 #include <sys/errno.h>
52 #include <sys/dlpi.h>
53 #include <sys/mac_provider.h>
54 #include <sys/mac_ether.h>
55 #include <sys/vlan.h>
56 #include <sys/ddi.h>
57 #include <sys/sunddi.h>
58 #include <sys/pci.h>
59 #include <sys/pcie.h>
60 #include <sys/sdt.h>
61 #include <sys/ethernet.h>
62 #include <sys/pattr.h>
63 #include <sys/strsubr.h>
64 #include <sys/netlb.h>
65 #include <sys/random.h>
66 #include <inet/common.h>
67 #include <inet/tcp.h>
68 #include <inet/ip.h>
69 #include <inet/mi.h>
70 #include <inet/nd.h>
71 #include <sys/ddifm.h>
72 #include <sys/fm/protocol.h>
73 #include <sys/fm/util.h>
74 #include <sys/fm/io/ddi.h>
75 #include <sys/ddi_ufm.h>
76 #include "e1000_api.h"
77 #include "e1000_82575.h"
78 #include "e1000_illumos.h"
79 
80 
81 #define	MODULE_NAME			"igb"	/* module name */
82 
83 #define	IGB_SUCCESS			DDI_SUCCESS
84 #define	IGB_FAILURE			DDI_FAILURE
85 
86 #define	IGB_UNKNOWN			0x00
87 #define	IGB_INITIALIZED			0x01
88 #define	IGB_STARTED			0x02
89 #define	IGB_SUSPENDED			0x04
90 #define	IGB_STALL			0x08
91 #define	IGB_ERROR			0x80
92 
93 #define	IGB_RX_STOPPED			0x1
94 
95 #define	IGB_INTR_NONE			0
96 #define	IGB_INTR_MSIX			1
97 #define	IGB_INTR_MSI			2
98 #define	IGB_INTR_LEGACY			3
99 
100 #define	IGB_ADAPTER_REGSET		1	/* mapping adapter registers */
101 #define	IGB_ADAPTER_MSIXTAB		4	/* mapping msi-x table */
102 
103 #define	IGB_NO_POLL			-1
104 #define	IGB_NO_FREE_SLOT		-1
105 
106 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
107 #define	MCAST_ALLOC_COUNT		256
108 #define	MAX_COOKIE			18
109 #define	MIN_NUM_TX_DESC			2
110 
111 /*
112  * Number of settings for interrupt throttle rate (ITR).  There is one of
113  * these per msi-x vector and it needs to be the maximum of all silicon
114  * types supported by this driver.
115  */
116 #define	MAX_NUM_EITR			25
117 
118 /*
119  * Maximum values for user configurable parameters
120  */
121 #define	MAX_TX_RING_SIZE		4096
122 #define	MAX_RX_RING_SIZE		4096
123 #define	MAX_RX_GROUP_NUM		4
124 
125 #define	MAX_MTU				9000
126 #define	MAX_RX_LIMIT_PER_INTR		4096
127 
128 #define	MAX_RX_COPY_THRESHOLD		9216
129 #define	MAX_TX_COPY_THRESHOLD		9216
130 #define	MAX_TX_RECYCLE_THRESHOLD	DEFAULT_TX_RING_SIZE
131 #define	MAX_TX_OVERLOAD_THRESHOLD	DEFAULT_TX_RING_SIZE
132 #define	MAX_TX_RESCHED_THRESHOLD	DEFAULT_TX_RING_SIZE
133 #define	MAX_MCAST_NUM			8192
134 
135 /*
136  * Minimum values for user configurable parameters
137  */
138 #define	MIN_TX_RING_SIZE		64
139 #define	MIN_RX_RING_SIZE		64
140 #define	MIN_RX_GROUP_NUM		1
141 
142 #define	MIN_MTU				ETHERMIN
143 #define	MIN_RX_LIMIT_PER_INTR		16
144 
145 #define	MIN_RX_COPY_THRESHOLD		0
146 #define	MIN_TX_COPY_THRESHOLD		0
147 #define	MIN_TX_RECYCLE_THRESHOLD	MIN_NUM_TX_DESC
148 #define	MIN_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
149 #define	MIN_TX_RESCHED_THRESHOLD	MIN_NUM_TX_DESC
150 #define	MIN_MCAST_NUM			8
151 
152 /*
153  * Default values for user configurable parameters
154  */
155 #define	DEFAULT_TX_RING_SIZE		512
156 #define	DEFAULT_RX_RING_SIZE		512
157 #define	DEFAULT_RX_GROUP_NUM		1
158 
159 #define	DEFAULT_MTU			ETHERMTU
160 #define	DEFAULT_RX_LIMIT_PER_INTR	256
161 
162 #define	DEFAULT_RX_COPY_THRESHOLD	128
163 #define	DEFAULT_TX_COPY_THRESHOLD	512
164 #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
165 #define	DEFAULT_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
166 #define	DEFAULT_TX_RESCHED_THRESHOLD	128
167 #define	DEFAULT_TX_RESCHED_THRESHOLD_LOW	32
168 #define	DEFAULT_MCAST_NUM		4096
169 
170 #define	IGB_LSO_MAXLEN			65535
171 
172 #define	TX_DRAIN_TIME			200
173 #define	RX_DRAIN_TIME			200
174 
175 #define	STALL_WATCHDOG_TIMEOUT		8	/* 8 seconds */
176 
177 /*
178  * Defined for IP header alignment.
179  */
180 #define	IPHDR_ALIGN_ROOM		2
181 
182 /*
183  * Bit flags for attach_progress
184  */
185 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
186 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
187 #define	ATTACH_PROGRESS_PROPS		0x0004	/* Properties initialized */
188 #define	ATTACH_PROGRESS_ALLOC_INTR	0x0008	/* Interrupts allocated */
189 #define	ATTACH_PROGRESS_ALLOC_RINGS	0x0010	/* Rings allocated */
190 #define	ATTACH_PROGRESS_ADD_INTR	0x0020	/* Intr handlers added */
191 #define	ATTACH_PROGRESS_LOCKS		0x0040	/* Locks initialized */
192 #define	ATTACH_PROGRESS_INIT_ADAPTER	0x0080	/* Adapter initialized */
193 #define	ATTACH_PROGRESS_STATS		0x0200	/* Kstats created */
194 #define	ATTACH_PROGRESS_MAC		0x0800	/* MAC registered */
195 #define	ATTACH_PROGRESS_ENABLE_INTR	0x1000	/* DDI interrupts enabled */
196 #define	ATTACH_PROGRESS_FMINIT		0x2000	/* FMA initialized */
197 #define	ATTACH_PROGRESS_UFM		0x4000	/* UFM enabled */
198 
199 #define	PROP_ADV_AUTONEG_CAP		"adv_autoneg_cap"
200 #define	PROP_ADV_1000FDX_CAP		"adv_1000fdx_cap"
201 #define	PROP_ADV_1000HDX_CAP		"adv_1000hdx_cap"
202 #define	PROP_ADV_100FDX_CAP		"adv_100fdx_cap"
203 #define	PROP_ADV_100HDX_CAP		"adv_100hdx_cap"
204 #define	PROP_ADV_10FDX_CAP		"adv_10fdx_cap"
205 #define	PROP_ADV_10HDX_CAP		"adv_10hdx_cap"
206 #define	PROP_DEFAULT_MTU		"default_mtu"
207 #define	PROP_FLOW_CONTROL		"flow_control"
208 #define	PROP_TX_RING_SIZE		"tx_ring_size"
209 #define	PROP_RX_RING_SIZE		"rx_ring_size"
210 #define	PROP_MR_ENABLE			"mr_enable"
211 #define	PROP_RX_GROUP_NUM		"rx_group_number"
212 
213 #define	PROP_INTR_FORCE			"intr_force"
214 #define	PROP_TX_HCKSUM_ENABLE		"tx_hcksum_enable"
215 #define	PROP_RX_HCKSUM_ENABLE		"rx_hcksum_enable"
216 #define	PROP_LSO_ENABLE			"lso_enable"
217 #define	PROP_TX_HEAD_WB_ENABLE		"tx_head_wb_enable"
218 #define	PROP_TX_COPY_THRESHOLD		"tx_copy_threshold"
219 #define	PROP_TX_RECYCLE_THRESHOLD	"tx_recycle_threshold"
220 #define	PROP_TX_OVERLOAD_THRESHOLD	"tx_overload_threshold"
221 #define	PROP_TX_RESCHED_THRESHOLD	"tx_resched_threshold"
222 #define	PROP_RX_COPY_THRESHOLD		"rx_copy_threshold"
223 #define	PROP_RX_LIMIT_PER_INTR		"rx_limit_per_intr"
224 #define	PROP_INTR_THROTTLING		"intr_throttling"
225 #define	PROP_MCAST_MAX_NUM		"mcast_max_num"
226 
227 #define	IGB_LB_NONE			0
228 #define	IGB_LB_EXTERNAL			1
229 #define	IGB_LB_INTERNAL_PHY		3
230 #define	IGB_LB_INTERNAL_SERDES		4
231 
232 enum ioc_reply {
233 	IOC_INVAL = -1,	/* bad, NAK with EINVAL */
234 	IOC_DONE,	/* OK, reply sent */
235 	IOC_ACK,	/* OK, just send ACK */
236 	IOC_REPLY	/* OK, just send reply */
237 };
238 
239 /*
240  * For s/w context extraction from a tx frame
241  */
242 #define	TX_CXT_SUCCESS		0
243 #define	TX_CXT_E_LSO_CSUM	(-1)
244 #define	TX_CXT_E_ETHER_TYPE	(-2)
245 
246 #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area)->dma_handle, \
247 				    0, 0, (flag)))
248 
249 /*
250  * Defined for ring index operations
251  * ASSERT(index < limit)
252  * ASSERT(step < limit)
253  * ASSERT(index1 < limit)
254  * ASSERT(index2 < limit)
255  */
256 #define	NEXT_INDEX(index, step, limit)	(((index) + (step)) < (limit) ? \
257 	(index) + (step) : (index) + (step) - (limit))
258 #define	PREV_INDEX(index, step, limit)	((index) >= (step) ? \
259 	(index) - (step) : (index) + (limit) - (step))
260 #define	OFFSET(index1, index2, limit)	((index1) <= (index2) ? \
261 	(index2) - (index1) : (index2) + (limit) - (index1))
262 
263 #define	LINK_LIST_INIT(_LH)	\
264 	(_LH)->head = (_LH)->tail = NULL
265 
266 #define	LIST_GET_HEAD(_LH)	((single_link_t *)((_LH)->head))
267 
268 #define	LIST_POP_HEAD(_LH)	\
269 	(single_link_t *)(_LH)->head; \
270 	{ \
271 		if ((_LH)->head != NULL) { \
272 			(_LH)->head = (_LH)->head->link; \
273 			if ((_LH)->head == NULL) \
274 				(_LH)->tail = NULL; \
275 		} \
276 	}
277 
278 #define	LIST_GET_TAIL(_LH)	((single_link_t *)((_LH)->tail))
279 
280 #define	LIST_PUSH_TAIL(_LH, _E)	\
281 	if ((_LH)->tail != NULL) { \
282 		(_LH)->tail->link = (single_link_t *)(_E); \
283 		(_LH)->tail = (single_link_t *)(_E); \
284 	} else { \
285 		(_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
286 	} \
287 	(_E)->link = NULL;
288 
289 #define	LIST_GET_NEXT(_LH, _E)		\
290 	(((_LH)->tail == (single_link_t *)(_E)) ? \
291 	NULL : ((single_link_t *)(_E))->link)
292 
293 
294 typedef struct single_link {
295 	struct single_link	*link;
296 } single_link_t;
297 
298 typedef struct link_list {
299 	single_link_t		*head;
300 	single_link_t		*tail;
301 } link_list_t;
302 
303 /*
304  * Property lookups
305  */
306 #define	IGB_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
307 				    DDI_PROP_DONTPASS, (n))
308 #define	IGB_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
309 				    DDI_PROP_DONTPASS, (n), -1)
310 
311 
312 /* capability/feature flags */
313 #define	IGB_FLAG_HAS_DCA	(1 << 0) /* has Direct Cache Access */
314 #define	IGB_FLAG_VMDQ_POOL	(1 << 1) /* has vmdq capability */
315 #define	IGB_FLAG_NEED_CTX_IDX	(1 << 2) /* context descriptor needs index */
316 
317 /* function pointer for nic-specific functions */
318 typedef void (*igb_nic_func_t)(struct igb *);
319 
320 /* adapter-specific info for each supported device type */
321 typedef struct adapter_info {
322 	/* limits */
323 	uint32_t	max_rx_que_num;	/* maximum number of rx queues */
324 	uint32_t	min_rx_que_num;	/* minimum number of rx queues */
325 	uint32_t	def_rx_que_num;	/* default number of rx queues */
326 	uint32_t	max_tx_que_num;	/* maximum number of tx queues */
327 	uint32_t	min_tx_que_num;	/* minimum number of tx queues */
328 	uint32_t	def_tx_que_num;	/* default number of tx queues */
329 	uint32_t	max_intr_throttle; /* maximum interrupt throttle */
330 	uint32_t	min_intr_throttle; /* minimum interrupt throttle */
331 	uint32_t	def_intr_throttle; /* default interrupt throttle */
332 	/* function pointers */
333 	igb_nic_func_t	enable_intr;	/* enable adapter interrupts */
334 	igb_nic_func_t	setup_msix;	/* set up msi-x vectors */
335 	/* capabilities */
336 	uint32_t	flags;		/* capability flags */
337 	uint32_t	rxdctl_mask;	/* mask for RXDCTL register */
338 } adapter_info_t;
339 
340 typedef union igb_ether_addr {
341 	struct {
342 		uint32_t	high;
343 		uint32_t	low;
344 	} reg;
345 	struct {
346 		uint8_t		set;
347 		uint8_t		group_index;
348 		uint8_t		addr[ETHERADDRL];
349 	} mac;
350 } igb_ether_addr_t;
351 
352 typedef enum {
353 	USE_NONE,
354 	USE_COPY,
355 	USE_DMA
356 } tx_type_t;
357 
358 typedef struct tx_context {
359 	uint32_t		hcksum_flags;
360 	uint32_t		ip_hdr_len;
361 	uint32_t		mac_hdr_len;
362 	uint32_t		l3_proto;
363 	uint32_t		l4_proto;
364 	uint32_t		mss;
365 	uint32_t		l4_hdr_len;
366 	boolean_t		lso_flag;
367 } tx_context_t;
368 
369 /* Hold address/length of each DMA segment */
370 typedef struct sw_desc {
371 	uint64_t		address;
372 	size_t			length;
373 } sw_desc_t;
374 
375 /* Handles and addresses of DMA buffer */
376 typedef struct dma_buffer {
377 	caddr_t			address;	/* Virtual address */
378 	uint64_t		dma_address;	/* DMA (Hardware) address */
379 	ddi_acc_handle_t	acc_handle;	/* Data access handle */
380 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
381 	size_t			size;		/* Buffer size */
382 	size_t			len;		/* Data length in the buffer */
383 } dma_buffer_t;
384 
385 /*
386  * Tx Control Block
387  */
388 typedef struct tx_control_block {
389 	single_link_t		link;
390 	uint32_t		last_index;
391 	uint32_t		frag_num;
392 	uint32_t		desc_num;
393 	mblk_t			*mp;
394 	tx_type_t		tx_type;
395 	ddi_dma_handle_t	tx_dma_handle;
396 	dma_buffer_t		tx_buf;
397 	sw_desc_t		desc[MAX_COOKIE];
398 } tx_control_block_t;
399 
400 /*
401  * RX Control Block
402  */
403 typedef struct rx_control_block {
404 	mblk_t			*mp;
405 	uint32_t		ref_cnt;
406 	dma_buffer_t		rx_buf;
407 	frtn_t			free_rtn;
408 	struct igb_rx_data	*rx_data;
409 } rx_control_block_t;
410 
411 /*
412  * Software Data Structure for Tx Ring
413  */
414 typedef struct igb_tx_ring {
415 	uint32_t		index;	/* Ring index */
416 	uint32_t		intr_vector;	/* Interrupt vector index */
417 
418 	/*
419 	 * Mutexes
420 	 */
421 	kmutex_t		tx_lock;
422 	kmutex_t		recycle_lock;
423 	kmutex_t		tcb_head_lock;
424 	kmutex_t		tcb_tail_lock;
425 
426 	/*
427 	 * Tx descriptor ring definitions
428 	 */
429 	dma_buffer_t		tbd_area;
430 	union e1000_adv_tx_desc	*tbd_ring;
431 	uint32_t		tbd_head; /* Index of next tbd to recycle */
432 	uint32_t		tbd_tail; /* Index of next tbd to transmit */
433 	uint32_t		tbd_free; /* Number of free tbd */
434 
435 	/*
436 	 * Tx control block list definitions
437 	 */
438 	tx_control_block_t	*tcb_area;
439 	tx_control_block_t	**work_list;
440 	tx_control_block_t	**free_list;
441 	uint32_t		tcb_head; /* Head index of free list */
442 	uint32_t		tcb_tail; /* Tail index of free list */
443 	uint32_t		tcb_free; /* Number of free tcb in free list */
444 
445 	uint32_t		*tbd_head_wb; /* Head write-back */
446 	uint32_t		(*tx_recycle)(struct igb_tx_ring *);
447 
448 	/*
449 	 * s/w context structure for TCP/UDP checksum offload and LSO.
450 	 */
451 	tx_context_t		tx_context;
452 
453 	/*
454 	 * Tx ring settings and status
455 	 */
456 	uint32_t		ring_size; /* Tx descriptor ring size */
457 	uint32_t		free_list_size;	/* Tx free list size */
458 
459 	boolean_t		reschedule;
460 	uint32_t		recycle_fail;
461 	uint32_t		stall_watchdog;
462 
463 	/*
464 	 * Per-ring statistics
465 	 */
466 	uint64_t		tx_pkts;	/* Packets Transmitted Count */
467 	uint64_t		tx_bytes;	/* Bytes Transmitted Count */
468 
469 #ifdef IGB_DEBUG
470 	/*
471 	 * Debug statistics
472 	 */
473 	uint32_t		stat_overload;
474 	uint32_t		stat_fail_no_tbd;
475 	uint32_t		stat_fail_no_tcb;
476 	uint32_t		stat_fail_dma_bind;
477 	uint32_t		stat_reschedule;
478 	uint32_t		stat_pkt_cnt;
479 #endif
480 
481 	/*
482 	 * Pointer to the igb struct
483 	 */
484 	struct igb		*igb;
485 	mac_ring_handle_t	ring_handle;	/* call back ring handle */
486 } igb_tx_ring_t;
487 
488 /*
489  * Software Receive Ring
490  */
491 typedef struct igb_rx_data {
492 	kmutex_t		recycle_lock;	/* Recycle lock, for rcb_tail */
493 
494 	/*
495 	 * Rx descriptor ring definitions
496 	 */
497 	dma_buffer_t		rbd_area;	/* DMA buffer of rx desc ring */
498 	union e1000_adv_rx_desc	*rbd_ring;	/* Rx desc ring */
499 	uint32_t		rbd_next;	/* Index of next rx desc */
500 
501 	/*
502 	 * Rx control block list definitions
503 	 */
504 	rx_control_block_t	*rcb_area;
505 	rx_control_block_t	**work_list;	/* Work list of rcbs */
506 	rx_control_block_t	**free_list;	/* Free list of rcbs */
507 	uint32_t		rcb_head;	/* Index of next free rcb */
508 	uint32_t		rcb_tail;	/* Index to put recycled rcb */
509 	uint32_t		rcb_free;	/* Number of free rcbs */
510 
511 	/*
512 	 * Rx sw ring settings and status
513 	 */
514 	uint32_t		ring_size;	/* Rx descriptor ring size */
515 	uint32_t		free_list_size;	/* Rx free list size */
516 
517 	uint32_t		rcb_pending;
518 	uint32_t		flag;
519 
520 	struct igb_rx_ring	*rx_ring;	/* Pointer to rx ring */
521 } igb_rx_data_t;
522 
523 /*
524  * Software Data Structure for Rx Ring
525  */
526 typedef struct igb_rx_ring {
527 	uint32_t		index;		/* Ring index */
528 	uint32_t		intr_vector;	/* Interrupt vector index */
529 
530 	igb_rx_data_t		*rx_data;	/* Rx software ring */
531 
532 	kmutex_t		rx_lock;	/* Rx access lock */
533 
534 	/*
535 	 * Per-ring statistics
536 	 */
537 	uint64_t		rx_pkts;	/* Packets Received Count */
538 	uint64_t		rx_bytes;	/* Bytes Received Count */
539 
540 #ifdef IGB_DEBUG
541 	/*
542 	 * Debug statistics
543 	 */
544 	uint32_t		stat_frame_error;
545 	uint32_t		stat_cksum_error;
546 	uint32_t		stat_exceed_pkt;
547 	uint32_t		stat_pkt_cnt;
548 #endif
549 
550 	struct igb		*igb;		/* Pointer to igb struct */
551 	mac_ring_handle_t	ring_handle;	/* call back ring handle */
552 	uint32_t		group_index;	/* group index */
553 	uint64_t		ring_gen_num;
554 } igb_rx_ring_t;
555 
556 /*
557  * Software Receive Ring Group
558  */
559 typedef struct igb_rx_group {
560 	uint32_t		index;		/* Group index */
561 	mac_group_handle_t	group_handle;   /* call back group handle */
562 	struct igb		*igb;		/* Pointer to igb struct */
563 } igb_rx_group_t;
564 
565 typedef enum {
566 	IGB_ETS_INDEX_INTERNAL		= 0,
567 	IGB_ETS_INDEX_EXTERNAL_1	= 1,
568 	IGB_ETS_INDEX_EXTERNAL_2	= 2,
569 	IGB_ETS_INDEX_EXTERNAL_3	= 3
570 } igb_ets_index_t;
571 
572 typedef enum {
573 	IGB_ETS_LOC_NA		= 0,
574 	IGB_ETS_LOC_HOT_SPOT	= 2,
575 	IGB_ETS_LOC_PCIE	= 3,
576 	IGB_ETS_LOC_BULKHEAD	= 4,
577 	IGB_ETS_LOC_BOARD	= 5,
578 	IGB_ETS_LOC_INLET	= 7
579 } igb_ets_loc_t;
580 
581 /*
582  * Sensor data
583  */
584 typedef struct igb_ets {
585 	igb_ets_index_t	iet_index;
586 	igb_ets_loc_t	iet_loc;
587 	uint8_t		iet_thresh;
588 	id_t		iet_ksensor;
589 } igb_ets_t;
590 
591 /*
592  * There are only four words defined for sensors.
593  */
594 #define	IGB_ETS_MAX	4
595 
596 typedef struct igb_sensors {
597 	boolean_t isn_valid;
598 	id_t isn_reg_ksensor;
599 	uint_t isn_nents;
600 	igb_ets_t isn_ets[IGB_ETS_MAX];
601 } igb_sensors_t;
602 
603 typedef struct igb {
604 	int			instance;
605 	mac_handle_t		mac_hdl;
606 	dev_info_t		*dip;
607 	struct e1000_hw		hw;
608 	struct igb_osdep	osdep;
609 
610 	adapter_info_t		*capab;		/* adapter capabilities */
611 
612 	uint32_t		igb_state;
613 	link_state_t		link_state;
614 	uint32_t		link_speed;
615 	uint32_t		link_duplex;
616 	boolean_t		link_complete;
617 	timeout_id_t		link_tid;
618 
619 	uint32_t		reset_count;
620 	uint32_t		attach_progress;
621 	uint32_t		loopback_mode;
622 	uint32_t		default_mtu;
623 	uint32_t		max_frame_size;
624 	uint32_t		dout_sync;
625 
626 	uint32_t		rcb_pending;
627 
628 	uint32_t		mr_enable;	/* Enable multiple rings */
629 	uint32_t		vmdq_mode;	/* Mode of VMDq */
630 
631 	/*
632 	 * Receive Rings and Groups
633 	 */
634 	igb_rx_ring_t		*rx_rings;	/* Array of rx rings */
635 	uint32_t		num_rx_rings;	/* Number of rx rings in use */
636 	uint32_t		rx_ring_size;	/* Rx descriptor ring size */
637 	uint32_t		rx_buf_size;	/* Rx buffer size */
638 	igb_rx_group_t		*rx_groups;	/* Array of rx groups */
639 	uint32_t		num_rx_groups;	/* Number of rx groups in use */
640 
641 	/*
642 	 * Transmit Rings
643 	 */
644 	igb_tx_ring_t		*tx_rings;	/* Array of tx rings */
645 	uint32_t		num_tx_rings;	/* Number of tx rings in use */
646 	uint32_t		tx_ring_size;	/* Tx descriptor ring size */
647 	uint32_t		tx_buf_size;	/* Tx buffer size */
648 
649 	boolean_t		tx_ring_init;
650 	boolean_t		tx_head_wb_enable; /* Tx head wrtie-back */
651 	boolean_t		tx_hcksum_enable; /* Tx h/w cksum offload */
652 	boolean_t		lso_enable;	/* Large Segment Offload */
653 	uint32_t		tx_copy_thresh;	/* Tx copy threshold */
654 	uint32_t		tx_recycle_thresh; /* Tx recycle threshold */
655 	uint32_t		tx_overload_thresh; /* Tx overload threshold */
656 	uint32_t		tx_resched_thresh; /* Tx reschedule threshold */
657 	boolean_t		rx_hcksum_enable; /* Rx h/w cksum offload */
658 	uint32_t		rx_copy_thresh; /* Rx copy threshold */
659 	uint32_t		rx_limit_per_intr; /* Rx pkts per interrupt */
660 
661 	uint32_t		intr_throttling[MAX_NUM_EITR];
662 	uint32_t		intr_force;
663 
664 	int			intr_type;
665 	int			intr_cnt;
666 	int			intr_cap;
667 	size_t			intr_size;
668 	uint_t			intr_pri;
669 	ddi_intr_handle_t	*htable;
670 	uint32_t		eims_mask;
671 	uint32_t		ims_mask;
672 
673 	kmutex_t		gen_lock; /* General lock for device access */
674 	kmutex_t		watchdog_lock;
675 	kmutex_t		link_lock;
676 	kmutex_t		rx_pending_lock;
677 
678 	boolean_t		watchdog_enable;
679 	boolean_t		watchdog_start;
680 	timeout_id_t		watchdog_tid;
681 
682 	boolean_t		unicst_init;
683 	uint32_t		unicst_avail;
684 	uint32_t		unicst_total;
685 	igb_ether_addr_t	unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
686 	uint32_t		mcast_count;
687 	uint32_t		mcast_alloc_count;
688 	uint32_t		mcast_max_num;
689 	struct ether_addr	*mcast_table;
690 
691 	/*
692 	 * LED related functions
693 	 */
694 	boolean_t		igb_led_setup;
695 
696 	/*
697 	 * Kstat definitions
698 	 */
699 	kstat_t			*igb_ks;
700 
701 	/*
702 	 * Backing store for MAC stats.  These are reported via GLDv3, instead
703 	 * of via our private kstat structure.
704 	 */
705 	uint64_t		stat_tor;	/* rbytes */
706 	uint64_t		stat_tpr;	/* rpackets */
707 	uint64_t		stat_tot;	/* obytes */
708 	uint64_t		stat_tpt;	/* opackets */
709 	uint64_t		stat_colc;	/* collisions */
710 	uint64_t		stat_mcc;	/* multi colls */
711 	uint64_t		stat_scc;	/* single colls */
712 	uint64_t		stat_ecol;	/* excessive colls */
713 	uint64_t		stat_latecol;	/* late colls */
714 	uint64_t		stat_bptc;	/* xmit bcast */
715 	uint64_t		stat_mptc;	/* xmit bcast */
716 	uint64_t		stat_bprc;	/* recv bcast */
717 	uint64_t		stat_mprc;	/* recv mcast */
718 	uint64_t		stat_rnbc;	/* recv nobuf */
719 	uint64_t		stat_roc;	/* recv toolong */
720 	uint64_t		stat_sec;	/* sqe errors */
721 	uint64_t		stat_dc;	/* defer */
722 	uint64_t		stat_algnerrc;	/* align errors */
723 	uint64_t		stat_crcerrs;	/* crc errors */
724 	uint64_t		stat_cexterr;	/* carrier extension errors */
725 	uint64_t		stat_ruc;	/* recv tooshort */
726 	uint64_t		stat_rjc;	/* recv jabber */
727 	uint64_t		stat_rxerrc;	/* recv errors */
728 
729 	uint32_t		param_en_1000fdx_cap:1,
730 				param_en_1000hdx_cap:1,
731 				param_en_100t4_cap:1,
732 				param_en_100fdx_cap:1,
733 				param_en_100hdx_cap:1,
734 				param_en_10fdx_cap:1,
735 				param_en_10hdx_cap:1,
736 				param_1000fdx_cap:1,
737 				param_1000hdx_cap:1,
738 				param_100t4_cap:1,
739 				param_100fdx_cap:1,
740 				param_100hdx_cap:1,
741 				param_10fdx_cap:1,
742 				param_10hdx_cap:1,
743 				param_autoneg_cap:1,
744 				param_pause_cap:1,
745 				param_asym_pause_cap:1,
746 				param_rem_fault:1,
747 				param_adv_1000fdx_cap:1,
748 				param_adv_1000hdx_cap:1,
749 				param_adv_100t4_cap:1,
750 				param_adv_100fdx_cap:1,
751 				param_adv_100hdx_cap:1,
752 				param_adv_10fdx_cap:1,
753 				param_adv_10hdx_cap:1,
754 				param_adv_autoneg_cap:1,
755 				param_adv_pause_cap:1,
756 				param_adv_asym_pause_cap:1,
757 				param_adv_rem_fault:1,
758 				param_lp_1000fdx_cap:1,
759 				param_lp_1000hdx_cap:1,
760 				param_lp_100t4_cap:1;
761 
762 	uint32_t		param_lp_100fdx_cap:1,
763 				param_lp_100hdx_cap:1,
764 				param_lp_10fdx_cap:1,
765 				param_lp_10hdx_cap:1,
766 				param_lp_autoneg_cap:1,
767 				param_lp_pause_cap:1,
768 				param_lp_asym_pause_cap:1,
769 				param_lp_rem_fault:1,
770 				param_pad_to_32:24;
771 
772 	/*
773 	 * FMA capabilities
774 	 */
775 	int			fm_capabilities;
776 
777 	ulong_t			page_size;
778 	ddi_ufm_handle_t	*igb_ufmh;
779 	igb_sensors_t		igb_sensors;
780 } igb_t;
781 
782 typedef struct igb_stat {
783 
784 	kstat_named_t reset_count;	/* Reset Count */
785 	kstat_named_t dout_sync;	/* DMA out of sync */
786 #ifdef IGB_DEBUG
787 	kstat_named_t rx_frame_error;	/* Rx Error in Packet */
788 	kstat_named_t rx_cksum_error;	/* Rx Checksum Error */
789 	kstat_named_t rx_exceed_pkt;	/* Rx Exceed Max Pkt Count */
790 
791 	kstat_named_t tx_overload;	/* Tx Desc Ring Overload */
792 	kstat_named_t tx_fail_no_tcb;	/* Tx Fail Freelist Empty */
793 	kstat_named_t tx_fail_no_tbd;	/* Tx Fail Desc Ring Empty */
794 	kstat_named_t tx_fail_dma_bind;	/* Tx Fail DMA bind */
795 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
796 
797 	kstat_named_t gprc;	/* Good Packets Received Count */
798 	kstat_named_t gptc;	/* Good Packets Xmitted Count */
799 	kstat_named_t gor;	/* Good Octets Received Count */
800 	kstat_named_t got;	/* Good Octets Xmitd Count */
801 	kstat_named_t prc64;	/* Packets Received - 64b */
802 	kstat_named_t prc127;	/* Packets Received - 65-127b */
803 	kstat_named_t prc255;	/* Packets Received - 127-255b */
804 	kstat_named_t prc511;	/* Packets Received - 256-511b */
805 	kstat_named_t prc1023;	/* Packets Received - 511-1023b */
806 	kstat_named_t prc1522;	/* Packets Received - 1024-1522b */
807 	kstat_named_t ptc64;	/* Packets Xmitted (64b) */
808 	kstat_named_t ptc127;	/* Packets Xmitted (64-127b) */
809 	kstat_named_t ptc255;	/* Packets Xmitted (128-255b) */
810 	kstat_named_t ptc511;	/* Packets Xmitted (255-511b) */
811 	kstat_named_t ptc1023;	/* Packets Xmitted (512-1023b) */
812 	kstat_named_t ptc1522;	/* Packets Xmitted (1024-1522b */
813 #endif
814 	kstat_named_t symerrs;	/* Symbol Error Count */
815 	kstat_named_t mpc;	/* Missed Packet Count */
816 	kstat_named_t rlec;	/* Receive Length Error Count */
817 	kstat_named_t xonrxc;	/* XON Received Count */
818 	kstat_named_t xontxc;	/* XON Xmitted Count */
819 	kstat_named_t xoffrxc;	/* XOFF Received Count */
820 	kstat_named_t xofftxc;	/* Xoff Xmitted Count */
821 	kstat_named_t fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
822 	kstat_named_t rfc;	/* Receive Frag Count */
823 	kstat_named_t tncrs;	/* Transmit with no CRS */
824 	kstat_named_t tsctc;	/* TCP seg contexts xmit count */
825 	kstat_named_t tsctfc;	/* TCP seg contexts xmit fail count */
826 } igb_stat_t;
827 
828 /*
829  * Function prototypes in e1000_osdep.c
830  */
831 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
832 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *);
833 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
834 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *);
835 void e1000_rar_clear(struct e1000_hw *, uint32_t);
836 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t,
837     uint32_t, uint8_t);
838 
839 /*
840  * Function prototypes in igb_buf.c
841  */
842 int igb_alloc_dma(igb_t *);
843 void igb_free_dma(igb_t *);
844 void igb_free_dma_buffer(dma_buffer_t *);
845 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring);
846 void igb_free_rx_ring_data(igb_rx_data_t *rx_data);
847 
848 /*
849  * Function prototypes in igb_main.c
850  */
851 int igb_start(igb_t *, boolean_t);
852 void igb_stop(igb_t *, boolean_t);
853 int igb_setup_link(igb_t *, boolean_t);
854 int igb_unicst_find(igb_t *, const uint8_t *);
855 int igb_unicst_set(igb_t *, const uint8_t *, int);
856 int igb_multicst_add(igb_t *, const uint8_t *);
857 int igb_multicst_remove(igb_t *, const uint8_t *);
858 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *);
859 void igb_enable_watchdog_timer(igb_t *);
860 void igb_disable_watchdog_timer(igb_t *);
861 int igb_atomic_reserve(uint32_t *, uint32_t);
862 int igb_check_acc_handle(ddi_acc_handle_t);
863 int igb_check_dma_handle(ddi_dma_handle_t);
864 void igb_fm_ereport(igb_t *, char *);
865 void igb_set_fma_flags(int);
866 
867 /*
868  * Function prototypes in igb_gld.c
869  */
870 int igb_m_start(void *);
871 void igb_m_stop(void *);
872 int igb_m_promisc(void *, boolean_t);
873 int igb_m_multicst(void *, boolean_t, const uint8_t *);
874 int igb_m_unicst(void *, const uint8_t *);
875 int igb_m_stat(void *, uint_t, uint64_t *);
876 void igb_m_resources(void *);
877 void igb_m_ioctl(void *, queue_t *, mblk_t *);
878 boolean_t igb_m_getcapab(void *, mac_capab_t, void *);
879 void igb_fill_ring(void *, mac_ring_type_t, const int, const int,
880     mac_ring_info_t *, mac_ring_handle_t);
881 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
882 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
883 void igb_m_propinfo(void *, const char *, mac_prop_id_t,
884     mac_prop_info_handle_t);
885 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *);
886 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *);
887 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t);
888 boolean_t igb_param_locked(mac_prop_id_t);
889 void igb_fill_group(void *arg, mac_ring_type_t, const int,
890     mac_group_info_t *, mac_group_handle_t);
891 int igb_rx_ring_intr_enable(mac_intr_handle_t);
892 int igb_rx_ring_intr_disable(mac_intr_handle_t);
893 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *);
894 
895 /*
896  * Function prototypes in igb_rx.c
897  */
898 mblk_t *igb_rx(igb_rx_ring_t *, int);
899 void igb_rx_recycle(caddr_t arg);
900 
901 /*
902  * Function prototypes in igb_tx.c
903  */
904 void igb_free_tcb(tx_control_block_t *);
905 void igb_put_free_list(igb_tx_ring_t *, link_list_t *);
906 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *);
907 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *);
908 
909 /*
910  * Function prototypes in igb_stat.c
911  */
912 int igb_init_stats(igb_t *);
913 
914 mblk_t *igb_rx_ring_poll(void *, int);
915 mblk_t *igb_tx_ring_send(void *, mblk_t *);
916 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
917 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
918 
919 /*
920  * Function prootypes in igb_sesnor.c
921  */
922 void igb_init_sensors(igb_t *);
923 void igb_fini_sensors(igb_t *);
924 
925 #ifdef __cplusplus
926 }
927 #endif
928 
929 #endif /* _IGB_SW_H */
930