1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include "igb_api.h" 69 #include "igb_82575.h" 70 71 72 #define MODULE_NAME "igb" /* module name */ 73 74 #define IGB_SUCCESS DDI_SUCCESS 75 #define IGB_FAILURE DDI_FAILURE 76 77 #define IGB_UNKNOWN 0x00 78 #define IGB_INITIALIZED 0x01 79 #define IGB_STARTED 0x02 80 #define IGB_SUSPENDED 0x04 81 82 #define IGB_INTR_NONE 0 83 #define IGB_INTR_MSIX 1 84 #define IGB_INTR_MSI 2 85 #define IGB_INTR_LEGACY 3 86 87 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 88 #define MAX_NUM_MULTICAST_ADDRESSES 256 89 #define MAX_NUM_EITR 10 90 #define MAX_COOKIE 16 91 #define MIN_NUM_TX_DESC 2 92 93 /* 94 * Maximum values for user configurable parameters 95 */ 96 #define MAX_TX_QUEUE_NUM 4 97 #define MAX_RX_QUEUE_NUM 4 98 #define MAX_TX_RING_SIZE 4096 99 #define MAX_RX_RING_SIZE 4096 100 101 #define MAX_MTU 9000 102 #define MAX_RX_LIMIT_PER_INTR 4096 103 #define MAX_RX_INTR_DELAY 65535 104 #define MAX_RX_INTR_ABS_DELAY 65535 105 #define MAX_TX_INTR_DELAY 65535 106 #define MAX_TX_INTR_ABS_DELAY 65535 107 #define MAX_INTR_THROTTLING 65535 108 109 #define MAX_RX_COPY_THRESHOLD 9216 110 #define MAX_TX_COPY_THRESHOLD 9216 111 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 112 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 113 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 114 115 /* 116 * Minimum values for user configurable parameters 117 */ 118 #define MIN_TX_QUEUE_NUM 1 119 #define MIN_RX_QUEUE_NUM 1 120 #define MIN_TX_RING_SIZE 64 121 #define MIN_RX_RING_SIZE 64 122 123 #define MIN_MTU ETHERMIN 124 #define MIN_RX_LIMIT_PER_INTR 16 125 #define MIN_RX_INTR_DELAY 0 126 #define MIN_RX_INTR_ABS_DELAY 0 127 #define MIN_TX_INTR_DELAY 0 128 #define MIN_TX_INTR_ABS_DELAY 0 129 #define MIN_INTR_THROTTLING 0 130 #define MIN_RX_COPY_THRESHOLD 0 131 #define MIN_TX_COPY_THRESHOLD 0 132 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 133 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 134 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 135 136 /* 137 * Default values for user configurable parameters 138 */ 139 #define DEFAULT_TX_QUEUE_NUM 1 140 #define DEFAULT_RX_QUEUE_NUM 1 141 #define DEFAULT_TX_RING_SIZE 512 142 #define DEFAULT_RX_RING_SIZE 512 143 144 #define DEFAULT_MTU ETHERMTU 145 #define DEFAULT_RX_LIMIT_PER_INTR 256 146 #define DEFAULT_RX_INTR_DELAY 0 147 #define DEFAULT_RX_INTR_ABS_DELAY 0 148 #define DEFAULT_TX_INTR_DELAY 300 149 #define DEFAULT_TX_INTR_ABS_DELAY 0 150 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 151 #define DEFAULT_RX_COPY_THRESHOLD 128 152 #define DEFAULT_TX_COPY_THRESHOLD 512 153 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 154 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 155 #define DEFAULT_TX_RESCHED_THRESHOLD 128 156 157 #define TX_DRAIN_TIME 200 158 #define RX_DRAIN_TIME 200 159 160 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 161 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 162 163 /* 164 * Defined for IP header alignment. 165 */ 166 #define IPHDR_ALIGN_ROOM 2 167 168 /* 169 * Bit flags for attach_progress 170 */ 171 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 172 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 173 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 174 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 175 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 176 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 177 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 178 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 179 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 180 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 181 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 182 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 183 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 184 185 186 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 187 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 188 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 189 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 190 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 191 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 192 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 193 #define PROP_DEFAULT_MTU "default_mtu" 194 #define PROP_FLOW_CONTROL "flow_control" 195 #define PROP_TX_QUEUE_NUM "tx_queue_number" 196 #define PROP_TX_RING_SIZE "tx_ring_size" 197 #define PROP_RX_QUEUE_NUM "rx_queue_number" 198 #define PROP_RX_RING_SIZE "rx_ring_size" 199 200 #define PROP_INTR_FORCE "intr_force" 201 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 202 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 203 #define PROP_LSO_ENABLE "lso_enable" 204 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 205 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 206 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 207 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 208 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 209 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 210 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 211 #define PROP_INTR_THROTTLING "intr_throttling" 212 213 #define IGB_LB_NONE 0 214 #define IGB_LB_EXTERNAL 1 215 #define IGB_LB_INTERNAL_MAC 2 216 #define IGB_LB_INTERNAL_PHY 3 217 #define IGB_LB_INTERNAL_SERDES 4 218 219 /* 220 * Shorthand for the NDD parameters 221 */ 222 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 223 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 224 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 225 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 226 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 227 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 228 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 229 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 230 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 231 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 232 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 233 234 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 235 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 236 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 237 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 238 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 239 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 240 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 241 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 242 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 243 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 244 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 245 246 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 247 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 248 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 249 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 250 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 251 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 252 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 253 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 254 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 255 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 256 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 257 258 enum ioc_reply { 259 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 260 IOC_DONE, /* OK, reply sent */ 261 IOC_ACK, /* OK, just send ACK */ 262 IOC_REPLY /* OK, just send reply */ 263 }; 264 265 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 266 (uintptr_t)(mp)->b_rptr) 267 268 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 269 0, 0, (flag))) 270 271 /* 272 * Defined for ring index operations 273 * ASSERT(index < limit) 274 * ASSERT(step < limit) 275 * ASSERT(index1 < limit) 276 * ASSERT(index2 < limit) 277 */ 278 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 279 (index) + (step) : (index) + (step) - (limit)) 280 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 281 (index) - (step) : (index) + (limit) - (step)) 282 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 283 (index2) - (index1) : (index2) + (limit) - (index1)) 284 285 #define LINK_LIST_INIT(_LH) \ 286 (_LH)->head = (_LH)->tail = NULL 287 288 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 289 290 #define LIST_POP_HEAD(_LH) \ 291 (single_link_t *)(_LH)->head; \ 292 { \ 293 if ((_LH)->head != NULL) { \ 294 (_LH)->head = (_LH)->head->link; \ 295 if ((_LH)->head == NULL) \ 296 (_LH)->tail = NULL; \ 297 } \ 298 } 299 300 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 301 302 #define LIST_PUSH_TAIL(_LH, _E) \ 303 if ((_LH)->tail != NULL) { \ 304 (_LH)->tail->link = (single_link_t *)(_E); \ 305 (_LH)->tail = (single_link_t *)(_E); \ 306 } else { \ 307 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 308 } \ 309 (_E)->link = NULL; 310 311 #define LIST_GET_NEXT(_LH, _E) \ 312 (((_LH)->tail == (single_link_t *)(_E)) ? \ 313 NULL : ((single_link_t *)(_E))->link) 314 315 316 typedef struct single_link { 317 struct single_link *link; 318 } single_link_t; 319 320 typedef struct link_list { 321 single_link_t *head; 322 single_link_t *tail; 323 } link_list_t; 324 325 /* 326 * Property lookups 327 */ 328 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 329 DDI_PROP_DONTPASS, (n)) 330 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 331 DDI_PROP_DONTPASS, (n), -1) 332 333 334 /* 335 * Named Data (ND) Parameter Management Structure 336 */ 337 typedef struct { 338 struct igb *private; 339 uint32_t info; 340 uint32_t min; 341 uint32_t max; 342 uint32_t val; 343 char *name; 344 } nd_param_t; 345 346 /* 347 * NDD parameter indexes, divided into: 348 * 349 * read-only parameters describing the hardware's capabilities 350 * read-write parameters controlling the advertised capabilities 351 * read-only parameters describing the partner's capabilities 352 * read-write parameters controlling the force speed and duplex 353 * read-only parameters describing the link state 354 * read-only parameters describing the driver properties 355 * read-write parameters controlling the driver properties 356 */ 357 enum { 358 PARAM_AUTONEG_CAP, 359 PARAM_PAUSE_CAP, 360 PARAM_ASYM_PAUSE_CAP, 361 PARAM_1000FDX_CAP, 362 PARAM_1000HDX_CAP, 363 PARAM_100T4_CAP, 364 PARAM_100FDX_CAP, 365 PARAM_100HDX_CAP, 366 PARAM_10FDX_CAP, 367 PARAM_10HDX_CAP, 368 PARAM_REM_FAULT, 369 370 PARAM_ADV_AUTONEG_CAP, 371 PARAM_ADV_PAUSE_CAP, 372 PARAM_ADV_ASYM_PAUSE_CAP, 373 PARAM_ADV_1000FDX_CAP, 374 PARAM_ADV_1000HDX_CAP, 375 PARAM_ADV_100T4_CAP, 376 PARAM_ADV_100FDX_CAP, 377 PARAM_ADV_100HDX_CAP, 378 PARAM_ADV_10FDX_CAP, 379 PARAM_ADV_10HDX_CAP, 380 PARAM_ADV_REM_FAULT, 381 382 PARAM_LP_AUTONEG_CAP, 383 PARAM_LP_PAUSE_CAP, 384 PARAM_LP_ASYM_PAUSE_CAP, 385 PARAM_LP_1000FDX_CAP, 386 PARAM_LP_1000HDX_CAP, 387 PARAM_LP_100T4_CAP, 388 PARAM_LP_100FDX_CAP, 389 PARAM_LP_100HDX_CAP, 390 PARAM_LP_10FDX_CAP, 391 PARAM_LP_10HDX_CAP, 392 PARAM_LP_REM_FAULT, 393 394 PARAM_LINK_STATUS, 395 PARAM_LINK_SPEED, 396 PARAM_LINK_DUPLEX, 397 398 PARAM_COUNT 399 }; 400 401 typedef union igb_ether_addr { 402 struct { 403 uint32_t high; 404 uint32_t low; 405 } reg; 406 struct { 407 uint8_t set; 408 uint8_t redundant; 409 uint8_t addr[ETHERADDRL]; 410 } mac; 411 } igb_ether_addr_t; 412 413 typedef enum { 414 USE_NONE, 415 USE_COPY, 416 USE_DMA 417 } tx_type_t; 418 419 typedef enum { 420 RCB_FREE, 421 RCB_SENDUP 422 } rcb_state_t; 423 424 typedef struct hcksum_context { 425 uint32_t hcksum_flags; 426 uint32_t ip_hdr_len; 427 uint32_t mac_hdr_len; 428 uint32_t l4_proto; 429 } hcksum_context_t; 430 431 /* Hold address/length of each DMA segment */ 432 typedef struct sw_desc { 433 uint64_t address; 434 size_t length; 435 } sw_desc_t; 436 437 /* Handles and addresses of DMA buffer */ 438 typedef struct dma_buffer { 439 caddr_t address; /* Virtual address */ 440 uint64_t dma_address; /* DMA (Hardware) address */ 441 ddi_acc_handle_t acc_handle; /* Data access handle */ 442 ddi_dma_handle_t dma_handle; /* DMA handle */ 443 size_t size; /* Buffer size */ 444 size_t len; /* Data length in the buffer */ 445 } dma_buffer_t; 446 447 /* 448 * Tx Control Block 449 */ 450 typedef struct tx_control_block { 451 single_link_t link; 452 uint32_t frag_num; 453 uint32_t desc_num; 454 mblk_t *mp; 455 tx_type_t tx_type; 456 ddi_dma_handle_t tx_dma_handle; 457 dma_buffer_t tx_buf; 458 sw_desc_t desc[MAX_COOKIE]; 459 } tx_control_block_t; 460 461 /* 462 * RX Control Block 463 */ 464 typedef struct rx_control_block { 465 mblk_t *mp; 466 rcb_state_t state; 467 dma_buffer_t rx_buf; 468 frtn_t free_rtn; 469 struct igb_rx_ring *rx_ring; 470 } rx_control_block_t; 471 472 /* 473 * Software Data Structure for Tx Ring 474 */ 475 typedef struct igb_tx_ring { 476 uint32_t index; /* Ring index */ 477 478 /* 479 * Mutexes 480 */ 481 kmutex_t tx_lock; 482 kmutex_t recycle_lock; 483 kmutex_t tcb_head_lock; 484 kmutex_t tcb_tail_lock; 485 486 /* 487 * Tx descriptor ring definitions 488 */ 489 dma_buffer_t tbd_area; 490 union e1000_adv_tx_desc *tbd_ring; 491 uint32_t tbd_head; /* Index of next tbd to recycle */ 492 uint32_t tbd_tail; /* Index of next tbd to transmit */ 493 uint32_t tbd_free; /* Number of free tbd */ 494 495 /* 496 * Tx control block list definitions 497 */ 498 tx_control_block_t *tcb_area; 499 tx_control_block_t **work_list; 500 tx_control_block_t **free_list; 501 uint32_t tcb_head; /* Head index of free list */ 502 uint32_t tcb_tail; /* Tail index of free list */ 503 uint32_t tcb_free; /* Number of free tcb in free list */ 504 505 uint32_t *tbd_head_wb; /* Head write-back */ 506 uint32_t (*tx_recycle)(struct igb_tx_ring *); 507 508 /* 509 * TCP/UDP checksum offload 510 */ 511 hcksum_context_t hcksum_context; 512 513 /* 514 * Tx ring settings and status 515 */ 516 uint32_t ring_size; /* Tx descriptor ring size */ 517 uint32_t free_list_size; /* Tx free list size */ 518 uint32_t copy_thresh; 519 uint32_t recycle_thresh; 520 uint32_t overload_thresh; 521 uint32_t resched_thresh; 522 523 boolean_t reschedule; 524 uint32_t recycle_fail; 525 uint32_t stall_watchdog; 526 527 #ifdef IGB_DEBUG 528 /* 529 * Debug statistics 530 */ 531 uint32_t stat_overload; 532 uint32_t stat_fail_no_tbd; 533 uint32_t stat_fail_no_tcb; 534 uint32_t stat_fail_dma_bind; 535 uint32_t stat_reschedule; 536 #endif 537 538 /* 539 * Pointer to the igb struct 540 */ 541 struct igb *igb; 542 543 } igb_tx_ring_t; 544 545 /* 546 * Software Receive Ring 547 */ 548 typedef struct igb_rx_ring { 549 uint32_t index; /* Ring index */ 550 uint32_t intr_vector; /* Interrupt vector index */ 551 552 /* 553 * Mutexes 554 */ 555 kmutex_t rx_lock; /* Rx access lock */ 556 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 557 558 /* 559 * Rx descriptor ring definitions 560 */ 561 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 562 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 563 uint32_t rbd_next; /* Index of next rx desc */ 564 565 /* 566 * Rx control block list definitions 567 */ 568 rx_control_block_t *rcb_area; 569 rx_control_block_t **work_list; /* Work list of rcbs */ 570 rx_control_block_t **free_list; /* Free list of rcbs */ 571 uint32_t rcb_head; /* Index of next free rcb */ 572 uint32_t rcb_tail; /* Index to put recycled rcb */ 573 uint32_t rcb_free; /* Number of free rcbs */ 574 575 /* 576 * Rx ring settings and status 577 */ 578 uint32_t ring_size; /* Rx descriptor ring size */ 579 uint32_t free_list_size; /* Rx free list size */ 580 uint32_t limit_per_intr; /* Max packets per interrupt */ 581 uint32_t copy_thresh; 582 583 #ifdef IGB_DEBUG 584 /* 585 * Debug statistics 586 */ 587 uint32_t stat_frame_error; 588 uint32_t stat_cksum_error; 589 uint32_t stat_exceed_pkt; 590 #endif 591 592 struct igb *igb; /* Pointer to igb struct */ 593 594 } igb_rx_ring_t; 595 596 typedef struct igb { 597 int instance; 598 mac_handle_t mac_hdl; 599 dev_info_t *dip; 600 struct e1000_hw hw; 601 struct igb_osdep osdep; 602 603 uint32_t igb_state; 604 link_state_t link_state; 605 uint32_t link_speed; 606 uint32_t link_duplex; 607 uint32_t link_down_timeout; 608 609 uint32_t reset_count; 610 uint32_t attach_progress; 611 uint32_t loopback_mode; 612 uint32_t max_frame_size; 613 614 /* 615 * Receive Rings 616 */ 617 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 618 uint32_t num_rx_rings; /* Number of rx rings in use */ 619 uint32_t rx_ring_size; /* Rx descriptor ring size */ 620 uint32_t rx_buf_size; /* Rx buffer size */ 621 622 /* 623 * Transmit Rings 624 */ 625 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 626 uint32_t num_tx_rings; /* Number of tx rings in use */ 627 uint32_t tx_ring_size; /* Tx descriptor ring size */ 628 uint32_t tx_buf_size; /* Tx buffer size */ 629 630 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 631 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 632 boolean_t lso_enable; /* Large Segment Offload */ 633 uint32_t tx_copy_thresh; /* Tx copy threshold */ 634 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 635 uint32_t tx_overload_thresh; /* Tx overload threshold */ 636 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 637 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 638 uint32_t rx_copy_thresh; /* Rx copy threshold */ 639 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 640 uint32_t intr_throttling[MAX_NUM_EITR]; 641 uint32_t intr_force; 642 643 int intr_type; 644 int intr_cnt; 645 int intr_cap; 646 size_t intr_size; 647 uint_t intr_pri; 648 ddi_intr_handle_t *htable; 649 uint32_t eims_mask; 650 651 kmutex_t gen_lock; /* General lock for device access */ 652 kmutex_t watchdog_lock; 653 654 boolean_t watchdog_enable; 655 boolean_t watchdog_start; 656 timeout_id_t watchdog_tid; 657 658 boolean_t unicst_init; 659 uint32_t unicst_avail; 660 uint32_t unicst_total; 661 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 662 uint32_t mcast_count; 663 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 664 665 /* 666 * Kstat definitions 667 */ 668 kstat_t *igb_ks; 669 670 /* 671 * NDD definitions 672 */ 673 caddr_t nd_data; 674 nd_param_t nd_params[PARAM_COUNT]; 675 676 } igb_t; 677 678 typedef struct igb_stat { 679 680 kstat_named_t link_speed; /* Link Speed */ 681 #ifdef IGB_DEBUG 682 kstat_named_t reset_count; /* Reset Count */ 683 684 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 685 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 686 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 687 688 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 689 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 690 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 691 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 692 kstat_named_t tx_reschedule; /* Tx Reschedule */ 693 694 kstat_named_t gprc; /* Good Packets Received Count */ 695 kstat_named_t gptc; /* Good Packets Xmitted Count */ 696 kstat_named_t gor; /* Good Octets Received Count */ 697 kstat_named_t got; /* Good Octets Xmitd Count */ 698 kstat_named_t prc64; /* Packets Received - 64b */ 699 kstat_named_t prc127; /* Packets Received - 65-127b */ 700 kstat_named_t prc255; /* Packets Received - 127-255b */ 701 kstat_named_t prc511; /* Packets Received - 256-511b */ 702 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 703 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 704 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 705 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 706 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 707 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 708 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 709 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 710 #endif 711 kstat_named_t crcerrs; /* CRC Error Count */ 712 kstat_named_t symerrs; /* Symbol Error Count */ 713 kstat_named_t mpc; /* Missed Packet Count */ 714 kstat_named_t scc; /* Single Collision Count */ 715 kstat_named_t ecol; /* Excessive Collision Count */ 716 kstat_named_t mcc; /* Multiple Collision Count */ 717 kstat_named_t latecol; /* Late Collision Count */ 718 kstat_named_t colc; /* Collision Count */ 719 kstat_named_t dc; /* Defer Count */ 720 kstat_named_t sec; /* Sequence Error Count */ 721 kstat_named_t rlec; /* Receive Length Error Count */ 722 kstat_named_t xonrxc; /* XON Received Count */ 723 kstat_named_t xontxc; /* XON Xmitted Count */ 724 kstat_named_t xoffrxc; /* XOFF Received Count */ 725 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 726 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 727 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 728 kstat_named_t mprc; /* Multicast Pkts Received Count */ 729 kstat_named_t rnbc; /* Receive No Buffers Count */ 730 kstat_named_t ruc; /* Receive Undersize Count */ 731 kstat_named_t rfc; /* Receive Frag Count */ 732 kstat_named_t roc; /* Receive Oversize Count */ 733 kstat_named_t rjc; /* Receive Jabber Count */ 734 kstat_named_t tor; /* Total Octets Recvd Count */ 735 kstat_named_t tot; /* Total Octets Xmted Count */ 736 kstat_named_t tpr; /* Total Packets Received */ 737 kstat_named_t tpt; /* Total Packets Xmitted */ 738 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 739 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 740 kstat_named_t algnerrc; /* Alignment Error count */ 741 kstat_named_t rxerrc; /* Rx Error Count */ 742 kstat_named_t tncrs; /* Transmit with no CRS */ 743 kstat_named_t cexterr; /* Carrier Extension Error count */ 744 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 745 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 746 } igb_stat_t; 747 748 /* 749 * Function prototypes in e1000_osdep.c 750 */ 751 void e1000_enable_pciex_master(struct e1000_hw *); 752 753 /* 754 * Function prototypes in igb_buf.c 755 */ 756 int igb_alloc_dma(igb_t *); 757 void igb_free_dma(igb_t *); 758 759 /* 760 * Function prototypes in igb_main.c 761 */ 762 int igb_start(igb_t *); 763 void igb_stop(igb_t *); 764 int igb_setup_link(igb_t *, boolean_t); 765 int igb_unicst_set(igb_t *, const uint8_t *, mac_addr_slot_t); 766 int igb_multicst_add(igb_t *, const uint8_t *); 767 int igb_multicst_remove(igb_t *, const uint8_t *); 768 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 769 void igb_enable_watchdog_timer(igb_t *); 770 void igb_disable_watchdog_timer(igb_t *); 771 int igb_atomic_reserve(uint32_t *, uint32_t); 772 773 /* 774 * Function prototypes in igb_gld.c 775 */ 776 int igb_m_start(void *); 777 void igb_m_stop(void *); 778 int igb_m_promisc(void *, boolean_t); 779 int igb_m_multicst(void *, boolean_t, const uint8_t *); 780 int igb_m_unicst(void *, const uint8_t *); 781 int igb_m_stat(void *, uint_t, uint64_t *); 782 void igb_m_resources(void *); 783 void igb_m_ioctl(void *, queue_t *, mblk_t *); 784 int igb_m_unicst_add(void *, mac_multi_addr_t *); 785 int igb_m_unicst_remove(void *, mac_addr_slot_t); 786 int igb_m_unicst_modify(void *, mac_multi_addr_t *); 787 int igb_m_unicst_get(void *, mac_multi_addr_t *); 788 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 789 790 /* 791 * Function prototypes in igb_rx.c 792 */ 793 mblk_t *igb_rx(igb_rx_ring_t *); 794 void igb_rx_recycle(caddr_t arg); 795 796 /* 797 * Function prototypes in igb_tx.c 798 */ 799 mblk_t *igb_m_tx(void *, mblk_t *); 800 void igb_free_tcb(tx_control_block_t *); 801 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 802 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 803 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 804 805 /* 806 * Function prototypes in igb_log.c 807 */ 808 void igb_notice(void *, const char *, ...); 809 void igb_log(void *, const char *, ...); 810 void igb_error(void *, const char *, ...); 811 812 /* 813 * Function prototypes in igb_ndd.c 814 */ 815 int igb_nd_init(igb_t *); 816 void igb_nd_cleanup(igb_t *); 817 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 818 819 /* 820 * Function prototypes in igb_stat.c 821 */ 822 int igb_init_stats(igb_t *); 823 824 825 #ifdef __cplusplus 826 } 827 #endif 828 829 #endif /* _IGB_SW_H */ 830