1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/ddifm.h> 67 #include <sys/fm/protocol.h> 68 #include <sys/fm/util.h> 69 #include <sys/fm/io/ddi.h> 70 #include "igb_api.h" 71 #include "igb_82575.h" 72 73 74 #define MODULE_NAME "igb" /* module name */ 75 76 #define IGB_SUCCESS DDI_SUCCESS 77 #define IGB_FAILURE DDI_FAILURE 78 79 #define IGB_UNKNOWN 0x00 80 #define IGB_INITIALIZED 0x01 81 #define IGB_STARTED 0x02 82 #define IGB_SUSPENDED 0x04 83 84 #define IGB_INTR_NONE 0 85 #define IGB_INTR_MSIX 1 86 #define IGB_INTR_MSI 2 87 #define IGB_INTR_LEGACY 3 88 89 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 90 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 91 92 #define IGB_NO_POLL -1 93 #define IGB_NO_FREE_SLOT -1 94 95 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 96 #define MAX_NUM_MULTICAST_ADDRESSES 256 97 #define MAX_COOKIE 16 98 #define MIN_NUM_TX_DESC 2 99 100 /* 101 * Number of settings for interrupt throttle rate (ITR). There is one of 102 * these per msi-x vector and it needs to be the maximum of all silicon 103 * types supported by this driver. 104 */ 105 #define MAX_NUM_EITR 25 106 107 /* 108 * Maximum values for user configurable parameters 109 */ 110 #define MAX_TX_RING_SIZE 4096 111 #define MAX_RX_RING_SIZE 4096 112 #define MAX_RX_GROUP_NUM 4 113 114 #define MAX_MTU 9000 115 #define MAX_RX_LIMIT_PER_INTR 4096 116 #define MAX_RX_INTR_DELAY 65535 117 #define MAX_RX_INTR_ABS_DELAY 65535 118 #define MAX_TX_INTR_DELAY 65535 119 #define MAX_TX_INTR_ABS_DELAY 65535 120 121 #define MAX_RX_COPY_THRESHOLD 9216 122 #define MAX_TX_COPY_THRESHOLD 9216 123 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 124 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 126 127 /* 128 * Minimum values for user configurable parameters 129 */ 130 #define MIN_TX_RING_SIZE 64 131 #define MIN_RX_RING_SIZE 64 132 #define MIN_RX_GROUP_NUM 1 133 134 #define MIN_MTU ETHERMIN 135 #define MIN_RX_LIMIT_PER_INTR 16 136 #define MIN_RX_INTR_DELAY 0 137 #define MIN_RX_INTR_ABS_DELAY 0 138 #define MIN_TX_INTR_DELAY 0 139 #define MIN_TX_INTR_ABS_DELAY 0 140 #define MIN_RX_COPY_THRESHOLD 0 141 #define MIN_TX_COPY_THRESHOLD 0 142 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 143 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 144 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 145 146 /* 147 * Default values for user configurable parameters 148 */ 149 #define DEFAULT_TX_RING_SIZE 512 150 #define DEFAULT_RX_RING_SIZE 512 151 #define DEFAULT_RX_GROUP_NUM 1 152 153 #define DEFAULT_MTU ETHERMTU 154 #define DEFAULT_RX_LIMIT_PER_INTR 256 155 #define DEFAULT_RX_INTR_DELAY 0 156 #define DEFAULT_RX_INTR_ABS_DELAY 0 157 #define DEFAULT_TX_INTR_DELAY 300 158 #define DEFAULT_TX_INTR_ABS_DELAY 0 159 #define DEFAULT_RX_COPY_THRESHOLD 128 160 #define DEFAULT_TX_COPY_THRESHOLD 512 161 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 162 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 163 #define DEFAULT_TX_RESCHED_THRESHOLD 128 164 165 #define TX_DRAIN_TIME 200 166 #define RX_DRAIN_TIME 200 167 168 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 169 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 170 171 /* 172 * Defined for IP header alignment. 173 */ 174 #define IPHDR_ALIGN_ROOM 2 175 176 /* 177 * Bit flags for attach_progress 178 */ 179 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 180 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 181 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 182 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 183 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 184 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 185 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 186 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 187 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 188 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 189 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 190 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 191 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 192 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 193 194 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 195 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 196 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 197 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 198 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 199 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 200 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 201 #define PROP_DEFAULT_MTU "default_mtu" 202 #define PROP_FLOW_CONTROL "flow_control" 203 #define PROP_TX_RING_SIZE "tx_ring_size" 204 #define PROP_RX_RING_SIZE "rx_ring_size" 205 #define PROP_MR_ENABLE "mr_enable" 206 #define PROP_RX_GROUP_NUM "rx_group_number" 207 208 #define PROP_INTR_FORCE "intr_force" 209 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 210 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 211 #define PROP_LSO_ENABLE "lso_enable" 212 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 213 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 214 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 215 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 216 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 217 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 218 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 219 #define PROP_INTR_THROTTLING "intr_throttling" 220 221 #define IGB_LB_NONE 0 222 #define IGB_LB_EXTERNAL 1 223 #define IGB_LB_INTERNAL_MAC 2 224 #define IGB_LB_INTERNAL_PHY 3 225 #define IGB_LB_INTERNAL_SERDES 4 226 227 /* 228 * Shorthand for the NDD parameters 229 */ 230 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 231 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 232 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 233 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 234 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 235 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 236 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 237 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 238 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 239 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 240 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 241 242 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 243 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 244 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 245 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 246 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 247 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 248 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 249 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 250 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 251 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 252 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 253 254 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 255 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 256 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 257 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 258 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 259 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 260 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 261 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 262 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 263 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 264 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 265 266 enum ioc_reply { 267 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 268 IOC_DONE, /* OK, reply sent */ 269 IOC_ACK, /* OK, just send ACK */ 270 IOC_REPLY /* OK, just send reply */ 271 }; 272 273 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 274 (uintptr_t)(mp)->b_rptr) 275 276 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 277 0, 0, (flag))) 278 279 /* 280 * Defined for ring index operations 281 * ASSERT(index < limit) 282 * ASSERT(step < limit) 283 * ASSERT(index1 < limit) 284 * ASSERT(index2 < limit) 285 */ 286 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 287 (index) + (step) : (index) + (step) - (limit)) 288 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 289 (index) - (step) : (index) + (limit) - (step)) 290 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 291 (index2) - (index1) : (index2) + (limit) - (index1)) 292 293 #define LINK_LIST_INIT(_LH) \ 294 (_LH)->head = (_LH)->tail = NULL 295 296 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 297 298 #define LIST_POP_HEAD(_LH) \ 299 (single_link_t *)(_LH)->head; \ 300 { \ 301 if ((_LH)->head != NULL) { \ 302 (_LH)->head = (_LH)->head->link; \ 303 if ((_LH)->head == NULL) \ 304 (_LH)->tail = NULL; \ 305 } \ 306 } 307 308 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 309 310 #define LIST_PUSH_TAIL(_LH, _E) \ 311 if ((_LH)->tail != NULL) { \ 312 (_LH)->tail->link = (single_link_t *)(_E); \ 313 (_LH)->tail = (single_link_t *)(_E); \ 314 } else { \ 315 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 316 } \ 317 (_E)->link = NULL; 318 319 #define LIST_GET_NEXT(_LH, _E) \ 320 (((_LH)->tail == (single_link_t *)(_E)) ? \ 321 NULL : ((single_link_t *)(_E))->link) 322 323 324 typedef struct single_link { 325 struct single_link *link; 326 } single_link_t; 327 328 typedef struct link_list { 329 single_link_t *head; 330 single_link_t *tail; 331 } link_list_t; 332 333 /* 334 * Property lookups 335 */ 336 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 337 DDI_PROP_DONTPASS, (n)) 338 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 339 DDI_PROP_DONTPASS, (n), -1) 340 341 342 /* capability/feature flags */ 343 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 344 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 345 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 346 347 /* function pointer for nic-specific functions */ 348 typedef void (*igb_nic_func_t)(struct igb *); 349 350 /* adapter-specific info for each supported device type */ 351 typedef struct adapter_info { 352 /* limits */ 353 uint32_t max_rx_que_num; /* maximum number of rx queues */ 354 uint32_t min_rx_que_num; /* minimum number of rx queues */ 355 uint32_t def_rx_que_num; /* default number of rx queues */ 356 uint32_t max_tx_que_num; /* maximum number of tx queues */ 357 uint32_t min_tx_que_num; /* minimum number of tx queues */ 358 uint32_t def_tx_que_num; /* default number of tx queues */ 359 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 360 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 361 uint32_t def_intr_throttle; /* default interrupt throttle */ 362 /* function pointers */ 363 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 364 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 365 /* capabilities */ 366 uint32_t flags; /* capability flags */ 367 } adapter_info_t; 368 369 /* 370 * Named Data (ND) Parameter Management Structure 371 */ 372 typedef struct { 373 struct igb *private; 374 uint32_t info; 375 uint32_t min; 376 uint32_t max; 377 uint32_t val; 378 char *name; 379 } nd_param_t; 380 381 /* 382 * NDD parameter indexes, divided into: 383 * 384 * read-only parameters describing the hardware's capabilities 385 * read-write parameters controlling the advertised capabilities 386 * read-only parameters describing the partner's capabilities 387 * read-write parameters controlling the force speed and duplex 388 * read-only parameters describing the link state 389 * read-only parameters describing the driver properties 390 * read-write parameters controlling the driver properties 391 */ 392 enum { 393 PARAM_AUTONEG_CAP, 394 PARAM_PAUSE_CAP, 395 PARAM_ASYM_PAUSE_CAP, 396 PARAM_1000FDX_CAP, 397 PARAM_1000HDX_CAP, 398 PARAM_100T4_CAP, 399 PARAM_100FDX_CAP, 400 PARAM_100HDX_CAP, 401 PARAM_10FDX_CAP, 402 PARAM_10HDX_CAP, 403 PARAM_REM_FAULT, 404 405 PARAM_ADV_AUTONEG_CAP, 406 PARAM_ADV_PAUSE_CAP, 407 PARAM_ADV_ASYM_PAUSE_CAP, 408 PARAM_ADV_1000FDX_CAP, 409 PARAM_ADV_1000HDX_CAP, 410 PARAM_ADV_100T4_CAP, 411 PARAM_ADV_100FDX_CAP, 412 PARAM_ADV_100HDX_CAP, 413 PARAM_ADV_10FDX_CAP, 414 PARAM_ADV_10HDX_CAP, 415 PARAM_ADV_REM_FAULT, 416 417 PARAM_LP_AUTONEG_CAP, 418 PARAM_LP_PAUSE_CAP, 419 PARAM_LP_ASYM_PAUSE_CAP, 420 PARAM_LP_1000FDX_CAP, 421 PARAM_LP_1000HDX_CAP, 422 PARAM_LP_100T4_CAP, 423 PARAM_LP_100FDX_CAP, 424 PARAM_LP_100HDX_CAP, 425 PARAM_LP_10FDX_CAP, 426 PARAM_LP_10HDX_CAP, 427 PARAM_LP_REM_FAULT, 428 429 PARAM_LINK_STATUS, 430 PARAM_LINK_SPEED, 431 PARAM_LINK_DUPLEX, 432 433 PARAM_COUNT 434 }; 435 436 typedef union igb_ether_addr { 437 struct { 438 uint32_t high; 439 uint32_t low; 440 } reg; 441 struct { 442 uint8_t set; 443 uint8_t group_index; 444 uint8_t addr[ETHERADDRL]; 445 } mac; 446 } igb_ether_addr_t; 447 448 typedef enum { 449 USE_NONE, 450 USE_COPY, 451 USE_DMA 452 } tx_type_t; 453 454 typedef enum { 455 RCB_FREE, 456 RCB_SENDUP 457 } rcb_state_t; 458 459 typedef struct hcksum_context { 460 uint32_t hcksum_flags; 461 uint32_t ip_hdr_len; 462 uint32_t mac_hdr_len; 463 uint32_t l4_proto; 464 } hcksum_context_t; 465 466 /* Hold address/length of each DMA segment */ 467 typedef struct sw_desc { 468 uint64_t address; 469 size_t length; 470 } sw_desc_t; 471 472 /* Handles and addresses of DMA buffer */ 473 typedef struct dma_buffer { 474 caddr_t address; /* Virtual address */ 475 uint64_t dma_address; /* DMA (Hardware) address */ 476 ddi_acc_handle_t acc_handle; /* Data access handle */ 477 ddi_dma_handle_t dma_handle; /* DMA handle */ 478 size_t size; /* Buffer size */ 479 size_t len; /* Data length in the buffer */ 480 } dma_buffer_t; 481 482 /* 483 * Tx Control Block 484 */ 485 typedef struct tx_control_block { 486 single_link_t link; 487 uint32_t frag_num; 488 uint32_t desc_num; 489 mblk_t *mp; 490 tx_type_t tx_type; 491 ddi_dma_handle_t tx_dma_handle; 492 dma_buffer_t tx_buf; 493 sw_desc_t desc[MAX_COOKIE]; 494 } tx_control_block_t; 495 496 /* 497 * RX Control Block 498 */ 499 typedef struct rx_control_block { 500 mblk_t *mp; 501 rcb_state_t state; 502 dma_buffer_t rx_buf; 503 frtn_t free_rtn; 504 struct igb_rx_ring *rx_ring; 505 } rx_control_block_t; 506 507 /* 508 * Software Data Structure for Tx Ring 509 */ 510 typedef struct igb_tx_ring { 511 uint32_t index; /* Ring index */ 512 uint32_t intr_vector; /* Interrupt vector index */ 513 514 /* 515 * Mutexes 516 */ 517 kmutex_t tx_lock; 518 kmutex_t recycle_lock; 519 kmutex_t tcb_head_lock; 520 kmutex_t tcb_tail_lock; 521 522 /* 523 * Tx descriptor ring definitions 524 */ 525 dma_buffer_t tbd_area; 526 union e1000_adv_tx_desc *tbd_ring; 527 uint32_t tbd_head; /* Index of next tbd to recycle */ 528 uint32_t tbd_tail; /* Index of next tbd to transmit */ 529 uint32_t tbd_free; /* Number of free tbd */ 530 531 /* 532 * Tx control block list definitions 533 */ 534 tx_control_block_t *tcb_area; 535 tx_control_block_t **work_list; 536 tx_control_block_t **free_list; 537 uint32_t tcb_head; /* Head index of free list */ 538 uint32_t tcb_tail; /* Tail index of free list */ 539 uint32_t tcb_free; /* Number of free tcb in free list */ 540 541 uint32_t *tbd_head_wb; /* Head write-back */ 542 uint32_t (*tx_recycle)(struct igb_tx_ring *); 543 544 /* 545 * TCP/UDP checksum offload 546 */ 547 hcksum_context_t hcksum_context; 548 549 /* 550 * Tx ring settings and status 551 */ 552 uint32_t ring_size; /* Tx descriptor ring size */ 553 uint32_t free_list_size; /* Tx free list size */ 554 uint32_t copy_thresh; 555 uint32_t recycle_thresh; 556 uint32_t overload_thresh; 557 uint32_t resched_thresh; 558 559 boolean_t reschedule; 560 uint32_t recycle_fail; 561 uint32_t stall_watchdog; 562 563 #ifdef IGB_DEBUG 564 /* 565 * Debug statistics 566 */ 567 uint32_t stat_overload; 568 uint32_t stat_fail_no_tbd; 569 uint32_t stat_fail_no_tcb; 570 uint32_t stat_fail_dma_bind; 571 uint32_t stat_reschedule; 572 uint32_t stat_pkt_cnt; 573 #endif 574 575 /* 576 * Pointer to the igb struct 577 */ 578 struct igb *igb; 579 mac_ring_handle_t ring_handle; /* call back ring handle */ 580 } igb_tx_ring_t; 581 582 /* 583 * Software Receive Ring 584 */ 585 typedef struct igb_rx_ring { 586 uint32_t index; /* Ring index */ 587 uint32_t intr_vector; /* Interrupt vector index */ 588 589 /* 590 * Mutexes 591 */ 592 kmutex_t rx_lock; /* Rx access lock */ 593 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 594 595 /* 596 * Rx descriptor ring definitions 597 */ 598 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 599 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 600 uint32_t rbd_next; /* Index of next rx desc */ 601 602 /* 603 * Rx control block list definitions 604 */ 605 rx_control_block_t *rcb_area; 606 rx_control_block_t **work_list; /* Work list of rcbs */ 607 rx_control_block_t **free_list; /* Free list of rcbs */ 608 uint32_t rcb_head; /* Index of next free rcb */ 609 uint32_t rcb_tail; /* Index to put recycled rcb */ 610 uint32_t rcb_free; /* Number of free rcbs */ 611 612 /* 613 * Rx ring settings and status 614 */ 615 uint32_t ring_size; /* Rx descriptor ring size */ 616 uint32_t free_list_size; /* Rx free list size */ 617 uint32_t limit_per_intr; /* Max packets per interrupt */ 618 uint32_t copy_thresh; 619 620 #ifdef IGB_DEBUG 621 /* 622 * Debug statistics 623 */ 624 uint32_t stat_frame_error; 625 uint32_t stat_cksum_error; 626 uint32_t stat_exceed_pkt; 627 uint32_t stat_pkt_cnt; 628 #endif 629 630 struct igb *igb; /* Pointer to igb struct */ 631 mac_ring_handle_t ring_handle; /* call back ring handle */ 632 uint32_t group_index; /* group index */ 633 uint64_t ring_gen_num; 634 } igb_rx_ring_t; 635 636 /* 637 * Software Receive Ring Group 638 */ 639 typedef struct igb_rx_group { 640 uint32_t index; /* Group index */ 641 mac_group_handle_t group_handle; /* call back group handle */ 642 struct igb *igb; /* Pointer to igb struct */ 643 } igb_rx_group_t; 644 645 typedef struct igb { 646 int instance; 647 mac_handle_t mac_hdl; 648 dev_info_t *dip; 649 struct e1000_hw hw; 650 struct igb_osdep osdep; 651 652 adapter_info_t *capab; /* adapter capabilities */ 653 654 uint32_t igb_state; 655 link_state_t link_state; 656 uint32_t link_speed; 657 uint32_t link_duplex; 658 uint32_t link_down_timeout; 659 660 uint32_t reset_count; 661 uint32_t attach_progress; 662 uint32_t loopback_mode; 663 uint32_t max_frame_size; 664 665 uint32_t mr_enable; /* Enable multiple rings */ 666 uint32_t vmdq_mode; /* Mode of VMDq */ 667 668 /* 669 * Receive Rings and Groups 670 */ 671 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 672 uint32_t num_rx_rings; /* Number of rx rings in use */ 673 uint32_t rx_ring_size; /* Rx descriptor ring size */ 674 uint32_t rx_buf_size; /* Rx buffer size */ 675 igb_rx_group_t *rx_groups; /* Array of rx groups */ 676 uint32_t num_rx_groups; /* Number of rx groups in use */ 677 678 /* 679 * Transmit Rings 680 */ 681 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 682 uint32_t num_tx_rings; /* Number of tx rings in use */ 683 uint32_t tx_ring_size; /* Tx descriptor ring size */ 684 uint32_t tx_buf_size; /* Tx buffer size */ 685 686 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 687 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 688 boolean_t lso_enable; /* Large Segment Offload */ 689 uint32_t tx_copy_thresh; /* Tx copy threshold */ 690 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 691 uint32_t tx_overload_thresh; /* Tx overload threshold */ 692 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 693 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 694 uint32_t rx_copy_thresh; /* Rx copy threshold */ 695 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 696 uint32_t intr_throttling[MAX_NUM_EITR]; 697 uint32_t intr_force; 698 699 int intr_type; 700 int intr_cnt; 701 int intr_cap; 702 size_t intr_size; 703 uint_t intr_pri; 704 ddi_intr_handle_t *htable; 705 uint32_t eims_mask; 706 uint32_t ims_mask; 707 708 kmutex_t gen_lock; /* General lock for device access */ 709 kmutex_t watchdog_lock; 710 711 boolean_t watchdog_enable; 712 boolean_t watchdog_start; 713 timeout_id_t watchdog_tid; 714 715 boolean_t unicst_init; 716 uint32_t unicst_avail; 717 uint32_t unicst_total; 718 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 719 uint32_t mcast_count; 720 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 721 722 /* 723 * Kstat definitions 724 */ 725 kstat_t *igb_ks; 726 727 /* 728 * NDD definitions 729 */ 730 caddr_t nd_data; 731 nd_param_t nd_params[PARAM_COUNT]; 732 733 /* 734 * FMA capabilities 735 */ 736 int fm_capabilities; 737 738 } igb_t; 739 740 typedef struct igb_stat { 741 742 kstat_named_t link_speed; /* Link Speed */ 743 #ifdef IGB_DEBUG 744 kstat_named_t reset_count; /* Reset Count */ 745 746 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 747 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 748 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 749 750 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 751 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 752 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 753 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 754 kstat_named_t tx_reschedule; /* Tx Reschedule */ 755 756 kstat_named_t gprc; /* Good Packets Received Count */ 757 kstat_named_t gptc; /* Good Packets Xmitted Count */ 758 kstat_named_t gor; /* Good Octets Received Count */ 759 kstat_named_t got; /* Good Octets Xmitd Count */ 760 kstat_named_t prc64; /* Packets Received - 64b */ 761 kstat_named_t prc127; /* Packets Received - 65-127b */ 762 kstat_named_t prc255; /* Packets Received - 127-255b */ 763 kstat_named_t prc511; /* Packets Received - 256-511b */ 764 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 765 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 766 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 767 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 768 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 769 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 770 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 771 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 772 #endif 773 kstat_named_t crcerrs; /* CRC Error Count */ 774 kstat_named_t symerrs; /* Symbol Error Count */ 775 kstat_named_t mpc; /* Missed Packet Count */ 776 kstat_named_t scc; /* Single Collision Count */ 777 kstat_named_t ecol; /* Excessive Collision Count */ 778 kstat_named_t mcc; /* Multiple Collision Count */ 779 kstat_named_t latecol; /* Late Collision Count */ 780 kstat_named_t colc; /* Collision Count */ 781 kstat_named_t dc; /* Defer Count */ 782 kstat_named_t sec; /* Sequence Error Count */ 783 kstat_named_t rlec; /* Receive Length Error Count */ 784 kstat_named_t xonrxc; /* XON Received Count */ 785 kstat_named_t xontxc; /* XON Xmitted Count */ 786 kstat_named_t xoffrxc; /* XOFF Received Count */ 787 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 788 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 789 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 790 kstat_named_t mprc; /* Multicast Pkts Received Count */ 791 kstat_named_t rnbc; /* Receive No Buffers Count */ 792 kstat_named_t ruc; /* Receive Undersize Count */ 793 kstat_named_t rfc; /* Receive Frag Count */ 794 kstat_named_t roc; /* Receive Oversize Count */ 795 kstat_named_t rjc; /* Receive Jabber Count */ 796 kstat_named_t tor; /* Total Octets Recvd Count */ 797 kstat_named_t tot; /* Total Octets Xmted Count */ 798 kstat_named_t tpr; /* Total Packets Received */ 799 kstat_named_t tpt; /* Total Packets Xmitted */ 800 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 801 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 802 kstat_named_t algnerrc; /* Alignment Error count */ 803 kstat_named_t rxerrc; /* Rx Error Count */ 804 kstat_named_t tncrs; /* Transmit with no CRS */ 805 kstat_named_t cexterr; /* Carrier Extension Error count */ 806 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 807 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 808 } igb_stat_t; 809 810 /* 811 * Function prototypes in e1000_osdep.c 812 */ 813 void e1000_enable_pciex_master(struct e1000_hw *); 814 void e1000_rar_clear(struct e1000_hw *hw, uint32_t); 815 void e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *, uint32_t, 816 uint32_t, uint8_t); 817 818 /* 819 * Function prototypes in igb_buf.c 820 */ 821 int igb_alloc_dma(igb_t *); 822 void igb_free_dma(igb_t *); 823 824 /* 825 * Function prototypes in igb_main.c 826 */ 827 int igb_start(igb_t *); 828 void igb_stop(igb_t *); 829 int igb_setup_link(igb_t *, boolean_t); 830 int igb_unicst_find(igb_t *, const uint8_t *); 831 int igb_unicst_set(igb_t *, const uint8_t *, int); 832 int igb_multicst_add(igb_t *, const uint8_t *); 833 int igb_multicst_remove(igb_t *, const uint8_t *); 834 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 835 void igb_enable_watchdog_timer(igb_t *); 836 void igb_disable_watchdog_timer(igb_t *); 837 int igb_atomic_reserve(uint32_t *, uint32_t); 838 int igb_check_acc_handle(ddi_acc_handle_t); 839 int igb_check_dma_handle(ddi_dma_handle_t); 840 void igb_fm_ereport(igb_t *, char *); 841 void igb_set_fma_flags(int, int); 842 843 /* 844 * Function prototypes in igb_gld.c 845 */ 846 int igb_m_start(void *); 847 void igb_m_stop(void *); 848 int igb_m_promisc(void *, boolean_t); 849 int igb_m_multicst(void *, boolean_t, const uint8_t *); 850 int igb_m_unicst(void *, const uint8_t *); 851 int igb_m_stat(void *, uint_t, uint64_t *); 852 void igb_m_resources(void *); 853 void igb_m_ioctl(void *, queue_t *, mblk_t *); 854 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 855 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 856 mac_ring_info_t *, mac_ring_handle_t); 857 void igb_fill_group(void *arg, mac_ring_type_t, const int, 858 mac_group_info_t *, mac_group_handle_t); 859 int igb_rx_ring_intr_enable(mac_intr_handle_t); 860 int igb_rx_ring_intr_disable(mac_intr_handle_t); 861 862 /* 863 * Function prototypes in igb_rx.c 864 */ 865 mblk_t *igb_rx(igb_rx_ring_t *, int); 866 void igb_rx_recycle(caddr_t arg); 867 868 /* 869 * Function prototypes in igb_tx.c 870 */ 871 void igb_free_tcb(tx_control_block_t *); 872 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 873 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 874 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 875 876 /* 877 * Function prototypes in igb_log.c 878 */ 879 void igb_notice(void *, const char *, ...); 880 void igb_log(void *, const char *, ...); 881 void igb_error(void *, const char *, ...); 882 883 /* 884 * Function prototypes in igb_ndd.c 885 */ 886 int igb_nd_init(igb_t *); 887 void igb_nd_cleanup(igb_t *); 888 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 889 890 /* 891 * Function prototypes in igb_stat.c 892 */ 893 int igb_init_stats(igb_t *); 894 895 mblk_t *igb_rx_ring_poll(void *, int); 896 mblk_t *igb_tx_ring_send(void *, mblk_t *); 897 898 #ifdef __cplusplus 899 } 900 #endif 901 902 #endif /* _IGB_SW_H */ 903