1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2025 Oxide Computer Company
14 */
15
16 /*
17 * Portions of the i2c nexus that directly interface with the parent controller
18 * that we create.
19 */
20
21 #include <sys/modctl.h>
22 #include <sys/conf.h>
23 #include <sys/devops.h>
24 #include <sys/ddi.h>
25 #include <sys/sunddi.h>
26 #include <sys/sunndi.h>
27 #include <sys/stddef.h>
28 #include <sys/mkdev.h>
29 #include <sys/ctype.h>
30
31 #include "i2cnex.h"
32
33 /*
34 * These are kept as non-static const values so that they can be tuned. This is
35 * not a committed interface and if we need to, these timeout values should
36 * instead be transformed into standard framework properties.
37 *
38 * We have selected a 100ms wait for the bus to be free. This is greater than
39 * the time that sending 512 bytes should take at 100 kHz. At 100 kHz, you can
40 * send 1 bit in 10us, or a byte in 80 us. To send 512 bytes (the largest I/O we
41 * do in one go), is 40.96 ms. Doubling that gets us to 100ms.
42 *
43 * For an entire I/O operation, we increase that to 500ms for now to give device
44 * drivers and other things a bit of leeway. This should be refined in the
45 * future. For an abort, we increase that to 1s.
46 *
47 * For polling, we use this minimal time of 15us. This value means 1 bit will be
48 * transferred, which usually isn't enough time at 100 kHz, but does a bit
49 * better at faster speeds. Some controllers also wait for say an empty status
50 * to be set to determine if they even do anything.
51 *
52 * These could be dependent on the controller's actual speed in the future.
53 */
54 uint32_t i2c_ctrl_to_bus_act_count = 100;
55 uint32_t i2c_ctrl_to_bus_act_delay_us = 1000;
56
57 uint32_t i2c_ctrl_to_io_count = 1;
58 uint32_t i2c_ctrl_to_io_delay_us = 500 * (MICROSEC / MILLISEC);
59
60 uint32_t i2c_ctrl_to_abort_count = 1;
61 uint32_t i2c_ctrl_to_abort_delay_us = 1000 * (MICROSEC / MILLISEC);
62
63 uint32_t i2c_ctrl_to_poll_ctrl_count = 1;
64 uint32_t i2c_ctrl_to_poll_ctrl_delay_us = 15;
65
66 static int
i2c_nex_ctrl_bus_config(dev_info_t * pdip,uint_t flags,ddi_bus_config_op_t op,void * arg,dev_info_t ** childp)67 i2c_nex_ctrl_bus_config(dev_info_t *pdip, uint_t flags, ddi_bus_config_op_t op,
68 void *arg, dev_info_t **childp)
69 {
70 i2c_nex_bus_config_t conf;
71 i2c_root_t *root = i2c_dip_to_root(pdip);
72
73 if (root == NULL) {
74 return (NDI_BADHANDLE);
75 }
76
77 switch (op) {
78 case BUS_CONFIG_ONE:
79 case BUS_CONFIG_ALL:
80 case BUS_CONFIG_DRIVER:
81 ndi_devi_enter(pdip);
82 break;
83 default:
84 return (NDI_FAILURE);
85 }
86
87 if (!i2c_nex_bus_config_init(&conf, op, arg)) {
88 ndi_devi_exit(pdip);
89 return (NDI_EINVAL);
90 }
91 mutex_enter(&root->ir_mutex);
92 for (i2c_ctrl_t *ctrl = list_head(&root->ir_ctrls); ctrl != NULL;
93 ctrl = list_next(&root->ir_ctrls, ctrl)) {
94 i2c_nex_bus_config_one(ctrl->ic_nexus, &conf);
95 }
96 mutex_exit(&root->ir_mutex);
97 i2c_nex_bus_config_fini(&conf);
98 ndi_devi_exit(pdip);
99
100 if (op == BUS_CONFIG_ONE) {
101 if (!conf.inbc_matched) {
102 return (NDI_EINVAL);
103 }
104
105 if (conf.inbc_ret != NDI_SUCCESS) {
106 return (conf.inbc_ret);
107 }
108 }
109
110 flags |= NDI_ONLINE_ATTACH;
111 return (ndi_busop_bus_config(pdip, flags, op, arg, childp, 0));
112 }
113
114 static int
i2c_nex_ctrl_bus_unconfig(dev_info_t * pdip,uint_t flags,ddi_bus_config_op_t op,void * arg)115 i2c_nex_ctrl_bus_unconfig(dev_info_t *pdip, uint_t flags,
116 ddi_bus_config_op_t op, void *arg)
117 {
118 int ret;
119 i2c_nex_bus_config_t conf;
120 i2c_root_t *root = i2c_dip_to_root(pdip);
121
122 if (root == NULL) {
123 return (NDI_BADHANDLE);
124 }
125
126 switch (op) {
127 case BUS_UNCONFIG_ONE:
128 case BUS_UNCONFIG_ALL:
129 case BUS_UNCONFIG_DRIVER:
130 ndi_devi_enter(pdip);
131 flags |= NDI_UNCONFIG;
132 ret = ndi_busop_bus_unconfig(pdip, flags, op, arg);
133 if (ret != 0) {
134 ndi_devi_exit(pdip);
135 return (ret);
136 }
137 break;
138 default:
139 return (NDI_FAILURE);
140 }
141
142 if (!i2c_nex_bus_config_init(&conf, op, arg)) {
143 ndi_devi_exit(pdip);
144 return (NDI_EINVAL);
145 }
146
147 mutex_enter(&root->ir_mutex);
148 for (i2c_ctrl_t *ctrl = list_head(&root->ir_ctrls); ctrl != NULL;
149 ctrl = list_next(&root->ir_ctrls, ctrl)) {
150 i2c_nex_bus_unconfig_one(ctrl->ic_nexus, &conf);
151 }
152 mutex_exit(&root->ir_mutex);
153 i2c_nex_bus_config_fini(&conf);
154 ndi_devi_exit(pdip);
155
156 if (op == BUS_CONFIG_ONE) {
157
158 if (!conf.inbc_matched) {
159 return (NDI_EINVAL);
160 }
161
162 if (conf.inbc_ret != NDI_SUCCESS) {
163 return (conf.inbc_ret);
164 }
165 }
166
167 return (NDI_SUCCESS);
168 }
169
170 /*
171 * The controller's bus ops need to generally call into the parent for all DMA
172 * activity. The main things that we need to define here are the bus_ctl,
173 * bus_config, and bus_unconfig.
174 */
175 static struct bus_ops i2c_nex_ctrl_bus_ops = {
176 .busops_rev = BUSO_REV,
177 .bus_dma_map = ddi_no_dma_map,
178 .bus_dma_allochdl = ddi_dma_allochdl,
179 .bus_dma_freehdl = ddi_dma_freehdl,
180 .bus_dma_bindhdl = ddi_dma_bindhdl,
181 .bus_dma_unbindhdl = ddi_dma_unbindhdl,
182 .bus_dma_flush = ddi_dma_flush,
183 .bus_dma_win = ddi_dma_win,
184 .bus_dma_ctl = ddi_dma_mctl,
185 .bus_prop_op = ddi_bus_prop_op,
186 .bus_ctl = i2c_nex_bus_ctl,
187 .bus_config = i2c_nex_ctrl_bus_config,
188 .bus_unconfig = i2c_nex_ctrl_bus_unconfig
189 };
190
191 void
i2c_ctrl_mod_fini(struct dev_ops * ops)192 i2c_ctrl_mod_fini(struct dev_ops *ops)
193 {
194 ops->devo_bus_ops = NULL;
195 }
196
197 void
i2c_ctrl_mod_init(struct dev_ops * ops)198 i2c_ctrl_mod_init(struct dev_ops *ops)
199 {
200 ops->devo_bus_ops = &i2c_nex_ctrl_bus_ops;
201 }
202
203 void
i2c_ctrl_register_free(i2c_ctrl_register_t * reg)204 i2c_ctrl_register_free(i2c_ctrl_register_t *reg)
205 {
206 if (reg == NULL)
207 return;
208 kmem_free(reg, sizeof (i2c_ctrl_register_t));
209 }
210
211 i2c_ctrl_reg_error_t
i2c_ctrl_register_alloc(uint32_t vers,i2c_ctrl_register_t ** regp)212 i2c_ctrl_register_alloc(uint32_t vers, i2c_ctrl_register_t **regp)
213 {
214 i2c_ctrl_register_t *reg;
215
216 if (vers != I2C_CTRL_PROVIDER_V0) {
217 return (I2C_CTRL_REG_E_BAD_VERS);
218 }
219
220 reg = kmem_zalloc(sizeof (i2c_ctrl_register_t), KM_SLEEP);
221 reg->ic_vers = I2C_CTRL_PROVIDER_V0;
222
223 *regp = reg;
224 return (I2C_CTRL_REG_E_OK);
225 }
226
227 static void
i2c_ctrl_lock_fini(i2c_ctrl_lock_t * lock)228 i2c_ctrl_lock_fini(i2c_ctrl_lock_t *lock)
229 {
230 VERIFY3P(lock->cl_owner, ==, NULL);
231 VERIFY3U(list_is_empty(&lock->cl_stack), !=, 0);
232 VERIFY3U(list_is_empty(&lock->cl_waiters), !=, 0);
233
234 list_destroy(&lock->cl_stack);
235 list_destroy(&lock->cl_waiters);
236 mutex_destroy(&lock->cl_mutex);
237 }
238
239 static void
i2c_ctrl_lock_init(i2c_ctrl_lock_t * lock)240 i2c_ctrl_lock_init(i2c_ctrl_lock_t *lock)
241 {
242 mutex_init(&lock->cl_mutex, NULL, MUTEX_DRIVER, NULL);
243 list_create(&lock->cl_waiters, sizeof (i2c_txn_t),
244 offsetof(i2c_txn_t, txn_wait_link));
245 list_create(&lock->cl_stack, sizeof (i2c_txn_t),
246 offsetof(i2c_txn_t, txn_stack_link));
247 }
248
249 /*
250 * Port cleanup is part of the actual attach/detach of the i2cnex. We don't do
251 * that in register/unregister.
252 */
253 static void
i2c_ctrl_cleanup(i2c_ctrl_t * ctrl)254 i2c_ctrl_cleanup(i2c_ctrl_t *ctrl)
255 {
256 i2cnex_nex_free(ctrl->ic_nexus);
257 ctrl->ic_nexus = NULL;
258
259 mutex_destroy(&ctrl->ic_txn_lock);
260 list_destroy(&ctrl->ic_txns);
261
262 /*
263 * As this is tearing down, we may need to remove any remnants of a plan
264 * or active mux.
265 */
266 while (list_remove_head(&ctrl->ic_mux_plan) != NULL)
267 ;
268 while (list_remove_head(&ctrl->ic_mux_active) != NULL)
269 ;
270
271 list_destroy(&ctrl->ic_mux_plan);
272 list_destroy(&ctrl->ic_mux_active);
273 i2c_ctrl_lock_fini(&ctrl->ic_lock);
274 kmem_free(ctrl, sizeof (i2c_ctrl_t));
275 }
276
277 i2c_ctrl_reg_error_t
i2c_ctrl_unregister(i2c_ctrl_hdl_t * hdl)278 i2c_ctrl_unregister(i2c_ctrl_hdl_t *hdl)
279 {
280 i2c_ctrl_t *ctrl;
281 i2c_root_t *root;
282
283 if (hdl == NULL) {
284 return (I2C_CTRL_REG_E_OK);
285 }
286
287 ctrl = (i2c_ctrl_t *)hdl;
288
289 /*
290 * If we made it here, by definition we have no children and there are
291 * no open file descriptors on the controller. Therefore it should be
292 * safe to allow this to be torn down.
293 */
294
295 root = ctrl->ic_root;
296
297 mutex_enter(&i2cnex_minors.im_mutex);
298 mutex_enter(&root->ir_mutex);
299 list_remove(&ctrl->ic_root->ir_ctrls, ctrl);
300 ctrl->ic_root = NULL;
301
302 /*
303 * If this was the last controller that was present here, then we need
304 * to clean up the root entry potentially. If we are the last one,
305 * because we hold the globals lock, then there's no way anyone else can
306 * find this and we are the last mapping to it.
307 */
308 bool fini = list_is_empty(&root->ir_ctrls) != 0;
309 mutex_exit(&root->ir_mutex);
310
311 /*
312 * By definition we had the last hold on this root therefore it's safe
313 * for us to have dropped the lock above and do the rest of the cleanup
314 * that's required.
315 */
316 if (fini) {
317 i2c_root_fini(root);
318 }
319 mutex_exit(&i2cnex_minors.im_mutex);
320
321 i2c_ctrl_cleanup(ctrl);
322 return (I2C_CTRL_REG_E_OK);
323 }
324
325 /*
326 * Ask the controller for its various limits and supported ops. An I2C
327 * controller and SMBus controller have optional and required limit properies.
328 *
329 * I2C_PROP_MAX_READ and I2C_PROP_MAX_WRITE:
330 * - required for I2C
331 * - optional for SMBus, queried if an I2C I/O op or I2C SMBus op present.
332 * Defaults to the value of SMBUS_PROP_BLOCK_SIZE.
333 *
334 * SMBUS_PROP_SUP_OPS and SMBUS_PROP_BLOCK_SIZE:
335 * - optional for I2C, but required if an SMBus I/O op specified
336 * - required for SMBus
337 */
338 static i2c_ctrl_reg_error_t
i2c_ctrl_init_limits(i2c_ctrl_t * ctrl)339 i2c_ctrl_init_limits(i2c_ctrl_t *ctrl)
340 {
341 bool smbus = ctrl->ic_type == I2C_CTRL_TYPE_SMBUS;
342 dev_info_t *dip = ctrl->ic_nexus->in_pdip;
343 const smbus_prop_op_t i2c_block = SMBUS_PROP_OP_I2C_WRITE_BLOCK |
344 SMBUS_PROP_OP_I2C_READ_BLOCK;
345
346 if (ctrl->ic_ops->i2c_io_smbus_f != NULL) {
347 i2c_error_t err;
348 uint32_t len = sizeof (uint32_t);
349 if (!i2c_prop_get(ctrl, SMBUS_PROP_SUP_OPS,
350 &ctrl->ic_limit.lim_smbus_ops, &len, &err)) {
351 dev_err(dip, CE_WARN, "failed to get property %s: "
352 "0x%x/0x%x", i2c_prop_name(SMBUS_PROP_SUP_OPS),
353 err.i2c_error, err.i2c_ctrl);
354 return (I2C_CTRL_REG_E_REQ_PROP);
355 }
356
357 VERIFY3U(len, ==, sizeof (uint32_t));
358 if (ctrl->ic_limit.lim_smbus_ops == 0) {
359 dev_err(dip, CE_WARN, "controller cannot specify "
360 "support for no SMBus ops");
361 return (I2C_CTLR_REG_E_BAD_PROP_VAL);
362 }
363
364 len = sizeof (uint32_t);
365 if (!i2c_prop_get(ctrl, SMBUS_PROP_MAX_BLOCK,
366 &ctrl->ic_limit.lim_smbus_block, &len, &err)) {
367 dev_err(dip, CE_WARN, "failed to get property %s: "
368 "0x%x/0x%x", i2c_prop_name(SMBUS_PROP_MAX_BLOCK),
369 err.i2c_error, err.i2c_ctrl);
370 return (I2C_CTRL_REG_E_REQ_PROP);
371 }
372
373 VERIFY3U(len, ==, sizeof (uint32_t));
374 if (ctrl->ic_limit.lim_smbus_block < SMBUS_V2_MAX_BLOCK ||
375 ctrl->ic_limit.lim_smbus_block > SMBUS_V3_MAX_BLOCK) {
376 dev_err(dip, CE_WARN, "unsupported SMBus maximum "
377 "block size: %u", ctrl->ic_limit.lim_smbus_block);
378 return (I2C_CTLR_REG_E_BAD_PROP_VAL);
379 }
380 }
381
382 if (ctrl->ic_ops->i2c_io_i2c_f != NULL ||
383 (ctrl->ic_limit.lim_smbus_ops & i2c_block) != 0) {
384 i2c_error_t err;
385 uint32_t len = sizeof (uint32_t);
386 if (!i2c_prop_get(ctrl, I2C_PROP_MAX_READ,
387 &ctrl->ic_limit.lim_i2c_read, &len, &err)) {
388 if (smbus && err.i2c_error == I2C_PROP_E_UNSUP) {
389 ctrl->ic_limit.lim_i2c_read =
390 ctrl->ic_limit.lim_smbus_block;
391 } else {
392 dev_err(dip, CE_WARN, "failed to get property "
393 "%s: 0x%x/0x%x",
394 i2c_prop_name(I2C_PROP_MAX_READ),
395 err.i2c_error, err.i2c_ctrl);
396 return (I2C_CTRL_REG_E_REQ_PROP);
397 }
398 }
399
400 VERIFY3U(len, ==, sizeof (uint32_t));
401 if (ctrl->ic_limit.lim_i2c_read == 0 ||
402 ctrl->ic_limit.lim_i2c_read > I2C_REQ_MAX) {
403 dev_err(dip, CE_WARN, "unsupported %s value",
404 i2c_prop_name(I2C_PROP_MAX_READ));
405 return (I2C_CTLR_REG_E_BAD_PROP_VAL);
406 }
407
408 len = sizeof (uint32_t);
409 if (!i2c_prop_get(ctrl, I2C_PROP_MAX_WRITE,
410 &ctrl->ic_limit.lim_i2c_write, &len, &err)) {
411 if (smbus && err.i2c_error == I2C_PROP_E_UNSUP) {
412 ctrl->ic_limit.lim_i2c_write =
413 ctrl->ic_limit.lim_smbus_block;
414 } else {
415 dev_err(dip, CE_WARN, "failed to get property "
416 "%s: 0x%x/0x%x",
417 i2c_prop_name(I2C_PROP_MAX_WRITE),
418 err.i2c_error, err.i2c_ctrl);
419 return (I2C_CTRL_REG_E_REQ_PROP);
420 }
421 }
422
423 VERIFY3U(len, ==, sizeof (uint32_t));
424 if (ctrl->ic_limit.lim_i2c_write == 0 ||
425 ctrl->ic_limit.lim_i2c_write > I2C_REQ_MAX) {
426 dev_err(dip, CE_WARN, "unsupported %s value",
427 i2c_prop_name(I2C_PROP_MAX_WRITE));
428 return (I2C_CTLR_REG_E_BAD_PROP_VAL);
429 }
430 }
431
432 return (I2C_CTRL_REG_E_OK);
433 }
434
435 i2c_ctrl_reg_error_t
i2c_ctrl_register(const i2c_ctrl_register_t * reg,i2c_ctrl_hdl_t ** hdlp)436 i2c_ctrl_register(const i2c_ctrl_register_t *reg, i2c_ctrl_hdl_t **hdlp)
437 {
438 i2c_ctrl_t *ctrl;
439 char name[I2C_NAME_MAX];
440 const char *namep;
441
442 if (reg == NULL || hdlp == NULL) {
443 return (I2C_CTRL_REG_E_NULL_ARG);
444 }
445
446 if (reg->ic_vers != I2C_CTRL_PROVIDER_V0) {
447 return (I2C_CTRL_REG_E_BAD_VERS);
448 }
449
450 if (reg->ic_ops == NULL) {
451 return (I2C_CTRL_REG_E_BAD_OPS);
452 }
453
454 if (reg->ic_ops->i2c_port_name_f == NULL) {
455 return (I2C_CTRL_REG_E_NEED_PORT_NAME_FUNC);
456 }
457
458 if (reg->ic_ops->i2c_prop_info_f == NULL) {
459 return (I2C_CTRL_REG_E_NEED_PROP_INFO_FUNC);
460 }
461
462 if (reg->ic_ops->i2c_prop_get_f == NULL) {
463 return (I2C_CTRL_REG_E_NEED_PROP_GET_FUNC);
464 }
465
466 switch (reg->ic_type) {
467 case I2C_CTRL_TYPE_I2C:
468 if (reg->ic_ops->i2c_io_i2c_f == NULL) {
469 return (EINVAL);
470 }
471 break;
472 case I2C_CTRL_TYPE_SMBUS:
473 if (reg->ic_ops->i2c_io_smbus_f == NULL) {
474 return (EINVAL);
475 }
476 break;
477 case I2C_CTRL_TYPE_I3C:
478 return (I2C_CTRL_REG_E_UNSUP_CTRL_TYPE);
479 default:
480 return (I2C_CTRL_REG_E_BAD_CTRL_TYPE);
481 }
482
483 if (reg->ic_dip == NULL) {
484 return (I2C_CTRL_REG_E_BAD_DIP);
485 }
486
487 if (reg->ic_nports == 0 || reg->ic_nports > I2C_MAX_PORTS) {
488 return (I2C_CTRL_REG_E_BAD_NPORTS);
489 }
490
491 if (reg->ic_name != NULL) {
492 size_t len = strnlen(reg->ic_name, I2C_NAME_MAX);
493
494 if (len >= I2C_NAME_MAX) {
495 return (I2C_CTRL_REG_E_BAD_NAME);
496 }
497
498 if (len == 0 || reg->ic_name[len] != '\0') {
499 return (I2C_CTRL_REG_E_BAD_NAME);
500 }
501
502 for (size_t i = 0; i < len; i++) {
503 if (!ISALNUM(reg->ic_name[i])) {
504 return (I2C_CTRL_REG_E_BAD_NAME);
505 }
506 }
507 namep = reg->ic_name;
508 } else {
509 if (snprintf(name, sizeof (name), "%s%d",
510 ddi_driver_name(reg->ic_dip),
511 ddi_get_instance(reg->ic_dip)) >= sizeof (name)) {
512 return (I2C_CTRL_REG_E_INTERNAL);
513 }
514
515 namep = name;
516 }
517
518 if (devopsp[ddi_driver_major(reg->ic_dip)]->devo_bus_ops !=
519 &i2c_nex_ctrl_bus_ops) {
520 return (I2C_CTRL_REG_E_BAD_MOD_TYPE);
521 }
522
523 /*
524 * Now that everything has been validated, attempt to create the
525 * controller and the nexus information.
526 */
527 ctrl = kmem_zalloc(sizeof (i2c_ctrl_t), KM_SLEEP);
528 i2c_ctrl_lock_init(&ctrl->ic_lock);
529 list_create(&ctrl->ic_mux_plan, sizeof (i2c_port_t),
530 offsetof(i2c_port_t, ip_ctrl_link));
531 list_create(&ctrl->ic_mux_active, sizeof (i2c_port_t),
532 offsetof(i2c_port_t, ip_ctrl_link));
533 list_create(&ctrl->ic_txns, sizeof (i2c_txn_t),
534 offsetof(i2c_txn_t, txn_link));
535 mutex_init(&ctrl->ic_txn_lock, NULL, MUTEX_DRIVER, NULL);
536 ctrl->ic_drv = reg->ic_drv;
537 ctrl->ic_ops = reg->ic_ops;
538 ctrl->ic_type = reg->ic_type;
539 ctrl->ic_nexus = i2cnex_nex_alloc(I2C_NEXUS_T_CTRL, reg->ic_dip, NULL,
540 NULL, namep, ctrl);
541 if (ctrl->ic_nexus == NULL) {
542 i2c_ctrl_cleanup(ctrl);
543 return (I2C_CTRL_REG_E_NEXUS);
544 }
545
546 /*
547 * Verify we can get the various limit properties that we expect.
548 */
549 i2c_ctrl_reg_error_t ret = i2c_ctrl_init_limits(ctrl);
550 if (ret != I2C_CTRL_REG_E_OK) {
551 i2c_ctrl_cleanup(ctrl);
552 return (ret);
553 }
554
555 ctrl->ic_nports = reg->ic_nports;
556 i2c_root_t *root = i2c_root_init(reg->ic_dip);
557
558 /*
559 * We currently require global uniqueness for controller names otherwise
560 * userland is going to have a very bad day.
561 */
562 mutex_enter(&root->ir_mutex);
563 for (i2c_ctrl_t *c = list_head(&root->ir_ctrls); c != NULL;
564 c = list_next(&root->ir_ctrls, c)) {
565 if (bcmp(c->ic_nexus->in_addr, ctrl->ic_nexus->in_addr,
566 sizeof (c->ic_nexus->in_addr)) == 0) {
567 i2c_ctrl_cleanup(ctrl);
568 return (I2C_CTRL_REG_E_NOT_UNIQUE);
569 }
570 }
571
572 ctrl->ic_root = root;
573 list_insert_tail(&root->ir_ctrls, ctrl);
574 mutex_exit(&root->ir_mutex);
575
576 *hdlp = (i2c_ctrl_hdl_t *)ctrl;
577 return (0);
578 }
579
580 /*
581 * The timeout count and delay in hertz functions are used to allow controllers
582 * to query values to use. Currently these are just globals in the i2c nexus;
583 * however, we don't want drivers to encode their own and this gives us a future
584 * path where this can be a tunable on a per-controller basis. Right now the
585 * controller arguments are unused, but are here to make it easier to adjust to
586 * that possible future.
587 */
588 uint32_t
i2c_ctrl_timeout_count(i2c_ctrl_hdl_t * hdl,i2c_ctrl_timeout_t to)589 i2c_ctrl_timeout_count(i2c_ctrl_hdl_t *hdl, i2c_ctrl_timeout_t to)
590 {
591 switch (to) {
592 case I2C_CTRL_TO_IO:
593 return (i2c_ctrl_to_io_count);
594 case I2C_CTRL_TO_ABORT:
595 return (i2c_ctrl_to_abort_count);
596 case I2C_CTRL_TO_POLL_CTRL:
597 return (i2c_ctrl_to_poll_ctrl_count);
598 case I2C_CTRL_TO_BUS_ACT:
599 return (i2c_ctrl_to_bus_act_count);
600 default:
601 panic("programmer error: requested invalid timeout 0x%x", to);
602 }
603 }
604
605 uint32_t
i2c_ctrl_timeout_delay_us(i2c_ctrl_hdl_t * hdl,i2c_ctrl_timeout_t to)606 i2c_ctrl_timeout_delay_us(i2c_ctrl_hdl_t *hdl, i2c_ctrl_timeout_t to)
607 {
608 switch (to) {
609 case I2C_CTRL_TO_IO:
610 return (i2c_ctrl_to_io_delay_us);
611 case I2C_CTRL_TO_ABORT:
612 return (i2c_ctrl_to_abort_delay_us);
613 case I2C_CTRL_TO_POLL_CTRL:
614 return (i2c_ctrl_to_poll_ctrl_delay_us);
615 case I2C_CTRL_TO_BUS_ACT:
616 return (i2c_ctrl_to_bus_act_delay_us);
617 default:
618 panic("programmer error: requested invalid timeout 0x%x", to);
619 }
620 }
621
622 /*
623 * Translate a write-only request. We try to stick to SMBus 2.0 class requests
624 * for the time being that we expect most devices to be able to implement. For
625 * pure writes we can write up to the SMBus 2.0 max request size plus 1 bytes.
626 * In other words 33. Requests of up to 3 bytes will use the standard operations
627 * while others will need to use the I2C block write operation.
628 */
629 static bool
i2c_ctrl_io_i2c_xlate_wo(i2c_ctrl_t * ctrl,const i2c_req_t * req,smbus_req_t * smbus)630 i2c_ctrl_io_i2c_xlate_wo(i2c_ctrl_t *ctrl, const i2c_req_t *req,
631 smbus_req_t *smbus)
632 {
633 if (req->ir_wlen == 1) {
634 smbus->smbr_op = SMBUS_OP_SEND_BYTE;
635 smbus->smbr_wdata[0] = req->ir_wdata[0];
636 return (true);
637 }
638
639 if (req->ir_wlen == 2) {
640 smbus->smbr_op = SMBUS_OP_WRITE_BYTE;
641 smbus->smbr_cmd = req->ir_wdata[0];
642 smbus->smbr_wdata[0] = req->ir_wdata[1];
643 return (true);
644 }
645
646 if (req->ir_wlen == 3) {
647 smbus->smbr_op = SMBUS_OP_WRITE_WORD;
648 smbus->smbr_cmd = req->ir_wdata[0];
649 smbus->smbr_wdata[0] = req->ir_wdata[1];
650 smbus->smbr_wdata[1] = req->ir_wdata[2];
651 return (true);
652 }
653
654 /*
655 * The SMBus controller maximum block size does not include the command
656 * code that is sent, hence the +1 below.
657 */
658 if (req->ir_wlen > ctrl->ic_limit.lim_smbus_block + 1) {
659 return (false);
660 }
661
662 smbus->smbr_op = SMBUS_OP_I2C_WRITE_BLOCK;
663 smbus->smbr_cmd = req->ir_wdata[0];
664 bcopy(req->ir_wdata + 1, smbus->smbr_wdata, req->ir_wlen - 1);
665 return (true);
666 }
667
668 /*
669 * The only read-only request that doesn't require a repeated start for SMBus is
670 * a single byte read. All other reads want to write a command in the form of a
671 * repeated start. Sorry I2C.
672 */
673 static bool
i2c_ctrl_io_i2c_xlate_ro(const i2c_req_t * req,smbus_req_t * smbus)674 i2c_ctrl_io_i2c_xlate_ro(const i2c_req_t *req, smbus_req_t *smbus)
675 {
676 if (req->ir_rlen == 1) {
677 smbus->smbr_op = SMBUS_OP_RECV_BYTE;
678 return (true);
679 }
680
681 return (false);
682 }
683
684 /*
685 * We have a mixed read/write request. There are still limitations here. We can
686 * easily translate a single byte write into an SMBus command code, allowing us
687 * to get a wide variety of read lengths here. However, if we are writing more
688 * than one byte, then need to perform a fixed size read, the only way we can do
689 * that is with a procedure call which requires a three byte write to do a two
690 * byte read.
691 */
692 static bool
i2c_ctrl_io_i2c_xlate_rw(i2c_ctrl_t * ctrl,const i2c_req_t * req,smbus_req_t * smbus)693 i2c_ctrl_io_i2c_xlate_rw(i2c_ctrl_t *ctrl, const i2c_req_t *req,
694 smbus_req_t *smbus)
695 {
696 if (req->ir_wlen == 3 && req->ir_rlen == 2) {
697 smbus->smbr_op = SMBUS_OP_PROCESS_CALL;
698 smbus->smbr_cmd = req->ir_wdata[0];
699 smbus->smbr_wdata[0] = req->ir_wdata[1];
700 smbus->smbr_wdata[1] = req->ir_wdata[2];
701 } else if (req->ir_wlen != 1) {
702 return (false);
703 }
704
705 smbus->smbr_cmd = req->ir_wdata[0];
706 if (req->ir_rlen == 1) {
707 smbus->smbr_op = SMBUS_OP_READ_BYTE;
708 return (true);
709 }
710
711 if (req->ir_rlen == 2) {
712 smbus->smbr_op = SMBUS_OP_READ_WORD;
713 return (true);
714 }
715
716 if (req->ir_rlen > ctrl->ic_limit.lim_smbus_block) {
717 return (false);
718 }
719
720 smbus->smbr_op = SMBUS_OP_I2C_READ_BLOCK;
721 smbus->smbr_rlen = req->ir_rlen;
722 return (true);
723 }
724
725 static bool
i2c_ctrl_io_i2c_xlate(i2c_txn_t * txn,i2c_ctrl_t * ctrl,i2c_port_t * port,i2c_req_t * req)726 i2c_ctrl_io_i2c_xlate(i2c_txn_t *txn, i2c_ctrl_t *ctrl, i2c_port_t *port,
727 i2c_req_t *req)
728 {
729 smbus_req_t *smbus = &ctrl->ic_reqs.req_smbus;
730
731 bzero(smbus, sizeof (smbus_req_t));
732 smbus->smbr_addr = req->ir_addr;
733 smbus->smbr_flags = req->ir_flags;
734
735 /*
736 * First look at write-only requests, then read-only requests.
737 */
738 if (req->ir_rlen == 0 && req->ir_wlen == 0) {
739 goto xlate_fail;
740 }
741
742 if (req->ir_rlen == 0) {
743 if (!i2c_ctrl_io_i2c_xlate_wo(ctrl, req, smbus))
744 goto xlate_fail;
745 } else if (req->ir_wlen == 0) {
746 if (!i2c_ctrl_io_i2c_xlate_ro(req, smbus))
747 goto xlate_fail;
748 } else {
749 if (!i2c_ctrl_io_i2c_xlate_rw(ctrl, req, smbus))
750 goto xlate_fail;
751 }
752
753 bool ret = i2c_ctrl_io_smbus(txn, ctrl, port, smbus);
754 req->ir_error = smbus->smbr_error;
755 bcopy(smbus->smbr_rdata, req->ir_rdata, sizeof (smbus->smbr_rdata));
756
757 return (ret);
758
759 xlate_fail:
760 /*
761 * Ultimately, we couldn't translate this command. The world of I2C is
762 * much richer than the world of SMBus.
763 */
764 i2c_ctrl_io_error(&req->ir_error, I2C_CORE_E_CANT_XLATE_REQ, 0);
765 return (false);
766 }
767
768 bool
i2c_ctrl_io_i2c(i2c_txn_t * txn,i2c_ctrl_t * ctrl,i2c_port_t * port,i2c_req_t * req)769 i2c_ctrl_io_i2c(i2c_txn_t *txn, i2c_ctrl_t *ctrl, i2c_port_t *port,
770 i2c_req_t *req)
771 {
772 VERIFY(i2c_txn_held(txn));
773 VERIFY3P(txn->txn_ctrl, ==, ctrl);
774
775 if (ctrl->ic_ops->i2c_io_i2c_f == NULL) {
776 return (i2c_ctrl_io_i2c_xlate(txn, ctrl, port, req));
777 }
778
779 /*
780 * Verify that muxes are set up as required to do I/O to this port.
781 */
782 if (!i2c_mux_update(txn, ctrl, port, &req->ir_error)) {
783 return (false);
784 }
785
786 req->ir_error.i2c_error = INT32_MAX;
787 req->ir_error.i2c_ctrl = INT32_MAX;
788
789 /*
790 * At this point, go ahead and perform the actual I/O request via the
791 * controller.
792 */
793 const i2c_port_t *ctrl_port = list_head(&ctrl->ic_mux_active);
794 VERIFY3P(ctrl_port, !=, NULL);
795 ctrl->ic_ops->i2c_io_i2c_f(ctrl->ic_drv, ctrl_port->ip_portno, req);
796
797 if (req->ir_error.i2c_error == INT32_MAX ||
798 req->ir_error.i2c_ctrl == INT32_MAX) {
799 dev_err(ctrl->ic_nexus->in_pdip, CE_WARN, "controller "
800 "failed to properly set error information");
801 req->ir_error.i2c_error = I2C_CORE_E_CONTROLLER;
802 req->ir_error.i2c_ctrl = I2C_CTRL_E_DRIVER;
803 }
804
805 return (req->ir_error.i2c_error == I2C_CORE_E_OK);
806 }
807
808 /*
809 * Translate I/O into an I2C request and then back into the corresponding
810 * results for SMBus. Most of these are straightforward. Unfortunately, the
811 * variable size requests require controller support and we don't handle them
812 * right now.
813 */
814 static bool
i2c_ctrl_io_smbus_xlate(i2c_txn_t * txn,i2c_ctrl_t * ctrl,i2c_port_t * port,smbus_req_t * req)815 i2c_ctrl_io_smbus_xlate(i2c_txn_t *txn, i2c_ctrl_t *ctrl, i2c_port_t *port,
816 smbus_req_t *req)
817 {
818 i2c_req_t *i2c = &ctrl->ic_reqs.req_i2c;
819
820 bzero(i2c, sizeof (i2c_req_t));
821
822 i2c->ir_addr = req->smbr_addr;
823 i2c->ir_flags = req->smbr_flags;
824
825 switch (req->smbr_op) {
826 case SMBUS_OP_SEND_BYTE:
827 i2c->ir_wlen = 1;
828 i2c->ir_wdata[0] = req->smbr_wdata[0];
829 break;
830 case SMBUS_OP_WRITE_BYTE:
831 i2c->ir_wlen = 2;
832 i2c->ir_wdata[0] = req->smbr_cmd;
833 i2c->ir_wdata[1] = req->smbr_wdata[0];
834 break;
835 case SMBUS_OP_WRITE_WORD:
836 i2c->ir_wlen = 3;
837 i2c->ir_wdata[0] = req->smbr_cmd;
838 i2c->ir_wdata[1] = req->smbr_wdata[0];
839 i2c->ir_wdata[2] = req->smbr_wdata[1];
840 break;
841 case SMBUS_OP_WRITE_U32:
842 i2c->ir_wlen = 5;
843 i2c->ir_wdata[0] = req->smbr_cmd;
844 i2c->ir_wdata[1] = req->smbr_wdata[0];
845 i2c->ir_wdata[2] = req->smbr_wdata[1];
846 i2c->ir_wdata[3] = req->smbr_wdata[2];
847 i2c->ir_wdata[4] = req->smbr_wdata[3];
848 break;
849 case SMBUS_OP_WRITE_U64:
850 i2c->ir_wlen = 9;
851 i2c->ir_wdata[0] = req->smbr_cmd;
852 i2c->ir_wdata[1] = req->smbr_wdata[0];
853 i2c->ir_wdata[2] = req->smbr_wdata[1];
854 i2c->ir_wdata[3] = req->smbr_wdata[2];
855 i2c->ir_wdata[4] = req->smbr_wdata[3];
856 i2c->ir_wdata[5] = req->smbr_wdata[4];
857 i2c->ir_wdata[6] = req->smbr_wdata[5];
858 i2c->ir_wdata[7] = req->smbr_wdata[6];
859 i2c->ir_wdata[8] = req->smbr_wdata[7];
860 break;
861 case SMBUS_OP_RECV_BYTE:
862 i2c->ir_rlen = 1;
863 break;
864 case SMBUS_OP_READ_BYTE:
865 i2c->ir_wlen = 1;
866 i2c->ir_wdata[0] = req->smbr_cmd;
867 i2c->ir_rlen = sizeof (uint8_t);
868 break;
869 case SMBUS_OP_READ_WORD:
870 i2c->ir_wlen = 1;
871 i2c->ir_wdata[0] = req->smbr_cmd;
872 i2c->ir_rlen = sizeof (uint16_t);
873 break;
874 case SMBUS_OP_READ_U32:
875 i2c->ir_wlen = 1;
876 i2c->ir_wdata[0] = req->smbr_cmd;
877 i2c->ir_rlen = sizeof (uint32_t);
878 break;
879 case SMBUS_OP_READ_U64:
880 i2c->ir_wlen = 1;
881 i2c->ir_wdata[0] = req->smbr_cmd;
882 i2c->ir_rlen = sizeof (uint64_t);
883 break;
884 case SMBUS_OP_PROCESS_CALL:
885 i2c->ir_wlen = 3;
886 i2c->ir_wdata[0] = req->smbr_cmd;
887 i2c->ir_wdata[1] = req->smbr_wdata[0];
888 i2c->ir_wdata[2] = req->smbr_wdata[1];
889 i2c->ir_rlen = sizeof (uint16_t);
890 break;
891 case SMBUS_OP_WRITE_BLOCK:
892 /*
893 * If we don't have space for this, the command code, and length
894 * then we're in trouble.
895 */
896 if (req->smbr_wlen + 2 > ctrl->ic_limit.lim_i2c_write) {
897 i2c_ctrl_io_error(&req->smbr_error,
898 I2C_CORE_E_CANT_XLATE_REQ, 0);
899 return (false);
900 }
901
902 i2c->ir_wlen = req->smbr_wlen + 2;
903 i2c->ir_wdata[0] = req->smbr_cmd;
904 i2c->ir_wdata[1] = req->smbr_wlen;
905 bcopy(req->smbr_wdata, i2c->ir_wdata + 2, req->smbr_wlen);
906 break;
907 case SMBUS_OP_I2C_WRITE_BLOCK:
908 if (req->smbr_wlen + 1 > ctrl->ic_limit.lim_i2c_write) {
909 i2c_ctrl_io_error(&req->smbr_error,
910 I2C_CORE_E_CANT_XLATE_REQ, 0);
911 return (false);
912 }
913
914 i2c->ir_wlen = req->smbr_wlen + 1;
915 i2c->ir_wdata[0] = req->smbr_cmd;
916 bcopy(req->smbr_wdata, i2c->ir_wdata + 1, req->smbr_wlen);
917 break;
918 case SMBUS_OP_I2C_READ_BLOCK:
919 i2c->ir_wlen = 1;
920 i2c->ir_wdata[0] = req->smbr_cmd;
921 i2c->ir_rlen = req->smbr_rlen;
922 break;
923 /*
924 * Host notify is not supported here. While it is a valid operation, it
925 * is not meant for the controller to issue.
926 */
927 case SMBUS_OP_HOST_NOTIFY:
928 i2c_ctrl_io_error(&req->smbr_error,
929 I2C_CORE_E_UNSUP_SMBUS_OP, 0);
930 return (false);
931 /*
932 * The block reads require the ability to usefully describe how to get
933 * variable length operations to controllers. We can add this emulation
934 * when required, but for now do not.
935 */
936 case SMBUS_OP_READ_BLOCK:
937 case SMBUS_OP_BLOCK_PROCESS_CALL:
938 i2c_ctrl_io_error(&req->smbr_error,
939 I2C_CORE_E_CANT_XLATE_REQ, 0);
940 return (false);
941 /*
942 * We should be able to translate a quick command. However, the main
943 * problem is that right now we don't have a good way of indicating
944 * read vs. write in the controller API for a zero-byte I/O in the
945 * controller API where we indicate the direction. This is something
946 * that should be remedied.
947 */
948 case SMBUS_OP_QUICK_COMMAND:
949 default:
950 i2c_ctrl_io_error(&req->smbr_error,
951 I2C_CORE_E_CANT_XLATE_REQ, 0);
952 return (false);
953 }
954
955 /*
956 * Copy error and data information back unconditionally. When we support
957 * variable length block I/O then we will need to update smbr_rlen with
958 * the actual length.
959 */
960 bool ret = i2c_ctrl_io_i2c(txn, ctrl, port, i2c);
961 req->smbr_error = i2c->ir_error;
962 bcopy(i2c->ir_rdata, req->smbr_rdata, sizeof (i2c->ir_rdata));
963
964 return (ret);
965 }
966
967 /*
968 * Submit SMBus-style I/O, translating it as required into an I2C-specific
969 * operation.
970 */
971 bool
i2c_ctrl_io_smbus(i2c_txn_t * txn,i2c_ctrl_t * ctrl,i2c_port_t * port,smbus_req_t * req)972 i2c_ctrl_io_smbus(i2c_txn_t *txn, i2c_ctrl_t *ctrl, i2c_port_t *port,
973 smbus_req_t *req)
974 {
975 VERIFY(i2c_txn_held(txn));
976 VERIFY3P(txn->txn_ctrl, ==, ctrl);
977
978 if (ctrl->ic_ops->i2c_io_smbus_f == NULL) {
979 VERIFY3P(ctrl->ic_ops->i2c_io_i2c_f, !=, NULL);
980 return (i2c_ctrl_io_smbus_xlate(txn, ctrl, port, req));
981 }
982
983 /*
984 * Verify that the requested operation is actually supported. If it is
985 * not, see if we can perform an I2C translation operation. Otherwise,
986 * there's nothing more for us to do.
987 */
988 if ((ctrl->ic_limit.lim_smbus_ops & (1 << req->smbr_op)) == 0) {
989 if (ctrl->ic_ops->i2c_io_i2c_f != NULL) {
990 return (i2c_ctrl_io_smbus_xlate(txn, ctrl, port, req));
991 }
992 i2c_ctrl_io_error(&req->smbr_error, I2C_CORE_E_CONTROLLER,
993 I2C_CTRL_E_UNSUP_CMD);
994 return (false);
995 }
996
997 /*
998 * Verify that muxes are set up as required to do I/O to this port.
999 */
1000 if (!i2c_mux_update(txn, ctrl, port, &req->smbr_error)) {
1001 return (false);
1002 }
1003
1004 req->smbr_error.i2c_error = INT32_MAX;
1005 req->smbr_error.i2c_ctrl = INT32_MAX;
1006
1007 /*
1008 * At this point, go ahead and perform the actual I/O request via the
1009 * controller.
1010 */
1011 const i2c_port_t *ctrl_port = list_head(&ctrl->ic_mux_active);
1012 VERIFY3P(ctrl_port, !=, NULL);
1013 ctrl->ic_ops->i2c_io_smbus_f(ctrl->ic_drv, ctrl_port->ip_portno, req);
1014
1015 if (req->smbr_error.i2c_error == INT32_MAX ||
1016 req->smbr_error.i2c_ctrl == INT32_MAX) {
1017 dev_err(ctrl->ic_nexus->in_pdip, CE_WARN, "controller "
1018 "failed to properly set error information");
1019 req->smbr_error.i2c_error = I2C_CORE_E_CONTROLLER;
1020 req->smbr_error.i2c_ctrl = I2C_CTRL_E_DRIVER;
1021 }
1022
1023 return (req->smbr_error.i2c_error == I2C_CORE_E_OK);
1024 }
1025
1026 bool
i2c_ctrl_port_name_portno(void * arg,uint32_t port,char * buf,size_t buflen)1027 i2c_ctrl_port_name_portno(void *arg, uint32_t port, char *buf, size_t buflen)
1028 {
1029 return (snprintf(buf, buflen, "%u", port) < sizeof (buf));
1030 }
1031