1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2025 Oxide Computer Company
14 */
15
16 /*
17 * I2C logic for client device drivers.
18 *
19 * This file contains all of the logic around I2C client functions that device
20 * drivers use to access an I2C bus. Today, access to an address is based on
21 * either the reg[] handle or allowing a device to access an address at the same
22 * spot in the tree as their device to handle muxing. Let's talk about the
23 * various abstractions that exist.
24 *
25 * ------------
26 * i2c_client_t
27 * ------------
28 *
29 * This i2c_client_t represents the information to talk to a given device at a
30 * specified address. It is assumed that an instance of a driver will create one
31 * of these per thing it needs to talk to and it will use it across multiple
32 * threads. In general, we want to keep the simple case simple for I2C drivers
33 * where by they don't have to think too much about locking of the client or
34 * related unless they need to perform different transactions coherently or they
35 * have something special going on where there are global side effects like the
36 * ee1004 driver where everyone is listening for the same address to determine
37 * which page is active.
38 *
39 * Because the i2c_client_t can be used by multiple threads in the driver in
40 * parallel, we generally treat access to the data that we cache in the
41 * i2c_client_t as being protected by and requiring the caller to hold the
42 * active i2c transaction represented by the i2c_txn_t. We do not require
43 * callers to have one before coming into here. We will get one on their
44 * behalf.
45 *
46 * An important aspect here is that everything is subordinate to holding the
47 * active transaction. This ensures that we honor lock ordering and avoid
48 * deadlock situations. Only once that is owned can one use the request
49 * structures embedded in the i2c_client_t. They are here to minimize run-time
50 * allocations.
51 *
52 * ----------------
53 * i2c_reg_handle_t
54 * ----------------
55 *
56 * The i2c_reg_handle_t is used as a convenient way to access data on an i2c
57 * device as many devices are ultimately phrased in terms of registers. The goal
58 * was to provide something that is similar to ddi_regs_map_setup(), but is
59 * phrased in terms of fallible I/O. Trying to squeeze this in and have drivers
60 * check results did not seem very practical where as for many other buses those
61 * transactions take the form of posted I/O and so are more reasonably phrased
62 * that way.
63 *
64 * The register handle is tied to the client and mostly contains metadata along
65 * with buffers that are used to make requests. In a similar fashion to the
66 * i2c_client_t, one is required to have an active transaction before accessing
67 * those. This means that the i2c_reg_handle_t is mostly the same as the
68 * i2c_client_t with respect to locking and access.
69 */
70
71 #include <sys/ddi.h>
72 #include <sys/sunddi.h>
73 #include <sys/bitext.h>
74 #include <sys/thread.h>
75 #include <sys/stddef.h>
76
77 #include "i2cnex.h"
78
79 /*
80 * This includes all possible i2c_errno_t translations. We'd rather just
81 * translate everything and give folks something potentially useful than get it
82 * wrong.
83 */
84 const char *
i2c_client_errtostr(i2c_client_t * client,i2c_errno_t errno)85 i2c_client_errtostr(i2c_client_t *client, i2c_errno_t errno)
86 {
87 switch (errno) {
88 case I2C_CORE_E_OK:
89 return ("I2C_CORE_E_OK");
90 case I2C_CORE_E_CONTROLLER:
91 return ("I2C_CORE_E_CONTROLLER");
92 case I2C_CORE_E_BAD_ADDR_TYPE:
93 return ("I2C_CORE_E_BAD_ADDR_TYPE");
94 case I2C_CORE_E_BAD_ADDR:
95 return ("I2C_CORE_E_BAD_ADDR");
96 case I2C_CORE_E_UNSUP_ADDR_TYPE:
97 return ("I2C_CORE_E_UNSUP_ADDR_TYPE");
98 case I2C_CORE_E_ADDR_RSVD:
99 return ("I2C_CORE_E_ADDR_RSVD");
100 case I2C_CORE_E_ADDR_IN_USE:
101 return ("I2C_CORE_E_ADDR_IN_USE");
102 case I2C_CORE_E_ADDR_REFCNT:
103 return ("I2C_CORE_E_ADDR_REFCNT");
104 case I2C_CORE_E_UNKNOWN_ADDR:
105 return ("I2C_CORE_E_UNKNOWN_ADDR");
106 case I2C_CORE_E_CANT_XLATE_REQ:
107 return ("I2C_CORE_E_CANT_XLATE_REQ");
108 case I2C_CORE_E_NEED_READ_OR_WRITE:
109 return ("I2C_CORE_E_NEED_READ_OR_WRITE");
110 case I2C_CORE_E_BAD_I2C_REQ_FLAGS:
111 return ("I2C_CORE_E_BAD_I2C_REQ_FLAGS");
112 case I2C_CORE_E_BAD_I2C_REQ_READ_LEN:
113 return ("I2C_CORE_E_BAD_I2C_REQ_READ_LEN");
114 case I2C_CORE_E_BAD_I2C_REQ_WRITE_LEN:
115 return ("I2C_CORE_E_BAD_I2C_REQ_WRITE_LEN");
116 case I2C_CORE_E_BAD_SMBUS_REQ_FLAGS:
117 return ("I2C_CORE_E_BAD_SMBUS_REQ_FLAGS");
118 case I2C_CORE_E_BAD_SMBUS_READ_LEN:
119 return ("I2C_CORE_E_BAD_SMBUS_READ_LEN");
120 case I2C_CORE_E_BAD_SMBUS_WRITE_LEN:
121 return ("I2C_CORE_E_BAD_SMBUS_WRITE_LEN");
122 case I2C_CORE_E_BAD_SMBUS_OP:
123 return ("I2C_CORE_E_BAD_SMBUS_OP");
124 case I2C_CORE_E_UNSUP_SMBUS_OP:
125 return ("I2C_CORE_E_UNSUP_SMBUS_OP");
126 case I2C_CORE_E_LOCK_WOULD_BLOCK:
127 return ("I2C_CORE_E_LOCK_WOULD_BLOCK");
128 case I2C_CORE_E_LOCK_WAIT_SIGNAL:
129 return ("I2C_CORE_E_LOCK_WAIT_SIGNAL");
130 case I2C_IOCTL_E_NVL_TOO_BIG:
131 return ("I2C_IOCTL_E_NVL_TOO_BIG");
132 case I2C_IOCTL_E_NVL_INVALID:
133 return ("I2C_IOCTL_E_NVL_INVALID");
134 case I2C_IOCTL_E_NVL_KEY_MISSING:
135 return ("I2C_IOCTL_E_NVL_KEY_MISSING");
136 case I2C_IOCTL_E_NVL_KEY_UNKNOWN:
137 return ("I2C_IOCTL_E_NVL_KEY_UNKNOWN");
138 case I2C_IOCTL_E_NVL_KEY_BAD_TYPE:
139 return ("I2C_IOCTL_E_NVL_KEY_BAD_TYPE");
140 case I2C_IOCTL_E_BAD_USER_DATA:
141 return ("I2C_IOCTL_E_BAD_USER_DATA");
142 case I2C_IOCTL_E_NO_KERN_MEM:
143 return ("I2C_IOCTL_E_NO_KERN_MEM");
144 case I2C_IOCTL_E_BAD_DEV_NAME:
145 return ("I2C_IOCTL_E_BAD_DEV_NAME");
146 case I2C_IOCTL_E_COMPAT_LEN_RANGE:
147 return ("I2C_IOCTL_E_COMPAT_LEN_RANGE");
148 case I2C_IOCTL_E_NEXUS:
149 return ("I2C_IOCTL_E_NEXUS");
150 case I2C_IOCTL_E_NO_BUS_LOCK_NEXUS:
151 return ("I2C_IOCTL_E_NO_BUS_LOCK_NEXUS");
152 case I2C_IOCTL_E_IN_PROGRESS:
153 return ("I2C_IOCTL_E_IN_PROGRESS");
154 case I2C_CLIENT_E_BAD_DIP:
155 return ("I2C_CLIENT_E_BAD_DIP");
156 case I2C_CLIENT_E_BAD_REG_IDX:
157 return ("I2C_CLIENT_E_BAD_REG_IDX");
158 case I2C_CLIENT_E_BAD_CLAIM_FLAGS:
159 return ("I2C_CLIENT_E_BAD_CLAIM_FLAGS");
160 case I2C_CLIENT_E_BAD_IO_FLAGS:
161 return ("I2C_CLIENT_E_BAD_IO_FLAGS");
162 case I2C_CLIENT_E_BAD_LOCK_FLAGS:
163 return ("I2C_CLIENT_E_BAD_LOCK_FLAGS");
164 case I2C_CLIENT_E_SIGNAL:
165 return ("I2C_CLIENT_E_SIGNAL");
166 case I2C_CLIENT_E_BAD_REG_ATTR_VERS:
167 return ("I2C_CLIENT_E_BAD_REG_ATTR_VERS");
168 case I2C_CLIENT_E_BAD_REG_ATTR_FLAGS:
169 return ("I2C_CLIENT_E_BAD_REG_ATTR_FLAGS");
170 case I2C_CLIENT_E_BAD_REG_ATTR_RLEN:
171 return ("I2C_CLIENT_E_BAD_REG_ATTR_RLEN");
172 case I2C_CLIENT_E_BAD_REG_ATTR_ALEN:
173 return ("I2C_CLIENT_E_BAD_REG_ATTR_ALEN");
174 case I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN:
175 return ("I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN");
176 case I2C_CLIENT_E_BAD_REG_ATTR_MAX:
177 return ("I2C_CLIENT_E_BAD_REG_ATTR_MAX");
178 case I2C_CLIENT_E_REG_ALEN_UNSUP_BY_CTRL:
179 return ("I2C_CLIENT_E_REG_ALEN_UNSUP_BY_CTRL");
180 case I2C_CLIENT_E_BAD_REG_ADDR:
181 return ("I2C_CLIENT_E_BAD_REG_ADDR");
182 case I2C_CLIENT_E_BAD_REG_COUNT:
183 return ("I2C_CLIENT_E_BAD_REG_COUNT");
184 case I2C_CLIENT_E_REG_ADDR_OVERFLOW:
185 return ("I2C_CLIENT_E_REG_ADDR_OVERFLOW");
186 case I2C_CLIENT_E_REG_IO_TOO_LARGE:
187 return ("I2C_CLIENT_E_REG_IO_TOO_LARGE");
188 case I2C_CLIENT_E_PARTIAL_REG:
189 return ("I2C_CLIENT_E_PARTIAL_REG");
190 case I2C_CLIENT_E_CLAIM_OWNED_ADDR:
191 return ("I2C_CLIENT_E_CLAIM_OWNED_ADDR");
192 case I2C_PROP_E_UNSUP:
193 return ("I2C_PROP_E_UNSUP");
194 case I2C_PROP_E_UNKNOWN:
195 return ("I2C_PROP_E_UNKNOWN");
196 case I2C_PROP_E_READ_ONLY:
197 return ("I2C_PROP_E_READ_ONLY");
198 case I2C_PROP_E_SMALL_BUF:
199 return ("I2C_PROP_E_SMALL_BUF");
200 case I2C_PROP_E_TOO_BIG_BUF:
201 return ("I2C_PROP_E_TOO_BIG_BUF");
202 case I2C_PROP_E_BAD_VAL:
203 return ("I2C_PROP_E_BAD_VAL");
204 case I2C_PROP_E_SET_UNSUP:
205 return ("I2C_PROP_E_SET_UNSUP");
206 case I2C_MUX_E_BAD_FLAG:
207 return ("I2C_MUX_E_BAD_FLAG");
208 default:
209 return ("unknown error");
210 }
211 }
212
213 const char *
i2c_client_ctrl_errtostr(i2c_client_t * client,i2c_ctrl_error_t errno)214 i2c_client_ctrl_errtostr(i2c_client_t *client, i2c_ctrl_error_t errno)
215 {
216 switch (errno) {
217 case I2C_CTRL_E_OK:
218 return ("I2C_CTRL_E_OK");
219 case I2C_CTRL_E_INTERNAL:
220 return ("I2C_CTRL_E_INTERNAL");
221 case I2C_CTRL_E_DRIVER:
222 return ("I2C_CTRL_E_DRIVER");
223 case I2C_CTRL_E_UNSUP_CMD:
224 return ("I2C_CTRL_E_UNSUP_CMD");
225 case I2C_CTRL_E_BUS_BUSY:
226 return ("I2C_CTRL_E_BUS_BUSY");
227 case I2C_CTRL_E_ADDR_NACK:
228 return ("I2C_CTRL_E_ADDR_NACK");
229 case I2C_CTRL_E_DATA_NACK:
230 return ("I2C_CTRL_E_DATA_NACK");
231 case I2C_CTRL_E_NACK:
232 return ("I2C_CTRL_E_NACK");
233 case I2C_CTRL_E_ARB_LOST:
234 return ("I2C_CTRL_E_ARB_LOST");
235 case I2C_CTRL_E_BAD_ACK:
236 return ("I2C_CTRL_E_BAD_ACK");
237 case I2C_CTRL_E_REQ_TO:
238 return ("I2C_CTRL_E_REQ_TO");
239 case I2C_CTRL_E_BAD_SMBUS_RLEN:
240 return ("I2C_CTRL_E_BAD_SMBUS_RLEN");
241 case I2C_CTRL_E_SMBUS_CLOCK_LOW:
242 return ("I2C_CTRL_E_SMBUS_CLOCK_LOW");
243 default:
244 return ("unknown error");
245 }
246 }
247
248 static i2c_errno_t
i2c_client_bus_lock(i2c_ctrl_t * ctrl,i2c_txn_tag_t tag,const void * arg,bool block,i2c_txn_t ** txnp)249 i2c_client_bus_lock(i2c_ctrl_t *ctrl, i2c_txn_tag_t tag, const void *arg,
250 bool block, i2c_txn_t **txnp)
251 {
252 i2c_txn_t *txn;
253 i2c_errno_t err;
254
255 txn = i2c_txn_alloc(ctrl, tag, arg);
256 err = i2c_txn_ctrl_lock(txn, block);
257 if (err != I2C_CORE_E_OK) {
258 i2c_txn_free(txn);
259 return (err);
260 }
261
262 *txnp = txn;
263 return (I2C_CORE_E_OK);
264
265 }
266
267 void
i2c_client_destroy(i2c_client_t * client)268 i2c_client_destroy(i2c_client_t *client)
269 {
270 i2c_txn_t *txn;
271
272 if (client == NULL)
273 return;
274
275 VERIFY3P(client->icli_txn, ==, NULL);
276 VERIFY3U(client->icli_curthread, ==, 0);
277
278 VERIFY3U(i2c_bus_lock(client, 0, &txn), ==, I2C_CORE_E_OK);
279 list_remove(&client->icli_dev->id_clients, client);
280
281 if ((client->icli_flags & I2C_CLIENT_F_CLAIM_ADDR) != 0) {
282 i2c_nexus_t *nex = client->icli_dev->id_nex;
283 i2c_port_t *port = nex->in_pnex->in_data.in_port;
284 if ((client->icli_flags & I2C_CLIENT_F_SHARED_ADDR) != 0) {
285 i2c_addr_free_shared(port, &client->icli_addr,
286 ddi_driver_major(client->icli_dip));
287 client->icli_flags &= ~I2C_CLIENT_F_SHARED_ADDR;
288 } else {
289 i2c_addr_free(port, &client->icli_addr);
290 }
291 client->icli_flags &= ~I2C_CLIENT_F_CLAIM_ADDR;
292 }
293 i2c_bus_unlock(txn);
294
295 VERIFY3U(list_is_empty(&client->icli_regs), !=, 0);
296
297 list_destroy(&client->icli_regs);
298 mutex_destroy(&client->icli_mutex);
299 kmem_free(client, sizeof (i2c_client_t));
300 }
301
302 static i2c_client_t *
i2c_client_alloc(i2c_txn_t * txn,i2c_dev_t * dev,dev_info_t * dip,const i2c_addr_t * addr)303 i2c_client_alloc(i2c_txn_t *txn, i2c_dev_t *dev, dev_info_t *dip,
304 const i2c_addr_t *addr)
305 {
306 i2c_client_t *client;
307
308 VERIFY(i2c_txn_held(txn));
309
310 client = kmem_zalloc(sizeof (i2c_client_t), KM_SLEEP);
311 client->icli_dip = dip;
312 client->icli_addr = *addr;
313 client->icli_dev = dev;
314 client->icli_ctrl = dev->id_nex->in_ctrl;
315 VERIFY3P(dev->id_nex->in_pnex->in_type, ==, I2C_NEXUS_T_PORT);
316 client->icli_io_port = dev->id_nex->in_pnex->in_data.in_port;
317 mutex_init(&client->icli_mutex, NULL, MUTEX_DRIVER, NULL);
318 list_create(&client->icli_regs, sizeof (i2c_reg_hdl_t),
319 offsetof(i2c_reg_hdl_t, reg_link));
320 list_insert_tail(&dev->id_clients, client);
321
322 return (client);
323 }
324
325 i2c_errno_t
i2c_client_init(dev_info_t * dip,uint32_t regno,i2c_client_t ** clientp)326 i2c_client_init(dev_info_t *dip, uint32_t regno, i2c_client_t **clientp)
327 {
328 int *reg;
329 uint_t nreg;
330 i2c_addr_t addr;
331 i2c_error_t err;
332 i2c_txn_t *txn;
333
334 if (!i2c_dip_is_dev(dip)) {
335 return (I2C_CLIENT_E_BAD_DIP);
336 }
337
338 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
339 "reg", ®, &nreg) != DDI_PROP_SUCCESS) {
340 return (I2C_CLIENT_E_BAD_DIP);
341 }
342
343 if (regno >= nreg / 2) {
344 ddi_prop_free(reg);
345 return (I2C_CLIENT_E_BAD_REG_IDX);
346 }
347
348 addr.ia_type = reg[regno * 2];
349 addr.ia_addr = reg[regno * 2 + 1];
350 ddi_prop_free(reg);
351
352 if (!i2c_addr_validate(&addr, &err)) {
353 return (err.i2c_error);
354 }
355
356 i2c_nexus_t *nex = i2c_dev_to_nexus(dip);
357 i2c_ctrl_t *ctrl = nex->in_ctrl;
358
359 err.i2c_error = i2c_client_bus_lock(ctrl, I2C_LOCK_TAG_CLIENT_ALLOC,
360 nex, true, &txn);
361 if (err.i2c_error != I2C_CORE_E_OK) {
362 return (err.i2c_error);
363 }
364 *clientp = i2c_client_alloc(txn, nex->in_data.in_dev, dip, &addr);
365 i2c_bus_unlock(txn);
366
367 return (I2C_CORE_E_OK);
368 }
369
370 i2c_errno_t
i2c_client_claim_addr(dev_info_t * dip,const i2c_addr_t * addr,i2c_claim_flags_t flags,i2c_client_t ** clientp)371 i2c_client_claim_addr(dev_info_t *dip, const i2c_addr_t *addr,
372 i2c_claim_flags_t flags, i2c_client_t **clientp)
373 {
374 int *reg;
375 uint_t nreg;
376 i2c_error_t err;
377 i2c_txn_t *txn;
378
379 if ((flags & ~I2C_CLAIM_F_SHARED) != 0) {
380 return (I2C_CLIENT_E_BAD_CLAIM_FLAGS);
381 }
382
383 if (!i2c_addr_validate(addr, &err)) {
384 return (err.i2c_error);
385 }
386
387 if (!i2c_dip_is_dev(dip)) {
388 return (I2C_CLIENT_E_BAD_DIP);
389 }
390
391 major_t major = ddi_driver_major(dip);
392 if (major == DDI_MAJOR_T_NONE || major == DDI_MAJOR_T_UNKNOWN) {
393 return (I2C_CLIENT_E_BAD_DIP);
394 }
395
396 /*
397 * Before we do anything else, see if this address is in reg[]. If it
398 * is, then as long as we weren't requesting a shared address, we can
399 * just do a normal i2c_client_init(). By definition the driver already
400 * owns it. Howerver, if the request was for a shared address the device
401 * owns, that's an error.
402 */
403 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
404 "reg", ®, &nreg) != DDI_PROP_SUCCESS) {
405 return (I2C_CLIENT_E_BAD_DIP);
406 }
407 for (uint_t i = 0; i < nreg / 2; i++) {
408 if (reg[i * 2] == addr->ia_type && reg[i * 2 + 1] ==
409 addr->ia_addr) {
410 if ((flags & I2C_CLAIM_F_SHARED) != 0) {
411 return (I2C_CLIENT_E_CLAIM_OWNED_ADDR);
412 }
413
414 return (i2c_client_init(dip, i, clientp));
415 }
416 }
417 ddi_prop_free(reg);
418
419
420 /*
421 * To allocate an address, we need to own the controller. Obtain the
422 * controller lock and use this. The fact that we've claimed this shared
423 * address is recorded on the client and stored on the device so it can
424 * be released when the client is freed.
425 */
426 i2c_nexus_t *nex = i2c_dev_to_nexus(dip);
427 i2c_ctrl_t *ctrl = nex->in_ctrl;
428 VERIFY3U(nex->in_pnex->in_type, ==, I2C_NEXUS_T_PORT);
429 i2c_port_t *port = nex->in_pnex->in_data.in_port;
430
431 err.i2c_error = i2c_client_bus_lock(ctrl, I2C_LOCK_TAG_CLIENT_ALLOC,
432 nex, true, &txn);
433 if (err.i2c_error != I2C_CORE_E_OK) {
434 return (err.i2c_error);
435 }
436
437 bool ret;
438 if ((flags & I2C_CLAIM_F_SHARED) != 0) {
439 ret = i2c_addr_alloc_shared(port, addr, major, &err);
440 } else {
441 ret = i2c_addr_alloc(port, addr, &err);
442 }
443
444 if (!ret) {
445 i2c_bus_unlock(txn);
446 return (err.i2c_error);
447 }
448
449 *clientp = i2c_client_alloc(txn, nex->in_data.in_dev, dip, addr);
450 (*clientp)->icli_flags |= I2C_CLIENT_F_CLAIM_ADDR;
451 if ((flags & I2C_CLAIM_F_SHARED) != 0) {
452 (*clientp)->icli_flags |= I2C_CLIENT_F_SHARED_ADDR;
453 }
454 i2c_bus_unlock(txn);
455
456 return (I2C_CORE_E_OK);
457 }
458
459 const i2c_addr_t *
i2c_client_addr(i2c_client_t * client)460 i2c_client_addr(i2c_client_t *client)
461 {
462 return (&client->icli_addr);
463 }
464
465 void
i2c_bus_unlock(i2c_txn_t * txn)466 i2c_bus_unlock(i2c_txn_t *txn)
467 {
468 i2c_txn_ctrl_unlock(txn);
469 i2c_txn_free(txn);
470 }
471
472 i2c_errno_t
i2c_bus_lock(i2c_client_t * client,i2c_bus_lock_flags_t flags,i2c_txn_t ** txnp)473 i2c_bus_lock(i2c_client_t *client, i2c_bus_lock_flags_t flags, i2c_txn_t **txnp)
474 {
475 bool block;
476 i2c_ctrl_t *ctrl = client->icli_ctrl;
477
478 if ((flags & ~I2C_BUS_LOCK_F_NONBLOCK) != 0) {
479 return (I2C_CLIENT_E_BAD_LOCK_FLAGS);
480 }
481
482 block = (flags & I2C_BUS_LOCK_F_NONBLOCK) == 0;
483 return (i2c_client_bus_lock(ctrl, I2C_LOCK_TAG_CLIENT_LOCK, client,
484 block, txnp));
485 }
486
487 /*
488 * We serialize an I2C client such only one I/O can be issued by a client at a
489 * time. If multiple kernel threads try to do so, they will block. Note, that
490 * this is still not great and means that the caller could clobber their error
491 * information. This mostly is designed as a belt and suspenders bit and to
492 * allow a bit of observability to the fact that this might be happening.
493 */
494 static void
i2c_client_io_release(i2c_client_t * client)495 i2c_client_io_release(i2c_client_t *client)
496 {
497 bool free;
498 i2c_txn_t *txn;
499
500 mutex_enter(&client->icli_mutex);
501 VERIFY3U(client->icli_curthread, ==, curthread);
502 client->icli_curthread = 0;
503 free = (client->icli_flags & I2C_CLIENT_F_ALLOC_TXN) != 0;
504 client->icli_flags &= ~I2C_CLIENT_F_ALLOC_TXN;
505 txn = client->icli_txn;
506 client->icli_txn = NULL;
507 mutex_exit(&client->icli_mutex);
508
509 if (free) {
510 i2c_bus_unlock(txn);
511 }
512 }
513
514 static bool
i2c_client_io_acquire(i2c_txn_t * txn,i2c_client_t * client,i2c_error_t * errp)515 i2c_client_io_acquire(i2c_txn_t *txn, i2c_client_t *client, i2c_error_t *errp)
516 {
517 bool alloc = false;
518
519 if (txn == NULL) {
520 i2c_errno_t err = i2c_bus_lock(client, 0, &txn);
521 if (err != I2C_CORE_E_OK) {
522 return (i2c_error(errp, err, 0));
523 }
524 alloc = true;
525 }
526
527 mutex_enter(&client->icli_mutex);
528 VERIFY3P(client->icli_txn, ==, NULL);
529 client->icli_txn = txn;
530 if (alloc) {
531 client->icli_flags |= I2C_CLIENT_F_ALLOC_TXN;
532 }
533 client->icli_curthread = (uintptr_t)curthread;
534 mutex_exit(&client->icli_mutex);
535
536 return (true);
537 }
538
539 /*
540 * Take care of everything that's required to submit an I/O request. Muxes that
541 * need to be activated are taken care of by the controller logic.
542 */
543 static bool
i2c_client_submit(i2c_client_t * client,bool smbus)544 i2c_client_submit(i2c_client_t *client, bool smbus)
545 {
546 i2c_ctrl_t *ctrl = client->icli_ctrl;
547 i2c_txn_t *txn = client->icli_txn;
548 bool ret;
549
550 VERIFY3P(txn, !=, NULL);
551 VERIFY(i2c_txn_held(txn));
552
553 if (smbus) {
554 ret = i2c_ctrl_io_smbus(txn, ctrl, client->icli_io_port,
555 &client->icli_reqs.req_smbus);
556 } else {
557 ret = i2c_ctrl_io_i2c(txn, ctrl, client->icli_io_port,
558 &client->icli_reqs.req_i2c);
559 }
560
561 return (ret);
562 }
563
564 bool
smbus_client_send_byte(i2c_txn_t * txn,i2c_client_t * client,uint8_t data,i2c_error_t * errp)565 smbus_client_send_byte(i2c_txn_t *txn, i2c_client_t *client, uint8_t data,
566 i2c_error_t *errp)
567 {
568 smbus_req_t *req = &client->icli_reqs.req_smbus;
569 i2c_error_t err;
570
571 if (errp == NULL)
572 errp = &err;
573
574 if (!i2c_client_io_acquire(txn, client, errp)) {
575 return (false);
576 }
577
578 bzero(req, sizeof (smbus_req_t));
579 req->smbr_addr = client->icli_addr;
580 req->smbr_op = SMBUS_OP_SEND_BYTE;
581 req->smbr_wlen = sizeof (data);
582 req->smbr_wdata[0] = data;
583
584 bool ret = i2c_client_submit(client, true);
585 *errp = req->smbr_error;
586 i2c_client_io_release(client);
587 return (ret);
588 }
589
590 bool
smbus_client_write_u8(i2c_txn_t * txn,i2c_client_t * client,uint8_t cmd,uint8_t data,i2c_error_t * errp)591 smbus_client_write_u8(i2c_txn_t *txn, i2c_client_t *client, uint8_t cmd,
592 uint8_t data, i2c_error_t *errp)
593 {
594 smbus_req_t *req = &client->icli_reqs.req_smbus;
595 i2c_error_t err;
596
597 if (errp == NULL)
598 errp = &err;
599
600 if (!i2c_client_io_acquire(txn, client, errp)) {
601 return (false);
602 }
603
604 bzero(req, sizeof (smbus_req_t));
605 req->smbr_addr = client->icli_addr;
606 req->smbr_op = SMBUS_OP_WRITE_BYTE;
607 req->smbr_wlen = sizeof (data);
608 req->smbr_cmd = cmd;
609 req->smbr_wdata[0] = data;
610
611 bool ret = i2c_client_submit(client, true);
612 *errp = req->smbr_error;
613 i2c_client_io_release(client);
614 return (ret);
615 }
616
617 bool
smbus_client_write_u16(i2c_txn_t * txn,i2c_client_t * client,uint8_t cmd,uint16_t data,i2c_error_t * errp)618 smbus_client_write_u16(i2c_txn_t *txn, i2c_client_t *client, uint8_t cmd,
619 uint16_t data, i2c_error_t *errp)
620 {
621 smbus_req_t *req = &client->icli_reqs.req_smbus;
622 i2c_error_t err;
623
624 if (errp == NULL)
625 errp = &err;
626
627 if (!i2c_client_io_acquire(txn, client, errp)) {
628 return (false);
629 }
630
631 bzero(req, sizeof (smbus_req_t));
632 req->smbr_addr = client->icli_addr;
633 req->smbr_op = SMBUS_OP_WRITE_BYTE;
634 req->smbr_wlen = sizeof (data);
635 req->smbr_cmd = cmd;
636 req->smbr_wdata[0] = bitx16(data, 7, 0);
637 req->smbr_wdata[1] = bitx16(data, 15, 8);
638
639 bool ret = i2c_client_submit(client, true);
640 *errp = req->smbr_error;
641 i2c_client_io_release(client);
642 return (ret);
643 }
644
645 bool
smbus_client_recv_byte(i2c_txn_t * txn,i2c_client_t * client,uint8_t * data,i2c_error_t * errp)646 smbus_client_recv_byte(i2c_txn_t *txn, i2c_client_t *client, uint8_t *data,
647 i2c_error_t *errp)
648 {
649 smbus_req_t *req = &client->icli_reqs.req_smbus;
650 i2c_error_t err;
651
652 if (errp == NULL)
653 errp = &err;
654
655 if (!i2c_client_io_acquire(txn, client, errp)) {
656 return (false);
657 }
658
659 bzero(req, sizeof (smbus_req_t));
660 req->smbr_addr = client->icli_addr;
661 req->smbr_op = SMBUS_OP_RECV_BYTE;
662
663 bool ret = i2c_client_submit(client, true);
664 *errp = req->smbr_error;
665 if (ret) {
666 *data = req->smbr_rdata[0];
667 }
668 i2c_client_io_release(client);
669 return (ret);
670 }
671
672 bool
smbus_client_read_u8(i2c_txn_t * txn,i2c_client_t * client,uint8_t cmd,uint8_t * data,i2c_error_t * errp)673 smbus_client_read_u8(i2c_txn_t *txn, i2c_client_t *client, uint8_t cmd,
674 uint8_t *data, i2c_error_t *errp)
675 {
676 smbus_req_t *req = &client->icli_reqs.req_smbus;
677 i2c_error_t err;
678
679 if (errp == NULL)
680 errp = &err;
681
682 if (!i2c_client_io_acquire(txn, client, errp)) {
683 return (false);
684 }
685
686 bzero(req, sizeof (smbus_req_t));
687 req->smbr_addr = client->icli_addr;
688 req->smbr_op = SMBUS_OP_READ_BYTE;
689 req->smbr_cmd = cmd;
690
691 bool ret = i2c_client_submit(client, true);
692 *errp = req->smbr_error;
693 if (ret) {
694 *data = req->smbr_rdata[0];
695 }
696 i2c_client_io_release(client);
697 return (ret);
698 }
699
700 bool
smbus_client_read_u16(i2c_txn_t * txn,i2c_client_t * client,uint8_t cmd,uint16_t * data,i2c_error_t * errp)701 smbus_client_read_u16(i2c_txn_t *txn, i2c_client_t *client, uint8_t cmd,
702 uint16_t *data, i2c_error_t *errp)
703 {
704 smbus_req_t *req = &client->icli_reqs.req_smbus;
705 i2c_error_t err;
706
707 if (errp == NULL)
708 errp = &err;
709
710 if (!i2c_client_io_acquire(txn, client, errp)) {
711 return (false);
712 }
713
714 bzero(req, sizeof (smbus_req_t));
715 req->smbr_addr = client->icli_addr;
716 req->smbr_op = SMBUS_OP_READ_BYTE;
717 req->smbr_cmd = cmd;
718
719 bool ret = i2c_client_submit(client, true);
720 *errp = req->smbr_error;
721 if (ret) {
722 *data = bitset16(0, req->smbr_rdata[0], 7, 0);
723 *data = bitset16(*data, req->smbr_rdata[1], 15, 8);
724 }
725 i2c_client_io_release(client);
726 return (ret);
727 }
728
729 void
i2c_reg_handle_destroy(i2c_reg_hdl_t * reg_hdl)730 i2c_reg_handle_destroy(i2c_reg_hdl_t *reg_hdl)
731 {
732 if (reg_hdl == NULL) {
733 return;
734 }
735
736 mutex_enter(®_hdl->reg_client->icli_mutex);
737 list_remove(®_hdl->reg_client->icli_regs, reg_hdl);
738 mutex_exit(®_hdl->reg_client->icli_mutex);
739 kmem_free(reg_hdl, sizeof (i2c_reg_hdl_t));
740 }
741
742 i2c_errno_t
i2c_reg_handle_init(i2c_client_t * client,const i2c_reg_acc_attr_t * attrp,i2c_reg_hdl_t ** outp)743 i2c_reg_handle_init(i2c_client_t *client, const i2c_reg_acc_attr_t *attrp,
744 i2c_reg_hdl_t **outp)
745 {
746 i2c_ctrl_t *ctrl = client->icli_ctrl;
747 const bool i2c = ctrl->ic_ops->i2c_io_i2c_f != NULL;
748
749 if (attrp->i2cacc_version != I2C_REG_ACC_ATTR_V0) {
750 return (I2C_CLIENT_E_BAD_REG_ATTR_VERS);
751 }
752
753 if (attrp->i2cacc_flags != 0) {
754 return (I2C_CLIENT_E_BAD_REG_ATTR_FLAGS);
755 }
756
757 /*
758 * Currently we only support 1 and 2 byte address and register widths.
759 */
760 if (attrp->i2cacc_reg_len != 1 &&
761 attrp->i2cacc_reg_len != 2) {
762 return (I2C_CLIENT_E_BAD_REG_ATTR_RLEN);
763 }
764
765 switch (attrp->i2cacc_addr_len) {
766 case 1:
767 if (attrp->i2cacc_addr_max > UINT8_MAX) {
768 return (I2C_CLIENT_E_BAD_REG_ATTR_MAX);
769 }
770 break;
771 case 2:
772 if (attrp->i2cacc_addr_max > UINT16_MAX) {
773 return (I2C_CLIENT_E_BAD_REG_ATTR_MAX);
774 }
775
776 if (!i2c) {
777 return (I2C_CLIENT_E_REG_ALEN_UNSUP_BY_CTRL);
778 }
779 break;
780 default:
781 return (I2C_CLIENT_E_BAD_REG_ATTR_ALEN);
782 }
783
784 switch (attrp->i2cacc_addr_endian) {
785 case DDI_NEVERSWAP_ACC:
786 if (attrp->i2cacc_addr_len > 1) {
787 return (I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN);
788 }
789 break;
790 case DDI_STRUCTURE_BE_ACC:
791 case DDI_STRUCTURE_LE_ACC:
792 break;
793 default:
794 return (I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN);
795 }
796
797 switch (attrp->i2cacc_reg_endian) {
798 case DDI_NEVERSWAP_ACC:
799 if (attrp->i2cacc_reg_len > 1) {
800 return (I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN);
801 }
802 break;
803 case DDI_STRUCTURE_BE_ACC:
804 case DDI_STRUCTURE_LE_ACC:
805 break;
806 default:
807 return (I2C_CLIENT_E_BAD_REG_ATTR_ENDIAN);
808 }
809
810 i2c_reg_hdl_t *reg_hdl = kmem_zalloc(sizeof (i2c_reg_hdl_t), KM_SLEEP);
811 reg_hdl->reg_client = client;
812 reg_hdl->reg_attr = *attrp;
813
814 /*
815 * Calculate the number of registers we can take from a read or write
816 * request. If we're issuing a write, we need to take the address length
817 * into account. If we're issuing a read, we don't. If the device
818 * supports I2C, we use the I2C maximums. If the device supports the I2C
819 * block emulation, we can use that as the limit. Otherwise, we are
820 * limited to a single register as that's what an SMBus get operation
821 * can do.
822 *
823 * When we have a two byte address, we need to take that into account
824 * for the length that we're requesting.
825 */
826 if (ctrl->ic_limit.lim_i2c_read != 0) {
827 reg_hdl->reg_max_nread = ctrl->ic_limit.lim_i2c_read /
828 reg_hdl->reg_attr.i2cacc_reg_len;
829 } else {
830 reg_hdl->reg_max_nread = 1;
831 }
832
833 if (ctrl->ic_limit.lim_i2c_write != 0) {
834 uint32_t max = ctrl->ic_limit.lim_i2c_read;
835 if (i2c) {
836 max -= reg_hdl->reg_attr.i2cacc_addr_len;
837 }
838 reg_hdl->reg_max_nwrite = max /
839 reg_hdl->reg_attr.i2cacc_reg_len;
840 } else {
841 reg_hdl->reg_max_nwrite = 1;
842 }
843
844 mutex_enter(&client->icli_mutex);
845 list_insert_tail(&client->icli_regs, reg_hdl);
846 mutex_exit(&client->icli_mutex);
847
848 *outp = reg_hdl;
849 return (I2C_CORE_E_OK);
850 }
851
852 /*
853 * Check several aspects of the request before we proceed with it:
854 *
855 * - That the requested number of bytes is an integral number of registers.
856 * - That the requested address range does not exceed the maximum (inclusive)
857 * address
858 * - That the total number of bytes requested fits within our maximum.
859 */
860 static bool
i2c_reg_check(i2c_reg_hdl_t * hdl,uint64_t addr,uint32_t nbytes,bool get,i2c_error_t * errp)861 i2c_reg_check(i2c_reg_hdl_t *hdl, uint64_t addr, uint32_t nbytes, bool get,
862 i2c_error_t *errp)
863 {
864 const i2c_reg_acc_attr_t *attr = &hdl->reg_attr;
865 size_t reg_max = get ? hdl->reg_max_nread : hdl->reg_max_nwrite;
866
867 if ((nbytes % attr->i2cacc_reg_len) != 0) {
868 return (i2c_error(errp, I2C_CLIENT_E_PARTIAL_REG, 0));
869 }
870
871 uint32_t nregs = nbytes / attr->i2cacc_reg_len;
872 if (nregs > reg_max) {
873 return (i2c_error(errp, I2C_CLIENT_E_REG_IO_TOO_LARGE, 0));
874 }
875
876 if (addr > attr->i2cacc_addr_max) {
877 return (i2c_error(errp, I2C_CLIENT_E_BAD_REG_ADDR, 0));
878 }
879
880 if (nregs == 0 || nregs > attr->i2cacc_addr_max) {
881 return (i2c_error(errp, I2C_CLIENT_E_BAD_REG_COUNT, 0));
882 }
883
884 if (addr > attr->i2cacc_addr_max + 1 - nregs) {
885 return (i2c_error(errp, I2C_CLIENT_E_REG_ADDR_OVERFLOW, 0));
886 }
887
888 return (true);
889 }
890
891 static void
i2c_reg_setup_addr(const i2c_reg_hdl_t * hdl,uint64_t addr,i2c_req_t * req)892 i2c_reg_setup_addr(const i2c_reg_hdl_t *hdl, uint64_t addr, i2c_req_t *req)
893 {
894 if (hdl->reg_attr.i2cacc_addr_len == 1) {
895 req->ir_wdata[0] = addr % UINT8_MAX;
896 req->ir_wlen = 1;
897 return;
898 }
899
900 uint16_t val = addr % UINT16_MAX;
901 switch (hdl->reg_attr.i2cacc_addr_endian) {
902 case DDI_STRUCTURE_BE_ACC:
903 val = BE_16(val);
904 break;
905 case DDI_STRUCTURE_LE_ACC:
906 val = LE_16(val);
907 break;
908 default:
909 break;
910 }
911
912 bcopy(&val, req->ir_wdata, sizeof (val));
913 req->ir_wlen = 2;
914 }
915
916 bool
i2c_reg_get(i2c_txn_t * txn,i2c_reg_hdl_t * hdl,uint64_t addr,void * buf,uint32_t nbytes,i2c_error_t * errp)917 i2c_reg_get(i2c_txn_t *txn, i2c_reg_hdl_t *hdl, uint64_t addr, void *buf,
918 uint32_t nbytes, i2c_error_t *errp)
919 {
920 i2c_req_t *req;
921 i2c_error_t err;
922
923 if (errp == NULL)
924 errp = &err;
925
926 if (!i2c_reg_check(hdl, addr, nbytes, true, errp)) {
927 return (false);
928 }
929
930 if (!i2c_client_io_acquire(txn, hdl->reg_client, errp)) {
931 return (false);
932 }
933
934 req = &hdl->reg_client->icli_reqs.req_i2c;
935 bzero(req, sizeof (i2c_req_t));
936 req->ir_addr = hdl->reg_client->icli_addr;
937
938 i2c_reg_setup_addr(hdl, addr, req);
939 req->ir_rlen = nbytes;
940 VERIFY3U(req->ir_rlen, <=, sizeof (req->ir_rdata));
941 bool ret = i2c_client_submit(hdl->reg_client, false);
942 *errp = req->ir_error;
943 if (!ret) {
944 i2c_client_io_release(hdl->reg_client);
945 return (false);
946 }
947
948 /*
949 * For 1 byte values, we can just copy them into place. For larger
950 * values, we need to manually walk and perform byte swaps.
951 */
952 if (hdl->reg_attr.i2cacc_reg_len == 1) {
953 bcopy(req->ir_rdata, buf, req->ir_rlen);
954 } else {
955 VERIFY3U(hdl->reg_attr.i2cacc_reg_len, ==, sizeof (uint16_t));
956 for (uint32_t i = 0; i < nbytes; i += sizeof (uint16_t)) {
957 uint16_t v;
958
959 bcopy(req->ir_rdata + i, &v, sizeof (v));
960 switch (hdl->reg_attr.i2cacc_reg_endian) {
961 case DDI_STRUCTURE_BE_ACC:
962 v = BE_16(v);
963 break;
964 case DDI_STRUCTURE_LE_ACC:
965 v = LE_16(v);
966 break;
967 default:
968 break;
969 }
970
971 bcopy(&v, buf + i, sizeof (v));
972 }
973 }
974
975 i2c_client_io_release(hdl->reg_client);
976 return (true);
977 }
978
979 bool
i2c_reg_put(i2c_txn_t * txn,i2c_reg_hdl_t * hdl,uint64_t addr,const void * buf,uint32_t nbytes,i2c_error_t * errp)980 i2c_reg_put(i2c_txn_t *txn, i2c_reg_hdl_t *hdl, uint64_t addr, const void *buf,
981 uint32_t nbytes, i2c_error_t *errp)
982 {
983 i2c_req_t *req;
984 i2c_error_t err;
985
986 if (errp == NULL)
987 errp = &err;
988
989 if (!i2c_reg_check(hdl, addr, nbytes, false, errp)) {
990 return (false);
991 }
992
993 if (!i2c_client_io_acquire(txn, hdl->reg_client, errp)) {
994 return (false);
995 }
996
997 req = &hdl->reg_client->icli_reqs.req_i2c;
998 bzero(req, sizeof (i2c_req_t));
999 req->ir_addr = hdl->reg_client->icli_addr;
1000
1001 i2c_reg_setup_addr(hdl, addr, req);
1002
1003 if (hdl->reg_attr.i2cacc_reg_len == 1) {
1004 bcopy(buf, req->ir_wdata + req->ir_wlen, nbytes);
1005 } else {
1006 for (uint32_t i = 0; i < nbytes; i += sizeof (uint16_t)) {
1007 uint16_t v;
1008
1009 bcopy(buf + i, &v, sizeof (v));
1010 switch (hdl->reg_attr.i2cacc_reg_endian) {
1011 case DDI_STRUCTURE_BE_ACC:
1012 v = BE_16(v);
1013 break;
1014 case DDI_STRUCTURE_LE_ACC:
1015 v = LE_16(v);
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 bcopy(&v, req->ir_wdata + req->ir_wlen + i, sizeof (v));
1022 }
1023 }
1024
1025 req->ir_wlen += nbytes;
1026 VERIFY3P(req->ir_wlen, <=, sizeof (req->ir_wdata));
1027
1028 bool ret = i2c_client_submit(hdl->reg_client, false);
1029 *errp = req->ir_error;
1030 i2c_client_io_release(hdl->reg_client);
1031 return (ret);
1032 }
1033
1034 uint32_t
i2c_reg_max_read(i2c_reg_hdl_t * hdl)1035 i2c_reg_max_read(i2c_reg_hdl_t *hdl)
1036 {
1037 return (hdl->reg_max_nread);
1038 }
1039
1040 uint32_t
i2c_reg_max_write(i2c_reg_hdl_t * hdl)1041 i2c_reg_max_write(i2c_reg_hdl_t *hdl)
1042 {
1043 return (hdl->reg_max_nwrite);
1044 }
1045
1046 /*
1047 * We need a relatively unique name for an I2C class sensor. For now we use the
1048 * driver name and instance, along with the address for this particular client.
1049 * Something that looks more like a tree perhaps be better. As we figure out how
1050 * to relate things in topo, we should feel free to revisit this.
1051 */
1052 int
i2c_client_ksensor_create_scalar(i2c_client_t * client,uint64_t kind,const ksensor_ops_t * ops,void * arg,const char * name,id_t * idp)1053 i2c_client_ksensor_create_scalar(i2c_client_t *client, uint64_t kind,
1054 const ksensor_ops_t *ops, void *arg, const char *name, id_t *idp)
1055 {
1056 dev_info_t *dip = client->icli_dip;
1057 const char *class;
1058 char *i2c_name;
1059
1060 switch (kind) {
1061 case SENSOR_KIND_TEMPERATURE:
1062 class = "ddi_sensor:temperature:i2c";
1063 break;
1064 case SENSOR_KIND_VOLTAGE:
1065 class = "ddi_sensor:voltage:i2c";
1066 break;
1067 case SENSOR_KIND_CURRENT:
1068 class = "ddi_sensor:current:i2c";
1069 break;
1070 default:
1071 return (ENOTSUP);
1072 }
1073
1074 i2c_name = kmem_asprintf("%s%d.%x:%s", ddi_driver_name(dip),
1075 ddi_get_instance(dip), client->icli_addr.ia_addr, name);
1076 int ret = ksensor_create(dip, ops, arg, i2c_name, class, idp);
1077 strfree(i2c_name);
1078 return (ret);
1079 }
1080