1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2026 Oxide Computer Company 14 */ 15 16 #ifndef _PCHSMBUS_H 17 #define _PCHSMBUS_H 18 19 /* 20 * Intel ICH/PCH SMBus Controller Definitions 21 * 22 * The ICH/PCH Controller is a device that always shows up in PCI configuration 23 * space. It has a few registers in configuration space and then has a primary 24 * BAR. That BAR is either I/O space or memory space depending on the 25 * generation. The original version of this in the ICH used I/O space. By the 26 * time of the PCH-era devices, this BAR shows up in memory space. Regardless of 27 * the source, the register definitions have generally stayed the same, with 28 * newer devices adding additional registers. We will denote in comments when 29 * certain registers and fields were added. 30 * 31 * A few notes and conventions: 32 * 33 * - All registers are generally 8-bit registers unless explicitly noted 34 * otherwise. 35 * - Registers in configuration space use the _PCI_ where as registers in the 36 * bar use _BAR_ to indicate where they are found. 37 */ 38 39 #include <sys/bitext.h> 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 46 /* 47 * Host Configuration -- HCFG (config space). 48 */ 49 #define PCH_R_PCIE_HCFG 0x40 50 /* 51 * Disable writes to SPD related data. This bit locks. It was added in PCH 7 52 * generation. It was reserved prior to this, so we can just read the reserved 0 53 * bit and interpret it as needed. 54 */ 55 #define PCH_R_HCFG_GET_SPDWD(r) bitx8(r, 4, 4) 56 /* 57 * Subsystem reset added in ICH8. 58 */ 59 #define PCH_R_HCFG_GET_SSRESET(r) bitx32(r, 3, 3) 60 #define PCH_R_HCFG_SET_SSRESET(r, v) bitset8(r, 3, 3, v) 61 #define PCH_R_HCFG_SET_I2CEN(r, v) bitset8(r, 2, 2, v) 62 #define PCH_R_HCFG_I2CEN_I2C 1 63 #define PCH_R_HCFG_I2CEN_SMBUS 0 64 #define PCH_R_HCFG_GET_SMI_EN(r) bitx8(r, 1, 1) 65 #define PCH_R_HCFG_SET_EN(r, v) bitset8(r, 0, 0, v) 66 67 /* 68 * Host Timing -- HTIM (config). 32-bits. 69 * 70 * Starting in the 100 series chipset Intel started mentioning the presence of 71 * the host timing register in PCI configuration space. Whether this is 72 * documented or not seems to vary. We mention this here, but our ability to 73 * confirm its register layout and presence across generations is rather 74 * limited. What knowledge we do have comes from the Ice Lake-D documentation 75 * and is also present in the C600 docs. It seems like in practice this may be 76 * there but documentation is sparse. These fields depend on the PHY clock. 77 */ 78 #define PCH_R_PCIE_HTIM 0x64 79 /* 80 * 0x0: -7 clocks 81 * 0x8: 0 clocks 82 * 0xff: 247 clocks 83 */ 84 #define PCH_R_HTIM_SET_THIGH(r, v) bitset32(r, 31, 24, v) 85 #define PCH_R_HTIM_SET_TLOW(r, v) bitset32(r, 23, 16, v) 86 /* 87 * Signed 4-bit two's complement. 0xf is -7, 0x7 is +7 88 */ 89 #define PCH_R_HTIM_SET_THDSTA(r, v) bitset32(r, 15, 12, v) 90 #define PCH_R_HTIM_SET_TSUSTA(r, v) bitset32(r, 11, 8, v) 91 #define PCH_R_HTIM_SET_TBUF(r, v) bitset32(r, 7, 4, v) 92 #define PCH_R_HTIM_SET_TSUSTO(r, v) bitset32(r, 3, 0, v) 93 94 /* 95 * Host Status -- HSTS (HST_STA) 96 */ 97 #define PCH_R_BAR_HSTS 0x00 98 typedef enum { 99 /* 100 * Byte done status (BDS). Indicates that a byte has been transmitted or 101 * received when the 32-byte buffer is not being used. 102 */ 103 PCH_HSTS_BYTE_DONE = 1 << 7, 104 /* 105 * In use status (IUS). This indicates that the device is currently in 106 * use. This is basically set whenever a read occurs and is meant to 107 * allow for software synchronization. 108 */ 109 PCH_HSTS_IN_USE = 1 << 6, 110 /* 111 * SMBus Alert status. Indicates that an SMBus Alert has been generated. 112 */ 113 PCH_HSTS_SMBUS_ALERT = 1 << 5, 114 /* 115 * Fail. This is set when a failed bus transaction occurs due to the 116 * kill bit being set. That is, software caused this. 117 */ 118 PCH_HSTS_FAIL = 1 << 4, 119 /* 120 * Bus error (BERR). This is set when a transaction collision occurs. 121 */ 122 PCH_HSTS_BUS_ERR = 1 << 3, 123 /* 124 * Device Error (DERR). This is in a number of different cases by 125 * hardware that may be host initiated such as illegal commands, device 126 * time outs, CRC errors, or more. 127 */ 128 PCH_HSTS_DEV_ERR = 1 << 2, 129 /* 130 * Interrupt (INTR). This indicates that the interrupt occurred because 131 * the last command was successful. 132 */ 133 PCH_HSTS_INTR = 1 << 1, 134 /* 135 * Host Busy (HBSY) Indicates that the device is busy running a command. 136 * When this is set only the block data is supposed to be accessed. 137 */ 138 PCH_HSTS_BUSY = 1 << 0 139 } pch_smbus_sts_t; 140 141 /* 142 * Macros for combinations of host status pieces that we care about. The first 143 * of these is the collection of errors. The second of these is the set of 144 * statuses we want to clear before a transaction and the second the ones after. 145 * The primary distinction here is that we don't want to clear the in use flag 146 * until we're done with an operation. While we don't actually support alerts, 147 * we make it part of the default clear set. Finally, the host busy flag is 148 * never part of these as we never want to manually clear the flag. 149 */ 150 #define PCH_HSTS_ERRORS (PCH_HSTS_FAIL | PCH_HSTS_BUS_ERR | \ 151 PCH_HSTS_DEV_ERR) 152 #define PCH_HSTS_CLEAR_PRE (PCH_HSTS_ERRORS | PCH_HSTS_INTR | \ 153 PCH_HSTS_BYTE_DONE | PCH_HSTS_SMBUS_ALERT) 154 #define PCH_HSTS_CLEAR_POST (PCH_HSTS_CLEAR_PRE | PCH_HSTS_IN_USE) 155 156 /* 157 * Host Control -- HCTL (HST_CNT) 158 */ 159 #define PCH_R_BAR_HCTL 0x02 160 /* 161 * PEC Controls were added in ICH3+. 162 */ 163 #define PCH_R_HCTL_SET_PEC(r, v) bitset8(r, 7, 7, v) 164 #define PCH_R_HCTL_SET_START(r, v) bitset8(r, 6, 6, v) 165 #define PCH_R_HCTL_SET_LAST(r, v) bitset8(r, 5, 5, v) 166 #define PCH_R_HCTL_SET_CMD(r, v) bitset8(r, 4, 2, v) 167 #define PCH_R_HCTL_SET_KILL(r, v) bitset8(r, 1, 1, v) 168 #define PCH_R_HCTL_SET_INT_EN(r, v) bitset8(r, 0, 0, v) 169 170 /* 171 * Host Command -- HCMD (HST_CMD). 172 * 173 * This contains the 8-bit SMBus command field. 174 */ 175 #define PCH_R_BAR_HCMD 0x03 176 177 /* 178 * Target Address -- TSA (XMIT_SLVA) 179 * 180 * This sets the 7-bit address and the read/write bit. 181 */ 182 #define PCH_R_BAR_TSA 0x04 183 #define PCH_R_TSA_SET_ADDR(r, v) bitset8(r, 7, 1, v) 184 #define PCH_R_TSA_SET_RW(r, v) bitset8(r, 0, 0, v) 185 #define PCH_R_TSA_RW_WRITE 0 186 #define PCH_R_TSA_RW_READ 1 187 188 /* 189 * Host Data 0 -- HD0 (HST_D0) 190 * Host Data 1 -- HD0 (HST_D1) 191 * 192 * These two bytes represent data sent or received in the SMBus commands. When 193 * using the block transfer, data 0 is the actual byte count that should be 194 * transferred. 195 */ 196 #define PCH_R_BAR_HD0 0x05 197 #define PCH_R_BAR_HD1 0x06 198 199 /* 200 * Host Block Data -- HBD (BLOCK_DB). 201 * 202 * This register is used as either a FIFO or a single byte buffer depending on 203 * whether or not the corresponding feature is enabled in the AUXC register. The 204 * ability to treat this as a FIFO was added in ICH4. 205 */ 206 #define PCH_R_BAR_HBD 0x07 207 208 /* 209 * Packet Error Check Data -- PEC. ICH3+ 210 */ 211 #define PCH_R_BAR_PEC 0x08 212 213 /* 214 * Receive Target Address -- RSA (RCV_SLVA). ICH2+ 215 */ 216 #define PCH_R_BAR_RSA 0x09 217 #define PCH_R_RSA_SET_ADDR(r, v) bitset8(r, 6, 0, v) 218 219 /* 220 * Target Data Register -- SD (SLV_DATA). ICH2+, 16-bits wide. 221 * 222 * This is a two byte register that contains the data that was received. The low 223 * bits correspond to message byte 0. The high bits, byte 1. 224 */ 225 #define PCH_R_BAR_SD 0x0a 226 227 /* 228 * Auxiliary Status -- AUXS (AUX_STS). ICH4+ 229 * 230 * When the ME is present and there are SMLink connections, some of these bits 231 * are read-only bits that describe whether they are enabled or present. 232 * However, the exact mapping here is unclear and as we cannot interact with 233 * them, left out. 234 */ 235 #define PCH_R_BAR_AUXS 0x0c 236 #define PCH_R_AUXS_GET_CRCE(r) bitx8(r, 0, 0) 237 #define PCH_R_AUXS_SET_CRCE(r, v) bitx8(r, 0, 0, v) 238 239 /* 240 * Auxiliary Control -- AUXC (AUX_CTL). ICH4+ 241 * 242 * This register enables a number of additional features in the controller. 243 */ 244 #define PCH_R_BAR_AUXC 0x0d 245 #define PCH_R_AUXC_SET_E32B(r, v) bitset8(r, 1, 1, v) 246 #define PCH_R_AUXC_SET_AAC(r, v) bitset8(r, 0, 0, v) 247 248 /* 249 * SMLink Pin Control -- SMLC. ICH2+ 250 * 251 * The SMLink is a controller that is nominally owned by the ME on several 252 * platforms. 253 */ 254 #define PCH_R_BAR_SMLC 0x0e 255 #define PCH_R_SMLC_SET_CLK_OVR(r) bitset8(r, 2, 2, v) 256 #define PCH_R_SMLC_CLK_LOW 0 257 #define PCH_R_SMLC_CLK_DEF 1 258 #define PCH_R_SMLC_GET_DATA(r) bitx8(r, 1, 1, v) 259 #define PCH_R_SMLC_GET_BCLK(r) bitx8(r, 0, 0, v) 260 261 /* 262 * SMBus Pin Control -- SMBC. ICH2+ 263 * 264 * This provides the current status of the bus pins and provides an override for 265 * the clock to force it low. 266 */ 267 #define PCH_R_BAR_SMBC 0x0f 268 #define PCH_R_SMBC_SET_CLK_OVR(r, v) bitset8(r, 2, 2, v) 269 #define PCH_R_SMBC_CLK_LOW 0 270 #define PCH_R_SMBC_CLK_DEF 1 271 #define PCH_R_SMBC_GET_DATA(r) bitx8(r, 1, 1, v) 272 #define PCH_R_SMBC_GET_BCLK(r) bitx8(r, 0, 0, v) 273 274 /* 275 * Target Status Register -- SSTS (SLV_STS). ICH3+ 276 */ 277 #define PCH_R_BAR_SSTS 0x10 278 #define PCH_R_SSTS_GET_HNS(r) bitx8(r, 0, 0) 279 #define PCH_R_SSTS_SET_HNS(r) bitx8(r, 0, 0, 1) 280 281 /* 282 * Target Command Register -- SCMD (SLV_CMD). ICH3+ 283 */ 284 #define PCH_R_BAR_SCMD 0x11 285 #define PCH_R_SCMD_GET_SMB_D(r) bitx8(r, 2, 2) 286 #define PCH_R_SCMD_SET_SMB_D(r, v) bitset8(r, 2, 2, v) 287 #define PCH_R_SCMD_GET_HNW(r) bitx8(r, 1, 1) 288 #define PCH_R_SCMD_SET_HNW(r, v) bitset8(r, 1, 1, v) 289 #define PCH_R_SCMD_GET_HNI(r) bitx8(r, 0, 0) 290 #define PCH_R_SCMD_SET_HNI(r, v) bitset8(r, 0, 0, v) 291 292 /* 293 * Notify Device Address -- NDA. ICH3+ 294 */ 295 #define PCH_R_BAR_NDA 0x14 296 #define PCH_R_NDA_SET_ADDR(r, v) bitset8(r, 7, 1, v) 297 298 /* 299 * Notify Data Low Byte -- NDLB. ICH3+ 300 * Notify Data High Byte -- NDHB. ICH3+ 301 * 302 * These registers contain the notification data when the notification status is 303 * set. The entire register is used for the byte. 304 */ 305 #define PCH_R_BAR_NDLB 0x16 306 #define PCH_R_BAR_NDHB 0x17 307 308 /* 309 * Command Operation Codes. These values must match the expectations of the Host 310 * Control register's command field. These do not have read versus write 311 * distinctions (other than i2c reads). Read versus write otherwise comes from 312 * the direction used. 313 */ 314 typedef enum { 315 PCH_SMBUS_CMD_QUICK = 0, 316 PCH_SMBUS_CMD_BYTE = 1, 317 PCH_SMBUS_CMD_BYTE_DATA = 2, 318 PCH_SMBUS_CMD_WORD_DATA = 3, 319 PCH_SMBUS_CMD_PROC_CALL = 4, 320 PCH_SMBUS_CMD_BLOCK = 5, 321 /* 322 * According to various datasheets, this command was added even in the 323 * original ICH. Other drivers claim that this was only supported 324 * started in ICH5+. In practice, we don't support anything without the 325 * extended buffer support and we are unlikely to find a 64-bit system 326 * with this old a chipset (but if we do, we can address it then). 327 */ 328 PCH_SMBUS_CMD_I2C_READ = 6, 329 /* 330 * This feature was specifically listed starting in ICH5+. 331 */ 332 PCH_SMBUS_CMD_BLOCK_PROC = 7 333 } pch_smbus_cmd_t; 334 335 /* 336 * These are a series of features that different devices can support that our 337 * per-device detection leverages to know what to use or not. Just because a 338 * feature is listed here doesn't mean the driver will take advantage or work on 339 * hardware without it. We have left out timing control due to its limited 340 * documentation. 341 */ 342 typedef enum { 343 /* 344 * Indicates that the controller supports acting as a target and that it 345 * supports notification features. The first is ICH2+. The second is 346 * ICH3+. 347 */ 348 PCH_SMBUS_FEAT_TARG = 1 << 0, 349 PCH_SMBUS_FEAT_TARG_NOTIFY = 1 << 1, 350 /* 351 * This indicates support for calculating the PEC and checking it in 352 * software. Generally speaking this is ICH3+. 353 */ 354 PCH_SMBUS_FEAT_SW_PEC = 1 << 2, 355 /* 356 * This indicates support for hardware PEC features. Generally speaking 357 * this is ICH4+. 358 */ 359 PCH_SMBUS_FEAT_HW_PEC = 1 << 3, 360 /* 361 * This indicates that the hardware supports the 32 byte block buffer 362 * features. This generally was added in ICH4+. 363 */ 364 PCH_SMBUS_FEAT_32B_BUF = 1 << 4, 365 /* 366 * This indicates that the hardware supports the block procedure call 367 * function. This is ICH5+. 368 */ 369 PCH_SMBUS_FEAT_BLOCK_PROC = 1 << 5, 370 /* 371 * Indicates support for the subsystem reset. This is ICH8+. 372 */ 373 PCH_SMBUS_FEAT_RESET = 1 << 6, 374 } pch_smbus_feat_t; 375 376 #define PCH_SMBUS_FEAT_ALL_ICH2 PCH_SMBUS_FEAT_TARG 377 #define PCH_SMBUS_FEAT_ALL_ICH3 (PCH_SMBUS_FEAT_ALL_ICH2 | \ 378 PCH_SMBUS_FEAT_TARG_NOTIFY | PCH_SMBUS_FEAT_SW_PEC) 379 #define PCH_SMBUS_FEAT_ALL_ICH4 (PCH_SMBUS_FEAT_ALL_ICH3 | \ 380 PCH_SMBUS_FEAT_HW_PEC | PCH_SMBUS_FEAT_32B_BUF) 381 #define PCH_SMBUS_FEAT_ALL_ICH5 (PCH_SMBUS_FEAT_ALL_ICH4 | \ 382 PCH_SMBUS_FEAT_BLOCK_PROC) 383 #define PCH_SMBUS_FEAT_ALL_ICH8 (PCH_SMBUS_FEAT_ALL_ICH5 | \ 384 PCH_SMBUS_FEAT_RESET) 385 386 /* 387 * The following are various PCI IDs for devices that we've sourced from Intel 388 * datasheets. 389 */ 390 #define PCH_SMBUS_VID_INTEL 0x8086 391 #define PCH_SMBUS_ICH0_82801AA 0x2413 392 #define PCH_SMBUS_ICH0_82901AB 0x2423 393 #define PCH_SMBUS_ICH2_82801BA 0x2443 394 #define PCH_SMBUS_ICH3_82801CA 0x2483 395 #define PCH_SMBUS_ICH4_82801DB 0x24c3 396 #define PCH_SMBUS_ICH5_82801Ex 0x24d3 397 #define PCH_SMBUS_6300ESB 0x25a4 398 #define PCH_SMBUS_ICH6 0x266a 399 #define PCH_SMBUS_631xESB 0x269b /* Also 632xESB */ 400 #define PCH_SMBUS_ICH7 0x27da 401 #define PCH_SMBUS_ICH8 0x283e 402 #define PCH_SMBUS_ICH9 0x2930 403 #define PCH_SMBUS_ICH10_USER 0x3a30 404 #define PCH_SMBUS_ICH10_CORP 0x3a60 405 #define PCH_SMBUS_PCH5 0x3b30 /* Also 3400 */ 406 #define PCH_SMBUS_PCH6 0x1cc2 /* Also C200 */ 407 #define PCH_SMBUS_C600 0x1d22 /* Also X79 */ 408 #define PCH_SMBUS_C600_SMB0 0x1d70 409 #define PCH_SMBUS_C600_SMB1 0x1d71 /* C606/C608 */ 410 #define PCH_SMBUS_C600_SMB2 0x1d72 /* C608 */ 411 #define PCH_SMBUS_DH89xxCC 0x2330 412 #define PCH_SMBUS_DH89xxCL 0x23b0 413 #define PCH_SMBUS_PCH7 0x1e22 /* Also C216 */ 414 #define PCH_SMBUS_PCH8 0x8cc2 /* Also C220 */ 415 /* 416 * This device ID has seen a bunch of use. It was originally the 4th Gen Core 417 * series low power ID. The 300 series on package low power also used it. It has 418 * also been used by some of the Braswell N/J 3xxx Atoms. 419 */ 420 #define PCH_SMBUS_PCH8_LP 0x9c22 421 #define PCH_SMBUS_C610 0x8d22 /* Also X99 */ 422 /* Owned by the ME, but may be released to us */ 423 #define PCH_SMBUS_C610_MS0 0x8d7d 424 #define PCH_SMBUS_C610_MS1 0x8d7e 425 #define PCH_SMBUS_C610_MS2 0x8d7f 426 #define PCH_SMBUS_PCH9 0x8ca2 427 #define PCH_SMBUS_PCH9_LP 0x9ca2 /* 5th Gen Mobile */ 428 #define PCH_SMBUS_BAYTRAIL 0x0f12 /* E3800 and Z3700 Atom */ 429 #define PCH_SMBUS_100 0xa123 /* Also C230 */ 430 #define PCH_SMBUS_DENVERTON 0x19df /* Atom C3000 */ 431 #define PCH_SMBUS_C740 0x1bc9 432 #define PCH_SMBUS_APOLLO 0x5ad4 /* Atom E3900, Silver Celeron */ 433 #define PCH_SMBUS_C620 0xa1a3 434 #define PCH_SMBUS_C620_SUPER 0xa223 435 #define PCH_SMBUS_200 0xa2a3 /* Also X299/Z370 */ 436 #define PCH_SMBUS_GEMINI 0x31d4 437 #define PCH_SMBUS_300 0xa323 /* Also C240 */ 438 /* Ice Lake Variants */ 439 #define PCH_SMBUS_ICE_LAKE_D 0x18df 440 #define PCH_SMBUS_495_PKG 0x34a3 441 /* Comet Lake */ 442 #define PCH_SMBUS_400_PKG 0x02a3 443 #define PCH_SMBUS_400 0x06a3 444 /* Elkhart Lake aka Atom x6000E */ 445 #define PCH_SMBUS_ELKHART 0x4b23 446 /* Tiger Lake */ 447 #define PCH_SMBUS_500 0x43a3 448 #define PCH_SMBUS_500_PKG 0xa0a3 449 #define PCH_SMBUS_JASPER 0x4da3 /* Pentium/Celeron Silver (Atom) */ 450 /* Alder Lake */ 451 #define PCH_SMBUS_600 0x7aa3 /* Also 700 series */ 452 #define PCH_SMBUS_600_PKG 0x51a3 /* Also 700 On-Package */ 453 #define PCH_SMBUS_ALDER_N 0x54a3 454 /* Raptor Lake */ 455 #define PCH_SMBUS_700 0x7a23 456 /* Meteor Lake */ 457 #define PCH_SMBUS_800 0x7f23 458 #define PCH_SMBUS_METEOR_PS 0x7e22 /* Also -H/-E */ 459 /* Arrow Lake */ 460 #define PCH_SMBUS_ULTRA_200 0x7722 461 /* Panther Lake */ 462 #define PCH_SMBUS_PANTHER_H 0xe322 463 #define PCH_SMBUS_PANTHER_P 0xe422 464 /* Nova Lake */ 465 #define PCH_SMBUS_900 0x6e23 466 467 #ifdef __cplusplus 468 } 469 #endif 470 471 #endif /* _PCHSMBUS_H */ 472