1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 #ifndef _ISMT_H 17 #define _ISMT_H 18 19 /* 20 * Intel SMBus Message Target Register Definitions 21 */ 22 23 #include <sys/types.h> 24 #include <sys/bitext.h> 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* 31 * General control register. 32 */ 33 #define ISMT_R_GCTRL 0x000 34 #define ISMT_R_GCTRL_SET_SRST(r, v) bitset32(r, 6, 6, v) 35 #define ISMT_R_GCTRL_SET_KILL(r, v) bitset32(r, 3, 3, v) 36 #define ISMT_R_GCTRL_SET_TRST(r, v) bitset32(r, 2, 2, v) 37 38 /* 39 * Interrupt cause DMA logging. While we don't actually use this information, we 40 * assume that hwarwdare may want to write to it. 41 */ 42 #define ISMT_R_SMTICL 0x008 43 44 /* 45 * These registers contain error masks that in theory firmware might manipulate. 46 * We don't mask any errors by default and leave these at their defaults. The 47 * last one is the current error status. Errors here are from the Xeon 48 * D-1700/1800/2700/2800. We don't know if they're used across more devices or 49 * not. 50 */ 51 #define ISMT_R_ERRINTMSK 0x010 52 #define ISMT_R_ERRAERMSK 0x014 53 #define ISMT_R_ERRSTS 0x018 54 typedef enum { 55 ISMT_ERR_CPE = 1 << 0, 56 ISMT_ERR_SPDWE = 1 << 1, 57 ISMT_ERR_IRE = 1 << 8, 58 ISMT_ERR_IRDPE = 1 << 9, 59 ISMT_ERR_ITE = 1 << 10, 60 ISMT_ERR_IMAE = 1 << 11, 61 ISMT_ERR_IHIE = 1 << 12, 62 ISMT_ERR_TRBAF = 1 << 16, 63 ISMT_ERR_TRBF = 1 << 17, 64 ISMT_ERR_CKLTO = 1 << 24 65 } ismt_err_t; 66 67 /* 68 * When an error occurs this is used to set information about what errors 69 * occurred in the ERRSTS register. 70 */ 71 #define ISMT_R_ERRINFO 0x01c 72 #define ISMT_R_ERRINFO_GET_INFO2(r) bitx32(r, 15, 13) 73 #define ISMT_R_ERRINFO_GET_PTRO2(r) bitx32(r, 12, 8) 74 #define ISMT_R_ERRINFO_GET_INFO1(r) bitx32(r, 7, 5) 75 #define ISMT_R_ERRINFO_GET_PTRO1(r) bitx32(r, 4, 0) 76 77 /* 78 * Controller-specific registers. 79 */ 80 81 /* 82 * Controller descriptor base address. Must be 64 byte aligned. 83 */ 84 #define ISMT_R_MDBA 0x100 85 86 /* 87 * Controller control register. 88 */ 89 #define ISMT_R_MCTRL 0x108 90 #define ISMT_R_MCTRL_SET_FMHP(r, v) bitset32(r, 23, 16, v) 91 #define ISMT_R_MCTRL_SET_MEIE(r, v) bitset32(r, 4, 4, v) 92 #define ISMT_R_MCTRL_GET_SPDDIS(r, v) bitx32(r, 3, 3) 93 #define ISMT_R_MCTRL_SET_SS(r, v) bitset32(r, 0, 0, v) 94 95 /* 96 * Controller status register. 97 */ 98 #define ISMT_R_MSTS 0x10c 99 #define ISMT_R_MSTS_GET_HMTP(r) bitx32(r, 23, 16) 100 #define ISMT_R_MSTS_SET_HMTP(r, v) bitset32(r, 23, 16, v) 101 #define ISMT_R_MSTS_GET_MIS(r) bitx32(r, 5, 5) 102 #define ISMT_R_MSTS_GET_MEIS(r) bitx32(r, 4, 4) 103 #define ISMT_R_MSTS_GET_IP(r) bitx32(r, 0, 0) 104 105 /* 106 * Controller descriptor size register. Sets the descriptor ring size. The 107 * value is 0s based, menaing the actual value is x + 1. 108 */ 109 #define ISMT_R_MDS 0x110 110 #define ISMT_R_MDS_SET_SIZE(r, v) bitset32(r, 7, 0, v) 111 112 /* 113 * This register controls the various retry policy aspects. 114 */ 115 #define ISMT_R_RPOLICY 0x114 116 117 /* 118 * Timing related registers. These are more registers that are in theory 119 * supposed to only be manipulated by firmware and several of these are supposed 120 * to be fused. We expose these mostly as read-only properties. 121 */ 122 #define ISMT_R_SPGT 0x300 123 #define ISMT_R_SPGT_GET_SPD(r) bitx32(r, 31, 30) 124 #define ISMT_R_SPT_SPD_80K 0 125 #define ISMT_R_SPT_SPD_100K 1 126 #define ISMT_R_SPT_SPD_400K 2 127 #define ISMT_R_SPT_SPD_1M 3 128 #define ISMT_R_SPGT_GET_THDDAT(r) bitx32(r, 19, 16) 129 #define ISMT_R_SPGT_GET_TSUDAT(r) bitx32(r, 11, 8) 130 #define ISMT_R_SPGT_GET_DG(r) bitx32(r, 7, 0) 131 #define ISMT_R_SPMT 0x304 132 #define ISMT_R_SPMT_GET_THIGH(r) bitx32(r, 31, 24) 133 #define ISMT_R_SPMT_GET_TLOW(r) bitx32(r, 23, 16) 134 #define ISMT_R_SPMT_GET_THDSTA(r) bitx32(r, 15, 12) 135 #define ISMT_R_SPMT_GET_TSUSTA(r) bitx32(r, 11, 8) 136 #define ISMT_R_SPMT_GET_TBUF(r) bitx32(r, 7, 4) 137 #define ISMT_R_SPMT_GET_TSUSTO(r) bitx32(r, 3, 0) 138 139 typedef struct { 140 uint32_t id_cmd_addr; 141 uint32_t id_status; 142 uint32_t id_low; 143 uint32_t id_high; 144 } ismt_desc_t; 145 146 /* 147 * Flags that control various behaviors: 148 */ 149 #define ISMT_DESC_CMD_SET_SOE(r, v) bitset32(r, 31, 31, v) 150 #define ISMT_DESC_CMD_SET_INT(r, v) bitset32(r, 30, 30, v) 151 #define ISMT_DESC_CMD_SET_I2C(r, v) bitset32(r, 29, 29, v) 152 #define ISMT_DESC_CMD_SET_PEC(r, v) bitset32(r, 28, 28, v) 153 #define ISMT_DESC_CMD_SET_FAIR(r, v) bitset32(r, 27, 27, v) 154 #define ISMT_DESC_CMD_SET_BLK(r, v) bitset32(r, 26, 26, v) 155 #define ISMT_DESC_CMD_SET_CWRL(r, v) bitset32(r, 24, 24, v) 156 157 /* 158 * This sets the read and write lenths, as well as the address. 159 */ 160 #define ISMT_DESC_CMD_SET_RDLEN(r, v) bitset32(r, 23, 16, v) 161 #define ISMT_DESC_CMD_SET_WRLEN(r, v) bitset32(r, 15, 8, v) 162 #define ISMT_DESC_CMD_SET_ADDR(r, v) bitset32(r, 7, 1, v) 163 #define ISMT_DESC_CMD_SET_RW(r, v) bitset32(r, 0, 0, v) 164 #define ISMT_DESC_CMD_RW_READ 1 165 #define ISMT_DESC_CMD_RW_WRITE 0 166 167 /* 168 * Actual number of transmitted and read bytes. 169 */ 170 #define ISMT_DESC_STS_GET_WRLEN(r) bitx32(r, 31, 24) 171 #define ISMT_DESC_STS_GET_RDLEN(r) bitx32(r, 23, 16) 172 #define ISMT_DESC_STS_GET_COLRTRY(r) bitx32(r, 14, 12) 173 #define ISMT_DESC_STS_GET_RETRY(r) bitx32(r, 11, 8) 174 #define ISMT_DESC_STS_GET_LPR(r) bitx32(r, 7, 7) 175 #define ISMT_DESC_STS_GET_COL(r) bitx32(r, 6, 6) 176 #define ISMT_DESC_STS_GET_CLTO(r) bitx32(r, 5, 5) 177 #define ISMT_DESC_STS_GET_CRC(r) bitx32(r, 4, 4) 178 #define ISMT_DESC_STS_GET_NACK(r) bitx32(r, 3, 3) 179 #define ISMT_DESC_STS_GET_SCS(r) bitx32(r, 0, 0) 180 181 /* 182 * Hardware maximum read and write lengths. The maximum write length includes 183 * the address byte and any command codes. The documentation is not the clearest 184 * around maximums (using Intel doc #595910, Rev 2.3) as an example. 185 * 186 * It says at various points that I2C transactions can be up to 240 bytes. 187 * However, it also says in the context of internal buffers that reads needs to 188 * be less than 32 bytes and writes less than 80 bytes. However, this is also 189 * referenced to a section about PEC. The 80 byte value is also supposed to 190 * include the command and the address, meaning that it would be limited to 78 191 * bytes. Ultimately, we constrain any SMBus style transaction to 32 bytes and 192 * allow all I2C transactions to be up to 240. 193 */ 194 #define ISMT_MAX_SMBUS 32 195 #define ISMT_MAX_I2C 240 196 197 #ifdef __cplusplus 198 } 199 #endif 200 201 #endif /* _ISMT_H */ 202