1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2025 Oxide Computer Company
14 */
15
16 /*
17 * Intel SMBus Message Transport controller driver.
18 *
19 * This is a DMA based SMBus controller that is found in some of the various
20 * Atom and Xeon-D based platforms. The hardware divides registers into three
21 * rough groups. There are the general registers, controller specific registers,
22 * and target specific registers. We don't implement the target.
23 *
24 * The device can support a ring of DMA transfers. We only will have one
25 * outstanding at a time, so we go with a simple length of 4 entries and have a
26 * single data DMA buffer that is used by all commands.
27 *
28 * Unlike the PCH-based SMBus controller, this controller supports both SMBus
29 * 2.0 commands and can perform arbitrary commands over I2C.
30 */
31
32 #include <sys/modctl.h>
33 #include <sys/conf.h>
34 #include <sys/devops.h>
35 #include <sys/ddi.h>
36 #include <sys/sunddi.h>
37 #include <sys/pci.h>
38 #include <sys/sysmacros.h>
39
40 #include <sys/i2c/controller.h>
41 #include "ismt.h"
42
43 /*
44 * The controller has a single BAR, SMTBAR, which is found in the BAR 0/1. This
45 * translates to reg[1] as reg[0] contains the config space information about
46 * the device.
47 */
48 #define ISMT_REGNO 1
49
50 /*
51 * Because we never use the offset and address for syncing, we want to cast the
52 * DMA sync call to void, but lets be paranoid on debug.
53 */
54 #ifdef DEBUG
55 #define ISMT_DMA_SYNC(buf, flag) ASSERT0(ddi_dma_sync((buf).id_hdl, \
56 0, 0, flag))
57 #else
58 #define ISMT_DMA_SYNC(buf, flag) (void) ddi_dma_sync((buf).id_hdl, \
59 0, 0, flag)
60 #endif /* DEBUG */
61
62
63 /*
64 * Allocation sizes for our ring and DMA data buffer. We size the ring at 4
65 * entries (though it seems like we could probably get away with just one). The
66 * data buffer we size at 128 bytes, which covers both the maximum read and
67 * maximum write in one go (though we shouldn't exceed it either one). The last
68 * one of these, the interrupt cause log size is the hardest. It defitely is
69 * written before every interrupt, but whether we need one of these per entry in
70 * the log or it just clobbers the last location is unclear. It doesn't actually
71 * ask for a size so we just double the number of ring entries.
72 */
73 #define ISMT_RING_NENTS 4
74 #define ISMT_RING_DMA_SIZE (ISMT_RING_NENTS * sizeof (ismt_desc_t))
75 #define ISMT_DATA_BUF_SIZE 128U
76 #define ISMT_ICL_DMA_SIZE (ISMT_RING_NENTS * sizeof (uint32_t) * 2)
77
78 typedef enum {
79 ISMT_INIT_PCI = 1 << 0,
80 ISMT_INIT_REGS = 1 << 1,
81 ISMT_INIT_INTR_ALLOC = 1 << 2,
82 ISMT_INIT_INTR_HDL = 1 << 3,
83 ISMT_INIT_SYNC = 1 << 4,
84 ISMT_INIT_INTR_EN = 1 << 5,
85 ISMT_INIT_I2C = 1 << 6
86 } ismt_init_t;
87
88 typedef struct {
89 ddi_dma_handle_t id_hdl;
90 caddr_t id_va;
91 ddi_acc_handle_t id_acc;
92 size_t id_alloc_len;
93 size_t id_size;
94 } ismt_dma_t;
95
96 typedef struct {
97 dev_info_t *ismt_dip;
98 ddi_acc_handle_t ismt_cfg;
99 ismt_init_t ismt_init;
100 /*
101 * Register related data
102 */
103 caddr_t ismt_base;
104 off_t ismt_regsize;
105 ddi_acc_handle_t ismt_regs;
106 /*
107 * DMA Information
108 */
109 ismt_dma_t ismt_ring_dma;
110 ismt_dma_t ismt_data_dma;
111 ismt_dma_t ismt_icl_dma;
112 /*
113 * Interrupt data
114 */
115 int ismt_nintrs;
116 int ismt_itype;
117 ddi_intr_handle_t ismt_intr_hdl;
118 uint_t ismt_intr_pri;
119 /*
120 * Request and framework synchronization.
121 */
122 i2c_speed_t ismt_speed;
123 kmutex_t ismt_mutex;
124 kcondvar_t ismt_cv;
125 i2c_ctrl_hdl_t *ismt_hdl;
126 uint32_t ismt_head;
127 uint32_t ismt_tail;
128 ismt_desc_t *ismt_ring;
129 smbus_req_t *ismt_req;
130 i2c_req_t *ismt_i2creq;
131 i2c_error_t *ismt_err;
132 bool ismt_req_done;
133 } ismt_t;
134
135 /*
136 * Consolidated DMA attributes for the descriptor ring and the data buffer. We
137 * use the stricter requirements from each because we don't actually allocate
138 * that much DMA memory here to make this simpler.
139 */
140 static const ddi_dma_attr_t ismt_dma_attr = {
141 .dma_attr_version = DMA_ATTR_V0,
142 /*
143 * Our DMA attributes can appear anywhere in 64-bit space.
144 */
145 .dma_attr_addr_lo = 0,
146 .dma_attr_addr_hi = UINT64_MAX,
147 /*
148 * Up to 255 bytes are allowed to be specified for transmit / recieve,
149 * where as the descriptor ring allows for up to 256 16 byte
150 * descriptors. We use the latter for here, with the knowledge that
151 * we're never allocating more than an amount that can fit due to the
152 * maxxfer value below.
153 */
154 .dma_attr_count_max = 256 * sizeof (ismt_desc_t),
155 /*
156 * The descriptor ring requires 64 byte alignment, where as the data
157 * buffer requires byte alignment. Use 64 byte alignment.
158 */
159 .dma_attr_align = 0x40,
160 /*
161 * Cargo culted burst sizes as PCIe probably doens't have quite the same
162 * concerns.
163 */
164 .dma_attr_burstsizes = 0xfff,
165 /*
166 * We set the minimum and maximum to the sizes here. The size limits are
167 * really set by PCIe breaking up transactions, not anything in the
168 * kernel. Therefore we set the maximum to the same as
169 * dma_attr_count_max, partially so we can avoid complaints about DMA
170 * less than a page by x86 rootnex.
171 */
172 .dma_attr_minxfer = 1,
173 .dma_attr_maxxfer = 256 * sizeof (ismt_desc_t),
174 /*
175 * Their are no segment restrictions and only one cookie can be used.
176 * For the granularity we basically set this to 1 because everything we
177 * allocate will be a multiple of this and we only have one cookie so it
178 * won't really be split..
179 */
180 .dma_attr_seg = UINT64_MAX,
181 .dma_attr_sgllen = 1,
182 .dma_attr_granular = 1,
183 .dma_attr_flags = 0
184 };
185
186 static uint32_t
ismt_read32(ismt_t * ismt,uint32_t reg)187 ismt_read32(ismt_t *ismt, uint32_t reg)
188 {
189 ASSERT3U(reg, <, ismt->ismt_regsize);
190 return (ddi_get32(ismt->ismt_regs, (uint32_t *)(ismt->ismt_base +
191 reg)));
192 }
193
194 static void
ismt_write32(ismt_t * ismt,uint32_t reg,uint32_t val)195 ismt_write32(ismt_t *ismt, uint32_t reg, uint32_t val)
196 {
197 ASSERT3U(reg, <, ismt->ismt_regsize);
198 ddi_put32(ismt->ismt_regs, (uint32_t *)(ismt->ismt_base + reg), val);
199 }
200
201 static void
ismt_write64(ismt_t * ismt,uint32_t reg,uint64_t val)202 ismt_write64(ismt_t *ismt, uint32_t reg, uint64_t val)
203 {
204 ASSERT3U(reg, <, ismt->ismt_regsize);
205 ddi_put64(ismt->ismt_regs, (uint64_t *)(ismt->ismt_base + reg), val);
206 }
207
208 static i2c_errno_t
ismt_prop_info(void * arg,i2c_prop_t prop,i2c_prop_info_t * info)209 ismt_prop_info(void *arg, i2c_prop_t prop, i2c_prop_info_t *info)
210 {
211 switch (prop) {
212 case I2C_PROP_BUS_SPEED:
213 i2c_prop_info_set_pos_bit32(info, I2C_SPEED_STD |
214 I2C_SPEED_FAST | I2C_SPEED_FPLUS);
215 break;
216 case SMBUS_PROP_SUP_OPS:
217 case I2C_PROP_MAX_READ:
218 case I2C_PROP_MAX_WRITE:
219 case SMBUS_PROP_MAX_BLOCK:
220 break;
221 default:
222 return (I2C_PROP_E_UNSUP);
223 }
224
225 i2c_prop_info_set_perm(info, I2C_PROP_PERM_RO);
226
227 return (I2C_CORE_E_OK);
228 }
229
230 /*
231 * Currently all the information that we return is static. If this changes, we
232 * should ensure we hold ismt_mutex during this.
233 */
234 static i2c_errno_t
ismt_prop_get(void * arg,i2c_prop_t prop,void * buf,size_t buflen)235 ismt_prop_get(void *arg, i2c_prop_t prop, void *buf, size_t buflen)
236 {
237 ismt_t *ismt = arg;
238 uint32_t val;
239
240 switch (prop) {
241 case I2C_PROP_BUS_SPEED:
242 val = ismt->ismt_speed;
243 break;
244 case SMBUS_PROP_SUP_OPS:
245 val = SMBUS_PROP_OP_QUICK_COMMAND | SMBUS_PROP_OP_SEND_BYTE |
246 SMBUS_PROP_OP_RECV_BYTE | SMBUS_PROP_OP_WRITE_BYTE |
247 SMBUS_PROP_OP_READ_BYTE | SMBUS_PROP_OP_WRITE_WORD |
248 SMBUS_PROP_OP_READ_WORD | SMBUS_PROP_OP_PROCESS_CALL |
249 SMBUS_PROP_OP_WRITE_BLOCK | SMBUS_PROP_OP_READ_BLOCK |
250 SMBUS_PROP_OP_BLOCK_PROCESS_CALL |
251 SMBUS_PROP_OP_I2C_WRITE_BLOCK |
252 SMBUS_PROP_OP_I2C_READ_BLOCK;
253 break;
254 case I2C_PROP_MAX_READ:
255 case I2C_PROP_MAX_WRITE:
256 val = ISMT_MAX_I2C;
257 break;
258 case SMBUS_PROP_MAX_BLOCK:
259 val = ISMT_MAX_SMBUS;
260 break;
261 default:
262 return (I2C_PROP_E_UNSUP);
263 }
264
265 VERIFY3U(buflen, >=, sizeof (val));
266 bcopy(&val, buf, sizeof (val));
267 return (I2C_CORE_E_OK);
268 }
269
270 static void
ismt_io_error(ismt_t * ismt,uint32_t sts)271 ismt_io_error(ismt_t *ismt, uint32_t sts)
272 {
273 i2c_ctrl_error_t err;
274 VERIFY3P(ismt->ismt_err, !=, NULL);
275
276 if (ISMT_DESC_STS_GET_NACK(sts) != 0) {
277 if (ISMT_DESC_STS_GET_WRLEN(sts) == 0) {
278 err = I2C_CTRL_E_ADDR_NACK;
279 } else {
280 err = I2C_CTRL_E_DATA_NACK;
281 }
282 } else if (ISMT_DESC_STS_GET_CRC(sts) != 0) {
283 /*
284 * As we don't enable PEC right now, we don't expect to see
285 * this. When we do, then this should be changed.
286 */
287 err = I2C_CTRL_E_DRIVER;
288 } else if (ISMT_DESC_STS_GET_CLTO(sts) != 0) {
289 err = I2C_CTRL_E_SMBUS_CLOCK_LOW;
290 } else if (ISMT_DESC_STS_GET_COL(sts) != 0) {
291 err = I2C_CTRL_E_ARB_LOST;
292 } else if (ISMT_DESC_STS_GET_LPR(sts) != 0) {
293 err = I2C_CTRL_E_DRIVER;
294 } else {
295 err = I2C_CTRL_E_INTERNAL;
296 }
297
298 i2c_ctrl_io_error(ismt->ismt_err, I2C_CORE_E_CONTROLLER, err);
299 }
300
301 /*
302 * Process the current completion.
303 */
304 static void
ismt_io(ismt_t * ismt)305 ismt_io(ismt_t *ismt)
306 {
307 ismt_desc_t *desc;
308 uint32_t sts;
309
310 VERIFY(MUTEX_HELD(&ismt->ismt_mutex));
311 ISMT_DMA_SYNC(ismt->ismt_ring_dma, DDI_DMA_SYNC_FORKERNEL);
312 ISMT_DMA_SYNC(ismt->ismt_data_dma, DDI_DMA_SYNC_FORKERNEL);
313 desc = &ismt->ismt_ring[ismt->ismt_tail];
314 ismt->ismt_tail = (ismt->ismt_tail + 1) % ISMT_RING_NENTS;
315 const uint8_t *buf = (uint8_t *)ismt->ismt_data_dma.id_va;
316
317 sts = LE_32(desc->id_status);
318 if (ISMT_DESC_STS_GET_SCS(sts) == 0) {
319 ismt_io_error(ismt, sts);
320 return;
321 }
322
323 if (ismt->ismt_i2creq != NULL) {
324 VERIFY3P(ismt->ismt_req, ==, NULL);
325 if (ismt->ismt_i2creq->ir_rlen > 0) {
326 VERIFY3U(ismt->ismt_i2creq->ir_rlen, ==,
327 ISMT_DESC_STS_GET_RDLEN(sts));
328 bcopy(buf, ismt->ismt_i2creq->ir_rdata,
329 ISMT_DESC_STS_GET_RDLEN(sts));
330 }
331 i2c_ctrl_io_success(ismt->ismt_err);
332 return;
333 }
334
335 switch (ismt->ismt_req->smbr_op) {
336 case SMBUS_OP_QUICK_COMMAND:
337 case SMBUS_OP_SEND_BYTE:
338 case SMBUS_OP_WRITE_BYTE:
339 case SMBUS_OP_WRITE_WORD:
340 case SMBUS_OP_WRITE_BLOCK:
341 case SMBUS_OP_I2C_WRITE_BLOCK:
342 /*
343 * Nothing to do for writes.
344 */
345 break;
346 case SMBUS_OP_RECV_BYTE:
347 case SMBUS_OP_READ_BYTE:
348 ismt->ismt_req->smbr_rdata[0] = buf[0];
349 break;
350 case SMBUS_OP_READ_WORD:
351 case SMBUS_OP_PROCESS_CALL:
352 ismt->ismt_req->smbr_rdata[0] = buf[0];
353 ismt->ismt_req->smbr_rdata[1] = buf[1];
354 break;
355 case SMBUS_OP_READ_BLOCK:
356 case SMBUS_OP_BLOCK_PROCESS_CALL:
357 if (ISMT_DESC_STS_GET_RDLEN(sts) != buf[0] + 1) {
358 i2c_ctrl_io_error(ismt->ismt_err, I2C_CORE_E_CONTROLLER,
359 I2C_CTRL_E_DRIVER);
360 return;
361 }
362 ismt->ismt_req->smbr_rlen = buf[0];
363 bcopy(&buf[1], ismt->ismt_req->smbr_rdata, buf[0]);
364 break;
365 case SMBUS_OP_I2C_READ_BLOCK:
366 bcopy(buf, ismt->ismt_req->smbr_rdata,
367 ISMT_DESC_STS_GET_RDLEN(sts));
368 break;
369 case SMBUS_OP_WRITE_U32:
370 case SMBUS_OP_WRITE_U64:
371 case SMBUS_OP_READ_U32:
372 case SMBUS_OP_READ_U64:
373 case SMBUS_OP_HOST_NOTIFY:
374 default:
375 panic("programmer error: unsupported request type 0x%x should "
376 "not have been completed", ismt->ismt_req->smbr_op);
377 }
378
379 i2c_ctrl_io_success(ismt->ismt_err);
380 }
381
382 /*
383 * When we're using MSI interrupts then the hardware will automatically clear
384 * the controller's interrupt status register based on our configuration.
385 * However if we're using INTx, then we will need to take care of reading the
386 * various status registers and checking what has happened.
387 *
388 * One nice thing is that we'll otherwise always get an interrupt when the whole
389 * operation is done.
390 */
391 static uint_t
ismt_intr(caddr_t arg1,caddr_t arg2)392 ismt_intr(caddr_t arg1, caddr_t arg2)
393 {
394 ismt_t *ismt = (ismt_t *)arg1;
395 uint32_t msts;
396 bool mis, meis;
397
398 mutex_enter(&ismt->ismt_mutex);
399 if (ismt->ismt_itype == DDI_INTR_TYPE_FIXED) {
400 msts = ismt_read32(ismt, ISMT_R_MSTS);
401 mis = ISMT_R_MSTS_GET_MIS(msts);
402 meis = ISMT_R_MSTS_GET_MEIS(msts);
403
404 if (!mis && !meis) {
405 mutex_exit(&ismt->ismt_mutex);
406 return (DDI_INTR_UNCLAIMED);
407 }
408 ismt_write32(ismt, ISMT_R_MSTS, msts);
409 }
410
411 ismt_io(ismt);
412 ismt->ismt_req_done = true;
413 cv_signal(&ismt->ismt_cv);
414 mutex_exit(&ismt->ismt_mutex);
415 return (DDI_INTR_CLAIMED);
416 }
417
418 static void
ismt_wait(ismt_t * ismt)419 ismt_wait(ismt_t *ismt)
420 {
421 VERIFY(MUTEX_HELD(&ismt->ismt_mutex));
422 VERIFY(ismt->ismt_req == NULL || ismt->ismt_i2creq == NULL);
423 VERIFY3P(ismt->ismt_req, !=, ismt->ismt_i2creq);
424
425 uint32_t to = i2c_ctrl_timeout_delay_us(ismt->ismt_hdl, I2C_CTRL_TO_IO);
426 clock_t abs = ddi_get_lbolt() + drv_usectohz(to);
427 while (!ismt->ismt_req_done) {
428 clock_t ret = cv_timedwait(&ismt->ismt_cv, &ismt->ismt_mutex,
429 abs);
430 if (ret == -1) {
431 break;
432 }
433 }
434
435 /*
436 * The command timed out. We need to set the KILL bit, complete the
437 * transaction, and go from there.
438 */
439 if (!ismt->ismt_req_done) {
440 uint32_t val = ISMT_R_GCTRL_SET_KILL(0, 1);
441 ismt_write32(ismt, ISMT_R_GCTRL, val);
442 i2c_ctrl_io_error(ismt->ismt_err, I2C_CORE_E_CONTROLLER,
443 I2C_CTRL_E_REQ_TO);
444 ismt->ismt_req_done = true;
445 }
446 }
447
448 static void
ismt_io_reset(ismt_t * ismt)449 ismt_io_reset(ismt_t *ismt)
450 {
451 VERIFY(MUTEX_HELD(&ismt->ismt_mutex));
452 bzero(ismt->ismt_data_dma.id_va, ISMT_DATA_BUF_SIZE);
453 bzero(ismt->ismt_icl_dma.id_va, ISMT_ICL_DMA_SIZE);
454 ismt->ismt_req = NULL;
455 ismt->ismt_i2creq = NULL;
456 ismt->ismt_err = NULL;
457 ismt->ismt_req_done = false;
458 }
459
460 /*
461 * Set the things that are common across all I/O requests: the address, the
462 * request for the fair bit, and ask for an interrupt. Hardware will ownly honor
463 * the bit if we're using MSIs and otherwise will always inject the interrupt,
464 * so we set this regardless.
465 */
466 static void
ismt_io_cmd_init(const i2c_addr_t * addr,uint32_t * cmdp)467 ismt_io_cmd_init(const i2c_addr_t *addr, uint32_t *cmdp)
468 {
469 uint32_t cmd;
470
471 ASSERT3U(addr->ia_type, ==, I2C_ADDR_7BIT);
472 cmd = ISMT_DESC_CMD_SET_ADDR(0, addr->ia_addr);
473 cmd = ISMT_DESC_CMD_SET_INT(cmd, 1);
474 cmd = ISMT_DESC_CMD_SET_FAIR(cmd, 1);
475 *cmdp = cmd;
476 }
477
478 static void
ismt_io_cmd_submit(ismt_t * ismt,uint32_t cmd,bool data)479 ismt_io_cmd_submit(ismt_t *ismt, uint32_t cmd, bool data)
480 {
481 ismt_desc_t *desc;
482
483 VERIFY(MUTEX_HELD(&ismt->ismt_mutex));
484 desc = &ismt->ismt_ring[ismt->ismt_head];
485 bzero(desc, sizeof (desc));
486
487 desc->id_cmd_addr = LE_32(cmd);
488 if (data) {
489 const ddi_dma_cookie_t *c;
490
491 c = ddi_dma_cookie_one(ismt->ismt_data_dma.id_hdl);
492 desc->id_low = LE_32(bitx64(c->dmac_laddress, 31, 0));
493 desc->id_high = LE_32(bitx64(c->dmac_laddress, 63, 32));
494 ISMT_DMA_SYNC(ismt->ismt_data_dma, DDI_DMA_SYNC_FORDEV);
495 }
496 ISMT_DMA_SYNC(ismt->ismt_ring_dma, DDI_DMA_SYNC_FORDEV);
497
498 /*
499 * Proceed to tell hardware to process this command. The datasheet
500 * suggests we need to update the descriptor pointer and then come back
501 * and ask the hardware to start as we can't set SS until at least one
502 * descriptor has been programmed.
503 */
504 ismt->ismt_head = (ismt->ismt_head + 1) % ISMT_RING_NENTS;
505 uint32_t mctrl = ismt_read32(ismt, ISMT_R_MCTRL);
506 mctrl = ISMT_R_MCTRL_SET_FMHP(mctrl, ismt->ismt_head);
507 ismt_write32(ismt, ISMT_R_MCTRL, mctrl);
508 mctrl = ISMT_R_MCTRL_SET_SS(mctrl, 1);
509 ismt_write32(ismt, ISMT_R_MCTRL, mctrl);
510
511 /*
512 * The command is running. We now need to wait for an interrupt or poll
513 * for completion. Unlike other drivers, we always have the interrupt
514 * enabled, which means we can't really poll.
515 */
516 ismt_wait(ismt);
517 }
518
519 static void
ismt_io_smbus(void * arg,uint32_t port,smbus_req_t * req)520 ismt_io_smbus(void *arg, uint32_t port, smbus_req_t *req)
521 {
522 ismt_t *ismt = arg;
523 uint8_t *buf;
524 uint32_t cmd;
525 bool data = false;
526
527 mutex_enter(&ismt->ismt_mutex);
528 ismt_io_reset(ismt);
529 ismt->ismt_req = req;
530 ismt->ismt_err = &req->smbr_error;
531
532 buf = (uint8_t *)ismt->ismt_data_dma.id_va;
533
534 /*
535 * Set up the descriptor. In particualr we need to determine whether to
536 * set:
537 *
538 * - The read address bit (default is write)
539 * - The block request bit
540 * - The C/WRL bit which determines whether the write field is the
541 * command.
542 * - The read and write length, if non-zero.
543 * - Whether we are going to use the data pointer and if we need to do
544 * anyhting to get it ready
545 *
546 * The read address bit and whether we use data are bools that we apply
547 * at the end.
548 */
549 ismt_io_cmd_init(&req->smbr_addr, &cmd);
550 switch (req->smbr_op) {
551 case SMBUS_OP_QUICK_COMMAND:
552 if ((req->smbr_flags & I2C_IO_REQ_F_QUICK_WRITE) != 0) {
553 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
554 } else {
555 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
556 }
557 break;
558 case SMBUS_OP_SEND_BYTE:
559 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
560 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
561 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_wdata[0]);
562 break;
563 case SMBUS_OP_WRITE_BYTE:
564 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
565 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, 2);
566 data = true;
567 buf[0] = req->smbr_cmd;
568 buf[1] = req->smbr_wdata[0];
569 break;
570 case SMBUS_OP_WRITE_WORD:
571 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
572 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, 3);
573 data = true;
574 buf[0] = req->smbr_cmd;
575 buf[1] = req->smbr_wdata[0];
576 buf[2] = req->smbr_wdata[1];
577 break;
578 case SMBUS_OP_WRITE_BLOCK:
579 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
580 cmd = ISMT_DESC_CMD_SET_BLK(cmd, 1);
581 VERIFY3U(req->smbr_wlen, <=, ISMT_MAX_SMBUS);
582 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_wlen + 1);
583 data = true;
584 buf[0] = req->smbr_cmd;
585 bcopy(req->smbr_wdata, &buf[1], req->smbr_wlen);
586 break;
587 case SMBUS_OP_I2C_WRITE_BLOCK:
588 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
589 cmd = ISMT_DESC_CMD_SET_I2C(cmd, 1);
590 VERIFY3U(req->smbr_wlen, >, 0);
591 VERIFY3U(req->smbr_wlen, <=, ISMT_MAX_I2C);
592 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_wlen + 1);
593 data = true;
594 buf[0] = req->smbr_cmd;
595 bcopy(req->smbr_wdata, &buf[1], req->smbr_wlen);
596 break;
597 case SMBUS_OP_RECV_BYTE:
598 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
599 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, 1);
600 data = true;
601 break;
602 case SMBUS_OP_READ_BYTE:
603 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
604 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
605 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_cmd);
606 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, 1);
607 data = true;
608 break;
609 case SMBUS_OP_READ_WORD:
610 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
611 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
612 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_cmd);
613 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, 2);
614 data = true;
615 break;
616 case SMBUS_OP_READ_BLOCK:
617 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
618 cmd = ISMT_DESC_CMD_SET_BLK(cmd, 1);
619 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
620 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_cmd);
621 VERIFY3U(req->smbr_rlen, >, 0);
622 VERIFY3U(req->smbr_rlen, <=, ISMT_MAX_SMBUS);
623 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, req->smbr_rlen + 1);
624 data = true;
625 break;
626 case SMBUS_OP_I2C_READ_BLOCK:
627 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
628 cmd = ISMT_DESC_CMD_SET_I2C(cmd, 1);
629 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
630 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_cmd);
631 VERIFY3U(req->smbr_rlen, >, 0);
632 VERIFY3U(req->smbr_rlen, <=, ISMT_MAX_I2C);
633 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, req->smbr_rlen);
634 data = true;
635 break;
636 case SMBUS_OP_PROCESS_CALL:
637 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
638 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, 3);
639 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, 2);
640 data = true;
641 buf[0] = req->smbr_cmd;
642 buf[1] = req->smbr_wdata[0];
643 buf[2] = req->smbr_wdata[1];
644 break;
645 case SMBUS_OP_BLOCK_PROCESS_CALL:
646 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
647 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->smbr_wlen + 1);
648 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, req->smbr_rlen + 1);
649 data = true;
650 buf[0] = req->smbr_cmd;
651 bcopy(req->smbr_wdata, &buf[1], req->smbr_wlen);
652 break;
653 /*
654 * As the datasheets don't have a way to directly run the U32/U64
655 * operations, we allow our translation layer to take care of it.
656 */
657 case SMBUS_OP_READ_U32:
658 case SMBUS_OP_READ_U64:
659 case SMBUS_OP_WRITE_U32:
660 case SMBUS_OP_WRITE_U64:
661 case SMBUS_OP_HOST_NOTIFY:
662 default:
663 dev_err(ismt->ismt_dip, CE_WARN, "!framework passed "
664 "unsupported SMBus command 0x%x", req->smbr_op);
665 i2c_ctrl_io_error(&req->smbr_error, I2C_CORE_E_CONTROLLER,
666 I2C_CTRL_E_UNSUP_CMD);
667 goto done;
668
669 }
670
671 ismt_io_cmd_submit(ismt, cmd, data);
672 done:
673 ismt->ismt_req = NULL;
674 ismt->ismt_i2creq = NULL;
675 ismt->ismt_err = NULL;
676 ismt->ismt_req_done = false;
677 mutex_exit(&ismt->ismt_mutex);
678 }
679
680 static void
ismt_io_i2c(void * arg,uint32_t port,i2c_req_t * req)681 ismt_io_i2c(void *arg, uint32_t port, i2c_req_t *req)
682 {
683 ismt_t *ismt = arg;
684 uint8_t *buf;
685 uint32_t cmd;
686 bool data = false;
687
688 mutex_enter(&ismt->ismt_mutex);
689 ismt_io_reset(ismt);
690 ismt->ismt_i2creq = req;
691 ismt->ismt_err = &req->ir_error;
692
693 buf = (uint8_t *)ismt->ismt_data_dma.id_va;
694
695 /*
696 * I2C Commands are required to always set the I2C bit and we must never
697 * set the block bit. The remaining flags and set up depend on whether
698 * we're doing a write, a read, or a write folowed by a read.
699 */
700 ismt_io_cmd_init(&req->ir_addr, &cmd);
701 cmd = ISMT_DESC_CMD_SET_I2C(cmd, 1);
702 cmd = ISMT_DESC_CMD_SET_BLK(cmd, 0);
703
704 if (req->ir_rlen > 0) {
705 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_READ);
706 VERIFY3U(req->ir_rlen, <, ISMT_MAX_I2C);
707 data = true;
708 cmd = ISMT_DESC_CMD_SET_RDLEN(cmd, req->ir_rlen);
709 }
710
711 if (req->ir_wlen > 0) {
712 cmd = ISMT_DESC_CMD_SET_RW(cmd, ISMT_DESC_CMD_RW_WRITE);
713
714 /*
715 * The datasheet tells us that if we have a 1 byte write, we
716 * need to set C/WRL and it will encode the data byte. Otherwise
717 * we use the normal write length.
718 */
719 if (req->ir_wlen == 1) {
720 cmd = ISMT_DESC_CMD_SET_CWRL(cmd, 1);
721 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->ir_wdata[0]);
722 } else {
723 VERIFY3U(req->ir_wlen, >, 0);
724 VERIFY3U(req->ir_wlen, <, ISMT_MAX_I2C);
725 cmd = ISMT_DESC_CMD_SET_WRLEN(cmd, req->ir_wlen);
726 data = true;
727 bcopy(req->ir_wdata, buf, req->ir_wlen);
728 }
729 }
730
731 ismt_io_cmd_submit(ismt, cmd, data);
732
733 ismt->ismt_req = NULL;
734 ismt->ismt_i2creq = NULL;
735 ismt->ismt_req_done = false;
736 mutex_exit(&ismt->ismt_mutex);
737 }
738
739 static const i2c_ctrl_ops_t ismt_ctrl_ops = {
740 .i2c_port_name_f = i2c_ctrl_port_name_portno,
741 .i2c_io_i2c_f = ismt_io_i2c,
742 .i2c_io_smbus_f = ismt_io_smbus,
743 .i2c_prop_info_f = ismt_prop_info,
744 .i2c_prop_get_f = ismt_prop_get
745 };
746
747 static bool
ismt_setup_regs(ismt_t * ismt)748 ismt_setup_regs(ismt_t *ismt)
749 {
750 int ret;
751 ddi_device_acc_attr_t attr;
752
753 bzero(&attr, sizeof (attr));
754 attr.devacc_attr_version = DDI_DEVICE_ATTR_V1;
755 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
756 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
757 attr.devacc_attr_access = DDI_DEFAULT_ACC;
758
759 if (ddi_dev_regsize(ismt->ismt_dip, ISMT_REGNO, &ismt->ismt_regsize) !=
760 DDI_SUCCESS) {
761 dev_err(ismt->ismt_dip, CE_WARN, "failed to get regs[%u] size",
762 ISMT_REGNO);
763 return (false);
764 }
765
766 ret = ddi_regs_map_setup(ismt->ismt_dip, ISMT_REGNO, &ismt->ismt_base,
767 0, ismt->ismt_regsize, &attr, &ismt->ismt_regs);
768 if (ret != DDI_SUCCESS) {
769 dev_err(ismt->ismt_dip, CE_WARN, "failed to map regs[%u]: %u",
770 ISMT_REGNO, ret);
771 return (false);
772 }
773
774 ismt->ismt_init |= ISMT_INIT_REGS;
775 return (true);
776 }
777
778 static void
ismt_dma_free(ismt_dma_t * dma)779 ismt_dma_free(ismt_dma_t *dma)
780 {
781 /* Proxy for DMA handle bound */
782 if (dma->id_size != 0) {
783 (void) ddi_dma_unbind_handle(dma->id_hdl);
784 dma->id_size = 0;
785 }
786
787 if (dma->id_acc != NULL) {
788 ddi_dma_mem_free(&dma->id_acc);
789 dma->id_acc = NULL;
790 dma->id_va = NULL;
791 dma->id_alloc_len = 0;
792 }
793
794 if (dma->id_hdl != NULL) {
795 ddi_dma_free_handle(&dma->id_hdl);
796 dma->id_hdl = NULL;
797 }
798
799 ASSERT0(dma->id_size);
800 ASSERT0(dma->id_alloc_len);
801 ASSERT3P(dma->id_acc, ==, NULL);
802 ASSERT3P(dma->id_hdl, ==, NULL);
803 ASSERT3P(dma->id_va, ==, NULL);
804 }
805
806 static bool
ismt_dma_alloc(ismt_t * ismt,ismt_dma_t * dma,size_t size)807 ismt_dma_alloc(ismt_t *ismt, ismt_dma_t *dma, size_t size)
808 {
809 int ret;
810 ddi_device_acc_attr_t acc;
811 uint_t flags = DDI_DMA_CONSISTENT;
812
813 bzero(dma, sizeof (ismt_dma_t));
814 ret = ddi_dma_alloc_handle(ismt->ismt_dip, &ismt_dma_attr,
815 DDI_DMA_SLEEP, NULL, &dma->id_hdl);
816 if (ret != DDI_SUCCESS) {
817 dev_err(ismt->ismt_dip, CE_WARN, "!failed to allocate DMA "
818 "handle: %d", ret);
819 return (false);
820 }
821
822 bzero(&acc, sizeof (acc));
823 acc.devacc_attr_version = DDI_DEVICE_ATTR_V1;
824 acc.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
825 acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
826 acc.devacc_attr_access = DDI_DEFAULT_ACC;
827 ret = ddi_dma_mem_alloc(dma->id_hdl, size, &acc, flags,
828 DDI_DMA_SLEEP, NULL, &dma->id_va, &dma->id_alloc_len,
829 &dma->id_acc);
830 if (ret != DDI_SUCCESS) {
831 dev_err(ismt->ismt_dip, CE_WARN, "!failed to allocate %lu "
832 "bytes of DMA memory: %d", size, ret);
833 ismt_dma_free(dma);
834 return (false);
835 }
836
837 bzero(dma->id_va, dma->id_alloc_len);
838 ret = ddi_dma_addr_bind_handle(dma->id_hdl, NULL, dma->id_va,
839 dma->id_alloc_len, DDI_DMA_RDWR | flags, DDI_DMA_DONTWAIT, NULL,
840 NULL, NULL);
841 if (ret != DDI_SUCCESS) {
842 dev_err(ismt->ismt_dip, CE_WARN, "!failed to bind %lu bytes of "
843 "DMA memory: %d", dma->id_alloc_len, ret);
844 ismt_dma_free(dma);
845 return (false);
846 }
847
848 dma->id_size = size;
849 return (true);
850 }
851
852 static bool
ismt_alloc_intr(ismt_t * ismt)853 ismt_alloc_intr(ismt_t *ismt)
854 {
855 int ret, types;
856
857 ret = ddi_intr_get_supported_types(ismt->ismt_dip, &types);
858 if (ret != DDI_SUCCESS) {
859 dev_err(ismt->ismt_dip, CE_WARN, "failed to get supproted "
860 "interrupt types: 0x%d", ret);
861 return (false);
862 }
863
864 /*
865 * We only expect hardware to support MSIs and INTx.
866 */
867 if ((types & DDI_INTR_TYPE_MSI) != 0) {
868 ret = ddi_intr_alloc(ismt->ismt_dip, &ismt->ismt_intr_hdl,
869 DDI_INTR_TYPE_MSI, 0, 1, &ismt->ismt_nintrs,
870 DDI_INTR_ALLOC_STRICT);
871 if (ret == DDI_SUCCESS) {
872 ismt->ismt_itype = DDI_INTR_TYPE_MSI;
873 return (true);
874 }
875 dev_err(ismt->ismt_dip, CE_WARN, "!failed to allocate MSI "
876 "interrupt");
877 }
878
879 if ((types & DDI_INTR_TYPE_FIXED) != 0) {
880 ret = ddi_intr_alloc(ismt->ismt_dip, &ismt->ismt_intr_hdl,
881 DDI_INTR_TYPE_MSI, 0, 1, &ismt->ismt_nintrs,
882 DDI_INTR_ALLOC_STRICT);
883 if (ret == DDI_SUCCESS) {
884 ismt->ismt_itype = DDI_INTR_TYPE_FIXED;
885 return (true);
886 }
887 dev_err(ismt->ismt_dip, CE_WARN, "!failed to allocate INTx "
888 "interrupt");
889 }
890
891 dev_err(ismt->ismt_dip, CE_WARN, "failed to allocate any interrupts "
892 "from type 0x%x", types);
893 return (false);
894 }
895
896 static bool
ismt_setup_intr(ismt_t * ismt)897 ismt_setup_intr(ismt_t *ismt)
898 {
899 int ret = ddi_intr_add_handler(ismt->ismt_intr_hdl, ismt_intr, ismt,
900 NULL);
901 if (ret != DDI_SUCCESS) {
902 dev_err(ismt->ismt_dip, CE_WARN, "failed to add interrupt "
903 "handler: 0x%x", ret);
904 return (false);
905 }
906 ismt->ismt_init |= ISMT_INIT_INTR_HDL;
907
908 ret = ddi_intr_get_pri(ismt->ismt_intr_hdl, &ismt->ismt_intr_pri);
909 if (ret != DDI_SUCCESS) {
910 dev_err(ismt->ismt_dip, CE_WARN, "failed to get interrupt "
911 "priority");
912 return (false);
913 }
914
915 return (true);
916 }
917
918 /*
919 * Go through and set up hardware for use. We need to explicitly take care of:
920 *
921 * - The Interrupt Cause Log
922 * - The Controller DMA ring
923 * - Firmware Head and Tail Registers
924 * - Enabling generation of interrupts
925 *
926 * We use the hardwar defaults for the device retry policy.
927 */
928 static void
ismt_ctrl_init(ismt_t * ismt)929 ismt_ctrl_init(ismt_t *ismt)
930 {
931 uint32_t val;
932 const ddi_dma_cookie_t *c;
933
934 c = ddi_dma_cookie_one(ismt->ismt_icl_dma.id_hdl);
935 ismt_write64(ismt, ISMT_R_SMTICL, c->dmac_laddress);
936
937 c = ddi_dma_cookie_one(ismt->ismt_ring_dma.id_hdl);
938 ismt_write64(ismt, ISMT_R_MDBA, c->dmac_laddress);
939
940 val = ISMT_R_MDS_SET_SIZE(0, ISMT_RING_NENTS - 1);
941 ismt_write32(ismt, ISMT_R_MDS, val);
942
943 val = ISMT_R_MCTRL_SET_FMHP(0, 0);
944 val = ISMT_R_MCTRL_SET_MEIE(val, 1);
945 ismt_write32(ismt, ISMT_R_MCTRL, val);
946
947 val = ISMT_R_MSTS_SET_HMTP(0, 0);
948 ismt_write32(ismt, ISMT_R_MSTS, val);
949
950 ismt->ismt_head = ismt->ismt_tail = 0;
951 ismt->ismt_ring = (ismt_desc_t *)ismt->ismt_ring_dma.id_va;
952
953 val = ismt_read32(ismt, ISMT_R_SPGT);
954 switch (ISMT_R_SPGT_GET_SPD(val)) {
955 case ISMT_R_SPT_SPD_80K:
956 case ISMT_R_SPT_SPD_100K:
957 ismt->ismt_speed = I2C_SPEED_STD;
958 break;
959 case ISMT_R_SPT_SPD_400K:
960 ismt->ismt_speed = I2C_SPEED_FAST;
961 break;
962 case ISMT_R_SPT_SPD_1M:
963 ismt->ismt_speed = I2C_SPEED_FPLUS;
964 break;
965 }
966 }
967
968 static bool
ismt_enable_intr(ismt_t * ismt)969 ismt_enable_intr(ismt_t *ismt)
970 {
971 int ret = ddi_intr_enable(ismt->ismt_intr_hdl);
972 if (ret != DDI_SUCCESS) {
973 dev_err(ismt->ismt_dip, CE_WARN, "failed to enable interrupt "
974 "handler: %d", ret);
975 return (false);
976 }
977
978 ismt->ismt_init |= ISMT_INIT_INTR_EN;
979 return (true);
980 }
981
982 static bool
ismt_register(ismt_t * ismt)983 ismt_register(ismt_t *ismt)
984 {
985 i2c_ctrl_reg_error_t ret;
986 i2c_ctrl_register_t *reg;
987
988 ret = i2c_ctrl_register_alloc(I2C_CTRL_PROVIDER, ®);
989 if (ret != 0) {
990 dev_err(ismt->ismt_dip, CE_WARN, "failed to allocate i2c "
991 "controller registration structure: 0x%x", ret);
992 return (false);
993 }
994
995 reg->ic_type = I2C_CTRL_TYPE_SMBUS;
996 reg->ic_nports = 1;
997 reg->ic_dip = ismt->ismt_dip;
998 reg->ic_drv = ismt;
999 reg->ic_ops = &ismt_ctrl_ops;
1000
1001 ret = i2c_ctrl_register(reg, &ismt->ismt_hdl);
1002 i2c_ctrl_register_free(reg);
1003 if (ret != 0) {
1004 dev_err(ismt->ismt_dip, CE_WARN, "failed to register with i2c "
1005 "framework: 0x%x", ret);
1006 return (false);
1007 }
1008 ismt->ismt_init |= ISMT_INIT_I2C;
1009
1010 return (true);
1011 }
1012
1013 static void
ismt_cleanup(ismt_t * ismt)1014 ismt_cleanup(ismt_t *ismt)
1015 {
1016 if ((ismt->ismt_init & ISMT_INIT_INTR_EN) != 0) {
1017 /*
1018 * If this fails while tearing down, there isn't much we can do.
1019 */
1020 int ret = ddi_intr_disable(ismt->ismt_intr_hdl);
1021 if (ret != DDI_SUCCESS) {
1022 dev_err(ismt->ismt_dip, CE_WARN, "failed to disable "
1023 "interrupt handler: %d", ret);
1024 }
1025
1026 ismt->ismt_init &= ~ISMT_INIT_INTR_EN;
1027 }
1028
1029 if ((ismt->ismt_init & ISMT_INIT_SYNC) != 0) {
1030 cv_destroy(&ismt->ismt_cv);
1031 mutex_destroy(&ismt->ismt_mutex);
1032 ismt->ismt_init &= ~ISMT_INIT_SYNC;
1033 }
1034
1035 if ((ismt->ismt_init & ISMT_INIT_INTR_HDL) != 0) {
1036 int ret = ddi_intr_remove_handler(ismt->ismt_intr_hdl);
1037 if (ret != 0) {
1038 dev_err(ismt->ismt_dip, CE_WARN, "failed to remove "
1039 "interrupt handler: 0x%x", ret);
1040 }
1041 ismt->ismt_init &= ~ISMT_INIT_INTR_HDL;
1042 }
1043 if ((ismt->ismt_init & ISMT_INIT_INTR_ALLOC) != 0) {
1044 int ret = ddi_intr_free(ismt->ismt_intr_hdl);
1045 if (ret != DDI_SUCCESS) {
1046 dev_err(ismt->ismt_dip, CE_WARN, "failed to free "
1047 "device interrupt: 0x%x", ret);
1048 }
1049
1050 ismt->ismt_init &= ~ISMT_INIT_INTR_ALLOC;
1051 }
1052
1053 ismt_dma_free(&ismt->ismt_icl_dma);
1054 ismt_dma_free(&ismt->ismt_data_dma);
1055 ismt_dma_free(&ismt->ismt_ring_dma);
1056
1057 if ((ismt->ismt_init & ISMT_INIT_REGS) != 0) {
1058 ddi_regs_map_free(&ismt->ismt_regs);
1059 ismt->ismt_regs = NULL;
1060 ismt->ismt_regsize = 0;
1061 ismt->ismt_init &= ~ISMT_INIT_REGS;
1062 }
1063
1064 if ((ismt->ismt_init & ISMT_INIT_PCI) != 0) {
1065 pci_config_teardown(&ismt->ismt_cfg);
1066 ismt->ismt_cfg = NULL;
1067 ismt->ismt_init &= ~ISMT_INIT_PCI;
1068 }
1069
1070 ASSERT0(ismt->ismt_init);
1071 ddi_set_driver_private(ismt->ismt_dip, NULL);
1072 kmem_free(ismt, sizeof (ismt_t));
1073 }
1074
1075 int
ismt_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)1076 ismt_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1077 {
1078 ismt_t *ismt;
1079
1080 switch (cmd) {
1081 case DDI_ATTACH:
1082 break;
1083 case DDI_RESUME:
1084 default:
1085 return (DDI_FAILURE);
1086 }
1087
1088 ismt = kmem_zalloc(sizeof (ismt_t), KM_SLEEP);
1089 ismt->ismt_dip = dip;
1090 ddi_set_driver_private(dip, ismt);
1091
1092 if (pci_config_setup(dip, &ismt->ismt_cfg) != DDI_SUCCESS) {
1093 dev_err(dip, CE_WARN, "failed to set up config space");
1094 goto cleanup;
1095 }
1096 ismt->ismt_init |= ISMT_INIT_PCI;
1097
1098 if (!ismt_setup_regs(ismt))
1099 goto cleanup;
1100
1101 if (!ismt_dma_alloc(ismt, &ismt->ismt_ring_dma, ISMT_RING_DMA_SIZE)) {
1102 dev_err(dip, CE_WARN, "failed to allocate ring DMA memory");
1103 goto cleanup;
1104 }
1105
1106 if (!ismt_dma_alloc(ismt, &ismt->ismt_data_dma, ISMT_DATA_BUF_SIZE)) {
1107 dev_err(dip, CE_WARN, "failed to allocate data buffer DMA "
1108 "memory");
1109 goto cleanup;
1110 }
1111
1112 if (!ismt_dma_alloc(ismt, &ismt->ismt_icl_dma, ISMT_ICL_DMA_SIZE)) {
1113 dev_err(dip, CE_WARN, "failed to allocate interrupt cause DMA "
1114 "memory");
1115 goto cleanup;
1116 }
1117
1118 if (!ismt_alloc_intr(ismt))
1119 goto cleanup;
1120 ismt->ismt_init |= ISMT_INIT_INTR_ALLOC;
1121
1122 if (!ismt_setup_intr(ismt))
1123 goto cleanup;
1124
1125 mutex_init(&ismt->ismt_mutex, NULL, MUTEX_DRIVER,
1126 DDI_INTR_PRI(ismt->ismt_intr_pri));
1127 cv_init(&ismt->ismt_cv, NULL, CV_DRIVER, NULL);
1128 ismt->ismt_init |= ISMT_INIT_SYNC;
1129
1130 ismt_ctrl_init(ismt);
1131
1132 if (!ismt_enable_intr(ismt))
1133 goto cleanup;
1134
1135 if (!ismt_register(ismt))
1136 goto cleanup;
1137
1138 return (DDI_SUCCESS);
1139
1140 cleanup:
1141 ismt_cleanup(ismt);
1142 return (DDI_FAILURE);
1143 }
1144
1145 int
ismt_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)1146 ismt_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1147 {
1148 ismt_t *ismt;
1149
1150 switch (cmd) {
1151 case DDI_DETACH:
1152 break;
1153 case DDI_SUSPEND:
1154 default:
1155 return (DDI_FAILURE);
1156 }
1157
1158 ismt = ddi_get_driver_private(dip);
1159 if (ismt == NULL) {
1160 dev_err(dip, CE_WARN, "asked to detach, but missing private "
1161 "data");
1162 return (DDI_FAILURE);
1163 }
1164
1165 VERIFY3P(ismt->ismt_dip, ==, dip);
1166 i2c_ctrl_reg_error_t ret = i2c_ctrl_unregister(ismt->ismt_hdl);
1167 if (ret != 0) {
1168 dev_err(dip, CE_WARN, "failed to unregister from i2c "
1169 "framework 0x%x", ret);
1170 return (DDI_FAILURE);
1171 }
1172 ismt->ismt_init &= ~ISMT_INIT_I2C;
1173 ismt_cleanup(ismt);
1174
1175 return (DDI_SUCCESS);
1176 }
1177
1178 static struct dev_ops ismt_dev_ops = {
1179 .devo_rev = DEVO_REV,
1180 .devo_refcnt = 0,
1181 .devo_identify = nulldev,
1182 .devo_probe = nulldev,
1183 .devo_attach = ismt_attach,
1184 .devo_detach = ismt_detach,
1185 .devo_reset = nodev,
1186 .devo_quiesce = ddi_quiesce_not_supported,
1187 };
1188
1189 static struct modldrv ismt_modldrv = {
1190 .drv_modops = &mod_driverops,
1191 .drv_linkinfo = "Intel SMBus Message Target",
1192 .drv_dev_ops = &ismt_dev_ops
1193 };
1194
1195 static struct modlinkage ismt_modlinkage = {
1196 .ml_rev = MODREV_1,
1197 .ml_linkage = { &ismt_modldrv, NULL }
1198 };
1199
1200 int
_init(void)1201 _init(void)
1202 {
1203 int ret;
1204
1205 i2c_ctrl_mod_init(&ismt_dev_ops);
1206 if ((ret = mod_install(&ismt_modlinkage)) != 0) {
1207 i2c_ctrl_mod_fini(&ismt_dev_ops);
1208 }
1209
1210 return (ret);
1211 }
1212
1213 int
_info(struct modinfo * modinfop)1214 _info(struct modinfo *modinfop)
1215 {
1216 return (mod_info(&ismt_modlinkage, modinfop));
1217 }
1218
1219 int
_fini(void)1220 _fini(void)
1221 {
1222 int ret;
1223
1224 if ((ret = mod_remove(&ismt_modlinkage)) == 0) {
1225 i2c_ctrl_mod_fini(&ismt_dev_ops);
1226 }
1227
1228 return (ret);
1229 }
1230