1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 131 #define E1000_DEV_ID_PCH2_LV_V 0x1503 132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 150 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 151 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 152 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 153 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 154 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 155 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 156 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 157 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 158 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 159 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 160 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 161 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 162 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 163 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 164 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 165 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 166 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 167 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 168 #define E1000_DEV_ID_82576 0x10C9 169 #define E1000_DEV_ID_82576_FIBER 0x10E6 170 #define E1000_DEV_ID_82576_SERDES 0x10E7 171 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 172 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 173 #define E1000_DEV_ID_82576_NS 0x150A 174 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 175 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 176 #define E1000_DEV_ID_82576_VF 0x10CA 177 #define E1000_DEV_ID_82576_VF_HV 0x152D 178 #define E1000_DEV_ID_I350_VF 0x1520 179 #define E1000_DEV_ID_I350_VF_HV 0x152F 180 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 181 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 182 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 183 #define E1000_DEV_ID_82580_COPPER 0x150E 184 #define E1000_DEV_ID_82580_FIBER 0x150F 185 #define E1000_DEV_ID_82580_SERDES 0x1510 186 #define E1000_DEV_ID_82580_SGMII 0x1511 187 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 188 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 189 #define E1000_DEV_ID_I350_COPPER 0x1521 190 #define E1000_DEV_ID_I350_FIBER 0x1522 191 #define E1000_DEV_ID_I350_SERDES 0x1523 192 #define E1000_DEV_ID_I350_SGMII 0x1524 193 #define E1000_DEV_ID_I350_DA4 0x1546 194 #define E1000_DEV_ID_I210_COPPER 0x1533 195 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 196 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 197 #define E1000_DEV_ID_I210_FIBER 0x1536 198 #define E1000_DEV_ID_I210_SERDES 0x1537 199 #define E1000_DEV_ID_I210_SGMII 0x1538 200 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 201 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 202 #define E1000_DEV_ID_I211_COPPER 0x1539 203 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 204 #define E1000_DEV_ID_I354_SGMII 0x1F41 205 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 206 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 207 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 208 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 209 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 210 211 #define E1000_REVISION_0 0 212 #define E1000_REVISION_1 1 213 #define E1000_REVISION_2 2 214 #define E1000_REVISION_3 3 215 #define E1000_REVISION_4 4 216 217 #define E1000_FUNC_0 0 218 #define E1000_FUNC_1 1 219 #define E1000_FUNC_2 2 220 #define E1000_FUNC_3 3 221 222 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 223 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 224 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 225 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 226 227 /* 228 * This enumeration represents all of the different kinds of MAC chips that are 229 * used by both the e1000g and igb drivers. The ordering here is important as 230 * certain classes of MACs are very similar, but have minor differences and so 231 * are compared based on the ordering here. Changing the order here should not 232 * be done arbitrarily. 233 */ 234 enum e1000_mac_type { 235 e1000_undefined = 0, 236 e1000_82542, 237 e1000_82543, 238 e1000_82544, 239 e1000_82540, 240 e1000_82545, 241 e1000_82545_rev_3, 242 e1000_82546, 243 e1000_82546_rev_3, 244 e1000_82541, 245 e1000_82541_rev_2, 246 e1000_82547, 247 e1000_82547_rev_2, 248 e1000_82571, 249 e1000_82572, 250 e1000_82573, 251 e1000_82574, 252 e1000_82583, 253 e1000_80003es2lan, 254 /* 255 * The following MACs all share the ich8 style of hardware and are 256 * implemented in ich8, though some are a little more different than 257 * others. The pch_lpt, pch_spt, pch_cnp, and pch_tgp families are a bit 258 * more different than the others and just have slight variants in 259 * behavior between them. They are ordered based on release. 260 */ 261 e1000_ich8lan, 262 e1000_ich9lan, 263 e1000_ich10lan, 264 e1000_pchlan, 265 e1000_pch2lan, 266 e1000_pch_lpt, 267 e1000_pch_spt, 268 e1000_pch_cnp, 269 e1000_pch_tgp, 270 /* 271 * After this point all MACs are used by the igb(7D) driver as opposed 272 * to e1000g(7D). If a new MAC is specific to e1000g series of devices, 273 * then it should be added above this. 274 */ 275 e1000_82575, 276 e1000_82576, 277 e1000_82580, 278 e1000_i350, 279 e1000_i354, 280 e1000_i210, 281 e1000_i211, 282 e1000_vfadapt, 283 e1000_vfadapt_i350, 284 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 285 }; 286 287 enum e1000_media_type { 288 e1000_media_type_unknown = 0, 289 e1000_media_type_copper = 1, 290 e1000_media_type_fiber = 2, 291 e1000_media_type_internal_serdes = 3, 292 e1000_num_media_types 293 }; 294 295 enum e1000_nvm_type { 296 e1000_nvm_unknown = 0, 297 e1000_nvm_none, 298 e1000_nvm_eeprom_spi, 299 e1000_nvm_eeprom_microwire, 300 e1000_nvm_flash_hw, 301 e1000_nvm_invm, 302 e1000_nvm_flash_sw 303 }; 304 305 enum e1000_nvm_override { 306 e1000_nvm_override_none = 0, 307 e1000_nvm_override_spi_small, 308 e1000_nvm_override_spi_large, 309 e1000_nvm_override_microwire_small, 310 e1000_nvm_override_microwire_large 311 }; 312 313 enum e1000_phy_type { 314 e1000_phy_unknown = 0, 315 e1000_phy_none, 316 e1000_phy_m88, 317 e1000_phy_igp, 318 e1000_phy_igp_2, 319 e1000_phy_gg82563, 320 e1000_phy_igp_3, 321 e1000_phy_ife, 322 e1000_phy_bm, 323 e1000_phy_82578, 324 e1000_phy_82577, 325 e1000_phy_82579, 326 e1000_phy_i217, 327 e1000_phy_82580, 328 e1000_phy_vf, 329 e1000_phy_i210, 330 }; 331 332 enum e1000_bus_type { 333 e1000_bus_type_unknown = 0, 334 e1000_bus_type_pci, 335 e1000_bus_type_pcix, 336 e1000_bus_type_pci_express, 337 e1000_bus_type_reserved 338 }; 339 340 enum e1000_bus_speed { 341 e1000_bus_speed_unknown = 0, 342 e1000_bus_speed_33, 343 e1000_bus_speed_66, 344 e1000_bus_speed_100, 345 e1000_bus_speed_120, 346 e1000_bus_speed_133, 347 e1000_bus_speed_2500, 348 e1000_bus_speed_5000, 349 e1000_bus_speed_reserved 350 }; 351 352 enum e1000_bus_width { 353 e1000_bus_width_unknown = 0, 354 e1000_bus_width_pcie_x1, 355 e1000_bus_width_pcie_x2, 356 e1000_bus_width_pcie_x4 = 4, 357 e1000_bus_width_pcie_x8 = 8, 358 e1000_bus_width_32, 359 e1000_bus_width_64, 360 e1000_bus_width_reserved 361 }; 362 363 enum e1000_1000t_rx_status { 364 e1000_1000t_rx_status_not_ok = 0, 365 e1000_1000t_rx_status_ok, 366 e1000_1000t_rx_status_undefined = 0xFF 367 }; 368 369 enum e1000_rev_polarity { 370 e1000_rev_polarity_normal = 0, 371 e1000_rev_polarity_reversed, 372 e1000_rev_polarity_undefined = 0xFF 373 }; 374 375 enum e1000_fc_mode { 376 e1000_fc_none = 0, 377 e1000_fc_rx_pause, 378 e1000_fc_tx_pause, 379 e1000_fc_full, 380 e1000_fc_default = 0xFF 381 }; 382 383 enum e1000_ffe_config { 384 e1000_ffe_config_enabled = 0, 385 e1000_ffe_config_active, 386 e1000_ffe_config_blocked 387 }; 388 389 enum e1000_dsp_config { 390 e1000_dsp_config_disabled = 0, 391 e1000_dsp_config_enabled, 392 e1000_dsp_config_activated, 393 e1000_dsp_config_undefined = 0xFF 394 }; 395 396 enum e1000_ms_type { 397 e1000_ms_hw_default = 0, 398 e1000_ms_force_master, 399 e1000_ms_force_slave, 400 e1000_ms_auto 401 }; 402 403 enum e1000_smart_speed { 404 e1000_smart_speed_default = 0, 405 e1000_smart_speed_on, 406 e1000_smart_speed_off 407 }; 408 409 enum e1000_serdes_link_state { 410 e1000_serdes_link_down = 0, 411 e1000_serdes_link_autoneg_progress, 412 e1000_serdes_link_autoneg_complete, 413 e1000_serdes_link_forced_up 414 }; 415 416 #define __le16 u16 417 #define __le32 u32 418 #define __le64 u64 419 /* Receive Descriptor */ 420 struct e1000_rx_desc { 421 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 422 __le16 length; /* Length of data DMAed into data buffer */ 423 __le16 csum; /* Packet checksum */ 424 u8 status; /* Descriptor status */ 425 u8 errors; /* Descriptor Errors */ 426 __le16 special; 427 }; 428 429 /* Receive Descriptor - Extended */ 430 union e1000_rx_desc_extended { 431 struct { 432 __le64 buffer_addr; 433 __le64 reserved; 434 } read; 435 struct { 436 struct { 437 __le32 mrq; /* Multiple Rx Queues */ 438 union { 439 __le32 rss; /* RSS Hash */ 440 struct { 441 __le16 ip_id; /* IP id */ 442 __le16 csum; /* Packet Checksum */ 443 } csum_ip; 444 } hi_dword; 445 } lower; 446 struct { 447 __le32 status_error; /* ext status/error */ 448 __le16 length; 449 __le16 vlan; /* VLAN tag */ 450 } upper; 451 } wb; /* writeback */ 452 }; 453 454 #define MAX_PS_BUFFERS 4 455 456 /* Number of packet split data buffers (not including the header buffer) */ 457 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 458 459 /* Receive Descriptor - Packet Split */ 460 union e1000_rx_desc_packet_split { 461 struct { 462 /* one buffer for protocol header(s), three data buffers */ 463 __le64 buffer_addr[MAX_PS_BUFFERS]; 464 } read; 465 struct { 466 struct { 467 __le32 mrq; /* Multiple Rx Queues */ 468 union { 469 __le32 rss; /* RSS Hash */ 470 struct { 471 __le16 ip_id; /* IP id */ 472 __le16 csum; /* Packet Checksum */ 473 } csum_ip; 474 } hi_dword; 475 } lower; 476 struct { 477 __le32 status_error; /* ext status/error */ 478 __le16 length0; /* length of buffer 0 */ 479 __le16 vlan; /* VLAN tag */ 480 } middle; 481 struct { 482 __le16 header_status; 483 /* length of buffers 1-3 */ 484 __le16 length[PS_PAGE_BUFFERS]; 485 } upper; 486 __le64 reserved; 487 } wb; /* writeback */ 488 }; 489 490 /* Transmit Descriptor */ 491 struct e1000_tx_desc { 492 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 493 union { 494 __le32 data; 495 struct { 496 __le16 length; /* Data buffer length */ 497 u8 cso; /* Checksum offset */ 498 u8 cmd; /* Descriptor control */ 499 } flags; 500 } lower; 501 union { 502 __le32 data; 503 struct { 504 u8 status; /* Descriptor status */ 505 u8 css; /* Checksum start */ 506 __le16 special; 507 } fields; 508 } upper; 509 }; 510 511 /* Offload Context Descriptor */ 512 struct e1000_context_desc { 513 union { 514 __le32 ip_config; 515 struct { 516 u8 ipcss; /* IP checksum start */ 517 u8 ipcso; /* IP checksum offset */ 518 __le16 ipcse; /* IP checksum end */ 519 } ip_fields; 520 } lower_setup; 521 union { 522 __le32 tcp_config; 523 struct { 524 u8 tucss; /* TCP checksum start */ 525 u8 tucso; /* TCP checksum offset */ 526 __le16 tucse; /* TCP checksum end */ 527 } tcp_fields; 528 } upper_setup; 529 __le32 cmd_and_length; 530 union { 531 __le32 data; 532 struct { 533 u8 status; /* Descriptor status */ 534 u8 hdr_len; /* Header length */ 535 __le16 mss; /* Maximum segment size */ 536 } fields; 537 } tcp_seg_setup; 538 }; 539 540 /* Offload data descriptor */ 541 struct e1000_data_desc { 542 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 543 union { 544 __le32 data; 545 struct { 546 __le16 length; /* Data buffer length */ 547 u8 typ_len_ext; 548 u8 cmd; 549 } flags; 550 } lower; 551 union { 552 __le32 data; 553 struct { 554 u8 status; /* Descriptor status */ 555 u8 popts; /* Packet Options */ 556 __le16 special; 557 } fields; 558 } upper; 559 }; 560 561 /* Statistics counters collected by the MAC */ 562 struct e1000_hw_stats { 563 u64 crcerrs; 564 u64 algnerrc; 565 u64 symerrs; 566 u64 rxerrc; 567 u64 mpc; 568 u64 scc; 569 u64 ecol; 570 u64 mcc; 571 u64 latecol; 572 u64 colc; 573 u64 dc; 574 u64 tncrs; 575 u64 sec; 576 u64 cexterr; 577 u64 rlec; 578 u64 xonrxc; 579 u64 xontxc; 580 u64 xoffrxc; 581 u64 xofftxc; 582 u64 fcruc; 583 u64 prc64; 584 u64 prc127; 585 u64 prc255; 586 u64 prc511; 587 u64 prc1023; 588 u64 prc1522; 589 u64 gprc; 590 u64 bprc; 591 u64 mprc; 592 u64 gptc; 593 u64 gorc; 594 u64 gotc; 595 u64 rnbc; 596 u64 ruc; 597 u64 rfc; 598 u64 roc; 599 u64 rjc; 600 u64 mgprc; 601 u64 mgpdc; 602 u64 mgptc; 603 u64 tor; 604 u64 tot; 605 u64 tpr; 606 u64 tpt; 607 u64 ptc64; 608 u64 ptc127; 609 u64 ptc255; 610 u64 ptc511; 611 u64 ptc1023; 612 u64 ptc1522; 613 u64 mptc; 614 u64 bptc; 615 u64 tsctc; 616 u64 tsctfc; 617 u64 iac; 618 u64 icrxptc; 619 u64 icrxatc; 620 u64 ictxptc; 621 u64 ictxatc; 622 u64 ictxqec; 623 u64 ictxqmtc; 624 u64 icrxdmtc; 625 u64 icrxoc; 626 u64 cbtmpc; 627 u64 htdpmc; 628 u64 cbrdpc; 629 u64 cbrmpc; 630 u64 rpthc; 631 u64 hgptc; 632 u64 htcbdpc; 633 u64 hgorc; 634 u64 hgotc; 635 u64 lenerrs; 636 u64 scvpc; 637 u64 hrmpc; 638 u64 doosync; 639 u64 o2bgptc; 640 u64 o2bspc; 641 u64 b2ospc; 642 u64 b2ogprc; 643 }; 644 645 struct e1000_vf_stats { 646 u64 base_gprc; 647 u64 base_gptc; 648 u64 base_gorc; 649 u64 base_gotc; 650 u64 base_mprc; 651 u64 base_gotlbc; 652 u64 base_gptlbc; 653 u64 base_gorlbc; 654 u64 base_gprlbc; 655 656 u32 last_gprc; 657 u32 last_gptc; 658 u32 last_gorc; 659 u32 last_gotc; 660 u32 last_mprc; 661 u32 last_gotlbc; 662 u32 last_gptlbc; 663 u32 last_gorlbc; 664 u32 last_gprlbc; 665 666 u64 gprc; 667 u64 gptc; 668 u64 gorc; 669 u64 gotc; 670 u64 mprc; 671 u64 gotlbc; 672 u64 gptlbc; 673 u64 gorlbc; 674 u64 gprlbc; 675 }; 676 677 struct e1000_phy_stats { 678 u32 idle_errors; 679 u32 receive_errors; 680 }; 681 682 struct e1000_host_mng_dhcp_cookie { 683 u32 signature; 684 u8 status; 685 u8 reserved0; 686 u16 vlan_id; 687 u32 reserved1; 688 u16 reserved2; 689 u8 reserved3; 690 u8 checksum; 691 }; 692 693 /* Host Interface "Rev 1" */ 694 struct e1000_host_command_header { 695 u8 command_id; 696 u8 command_length; 697 u8 command_options; 698 u8 checksum; 699 }; 700 701 #define E1000_HI_MAX_DATA_LENGTH 252 702 struct e1000_host_command_info { 703 struct e1000_host_command_header command_header; 704 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 705 }; 706 707 /* Host Interface "Rev 2" */ 708 struct e1000_host_mng_command_header { 709 u8 command_id; 710 u8 checksum; 711 u16 reserved1; 712 u16 reserved2; 713 u16 command_length; 714 }; 715 716 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 717 struct e1000_host_mng_command_info { 718 struct e1000_host_mng_command_header command_header; 719 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 720 }; 721 722 #include "e1000_mac.h" 723 #include "e1000_phy.h" 724 #include "e1000_nvm.h" 725 #include "e1000_manage.h" 726 #include "e1000_mbx.h" 727 728 /* Function pointers for the MAC. */ 729 struct e1000_mac_operations { 730 s32 (*init_params)(struct e1000_hw *); 731 s32 (*id_led_init)(struct e1000_hw *); 732 s32 (*blink_led)(struct e1000_hw *); 733 bool (*check_mng_mode)(struct e1000_hw *); 734 s32 (*check_for_link)(struct e1000_hw *); 735 s32 (*cleanup_led)(struct e1000_hw *); 736 void (*clear_hw_cntrs)(struct e1000_hw *); 737 void (*clear_vfta)(struct e1000_hw *); 738 s32 (*get_bus_info)(struct e1000_hw *); 739 void (*set_lan_id)(struct e1000_hw *); 740 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 741 s32 (*led_on)(struct e1000_hw *); 742 s32 (*led_off)(struct e1000_hw *); 743 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 744 s32 (*reset_hw)(struct e1000_hw *); 745 s32 (*init_hw)(struct e1000_hw *); 746 void (*shutdown_serdes)(struct e1000_hw *); 747 void (*power_up_serdes)(struct e1000_hw *); 748 s32 (*setup_link)(struct e1000_hw *); 749 s32 (*setup_physical_interface)(struct e1000_hw *); 750 s32 (*setup_led)(struct e1000_hw *); 751 void (*write_vfta)(struct e1000_hw *, u32, u32); 752 void (*config_collision_dist)(struct e1000_hw *); 753 int (*rar_set)(struct e1000_hw *, u8*, u32); 754 s32 (*read_mac_addr)(struct e1000_hw *); 755 s32 (*validate_mdi_setting)(struct e1000_hw *); 756 s32 (*set_obff_timer)(struct e1000_hw *, u32); 757 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 758 void (*release_swfw_sync)(struct e1000_hw *, u16); 759 }; 760 761 /* When to use various PHY register access functions: 762 * 763 * Func Caller 764 * Function Does Does When to use 765 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 766 * X_reg L,P,A n/a for simple PHY reg accesses 767 * X_reg_locked P,A L for multiple accesses of different regs 768 * on different pages 769 * X_reg_page A L,P for multiple accesses of different regs 770 * on the same page 771 * 772 * Where X=[read|write], L=locking, P=sets page, A=register access 773 * 774 */ 775 struct e1000_phy_operations { 776 s32 (*init_params)(struct e1000_hw *); 777 s32 (*acquire)(struct e1000_hw *); 778 s32 (*cfg_on_link_up)(struct e1000_hw *); 779 s32 (*check_polarity)(struct e1000_hw *); 780 s32 (*check_reset_block)(struct e1000_hw *); 781 s32 (*commit)(struct e1000_hw *); 782 s32 (*force_speed_duplex)(struct e1000_hw *); 783 s32 (*get_cfg_done)(struct e1000_hw *hw); 784 s32 (*get_cable_length)(struct e1000_hw *); 785 s32 (*get_info)(struct e1000_hw *); 786 s32 (*set_page)(struct e1000_hw *, u16); 787 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 788 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 789 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 790 void (*release)(struct e1000_hw *); 791 s32 (*reset)(struct e1000_hw *); 792 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 793 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 794 s32 (*write_reg)(struct e1000_hw *, u32, u16); 795 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 796 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 797 void (*power_up)(struct e1000_hw *); 798 void (*power_down)(struct e1000_hw *); 799 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 800 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 801 }; 802 803 /* Function pointers for the NVM. */ 804 struct e1000_nvm_operations { 805 s32 (*init_params)(struct e1000_hw *); 806 s32 (*acquire)(struct e1000_hw *); 807 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 808 void (*release)(struct e1000_hw *); 809 void (*reload)(struct e1000_hw *); 810 s32 (*update)(struct e1000_hw *); 811 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 812 s32 (*validate)(struct e1000_hw *); 813 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 814 }; 815 816 struct e1000_mac_info { 817 struct e1000_mac_operations ops; 818 u8 addr[ETH_ADDR_LEN]; 819 u8 perm_addr[ETH_ADDR_LEN]; 820 821 enum e1000_mac_type type; 822 823 u32 collision_delta; 824 u32 ledctl_default; 825 u32 ledctl_mode1; 826 u32 ledctl_mode2; 827 u32 mc_filter_type; 828 u32 tx_packet_delta; 829 u32 txcw; 830 831 u16 current_ifs_val; 832 u16 ifs_max_val; 833 u16 ifs_min_val; 834 u16 ifs_ratio; 835 u16 ifs_step_size; 836 u16 mta_reg_count; 837 u16 uta_reg_count; 838 839 /* Maximum size of the MTA register table in all supported adapters */ 840 #define MAX_MTA_REG 128 841 u32 mta_shadow[MAX_MTA_REG]; 842 u16 rar_entry_count; 843 844 u8 forced_speed_duplex; 845 846 bool adaptive_ifs; 847 bool has_fwsm; 848 bool arc_subsystem_valid; 849 bool asf_firmware_present; 850 bool autoneg; 851 bool autoneg_failed; 852 bool get_link_status; 853 bool in_ifs_mode; 854 bool report_tx_early; 855 enum e1000_serdes_link_state serdes_link_state; 856 bool serdes_has_link; 857 bool tx_pkt_filtering; 858 u32 max_frame_size; 859 }; 860 861 struct e1000_phy_info { 862 struct e1000_phy_operations ops; 863 enum e1000_phy_type type; 864 865 enum e1000_1000t_rx_status local_rx; 866 enum e1000_1000t_rx_status remote_rx; 867 enum e1000_ms_type ms_type; 868 enum e1000_ms_type original_ms_type; 869 enum e1000_rev_polarity cable_polarity; 870 enum e1000_smart_speed smart_speed; 871 872 u32 addr; 873 u32 id; 874 u32 reset_delay_us; /* in usec */ 875 u32 revision; 876 877 enum e1000_media_type media_type; 878 879 u16 autoneg_advertised; 880 u16 autoneg_mask; 881 u16 cable_length; 882 u16 max_cable_length; 883 u16 min_cable_length; 884 885 u8 mdix; 886 887 bool disable_polarity_correction; 888 bool is_mdix; 889 bool polarity_correction; 890 bool speed_downgraded; 891 bool autoneg_wait_to_complete; 892 }; 893 894 struct e1000_nvm_info { 895 struct e1000_nvm_operations ops; 896 enum e1000_nvm_type type; 897 enum e1000_nvm_override override; 898 899 u32 flash_bank_size; 900 u32 flash_base_addr; 901 902 u16 word_size; 903 u16 delay_usec; 904 u16 address_bits; 905 u16 opcode_bits; 906 u16 page_size; 907 }; 908 909 struct e1000_bus_info { 910 enum e1000_bus_type type; 911 enum e1000_bus_speed speed; 912 enum e1000_bus_width width; 913 914 u16 func; 915 u16 pci_cmd_word; 916 }; 917 918 struct e1000_fc_info { 919 u32 high_water; /* Flow control high-water mark */ 920 u32 low_water; /* Flow control low-water mark */ 921 u16 pause_time; /* Flow control pause timer */ 922 u16 refresh_time; /* Flow control refresh timer */ 923 bool send_xon; /* Flow control send XON */ 924 bool strict_ieee; /* Strict IEEE mode */ 925 enum e1000_fc_mode current_mode; /* FC mode in effect */ 926 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 927 }; 928 929 struct e1000_mbx_operations { 930 s32 (*init_params)(struct e1000_hw *hw); 931 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 932 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 933 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 934 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 935 s32 (*check_for_msg)(struct e1000_hw *, u16); 936 s32 (*check_for_ack)(struct e1000_hw *, u16); 937 s32 (*check_for_rst)(struct e1000_hw *, u16); 938 }; 939 940 struct e1000_mbx_stats { 941 u32 msgs_tx; 942 u32 msgs_rx; 943 944 u32 acks; 945 u32 reqs; 946 u32 rsts; 947 }; 948 949 struct e1000_mbx_info { 950 struct e1000_mbx_operations ops; 951 struct e1000_mbx_stats stats; 952 u32 timeout; 953 u32 usec_delay; 954 u16 size; 955 }; 956 957 struct e1000_dev_spec_82541 { 958 enum e1000_dsp_config dsp_config; 959 enum e1000_ffe_config ffe_config; 960 u32 tx_fifo_head; 961 u32 tx_fifo_start; 962 u32 tx_fifo_size; 963 u16 dsp_reset_counter; 964 u16 spd_default; 965 bool phy_init_script; 966 bool ttl_workaround; 967 }; 968 969 struct e1000_dev_spec_82542 { 970 bool dma_fairness; 971 }; 972 973 struct e1000_dev_spec_82543 { 974 u32 tbi_compatibility; 975 bool dma_fairness; 976 bool init_phy_disabled; 977 }; 978 979 struct e1000_dev_spec_82571 { 980 bool laa_is_present; 981 u32 smb_counter; 982 E1000_MUTEX swflag_mutex; 983 }; 984 985 struct e1000_dev_spec_80003es2lan { 986 bool mdic_wa_enable; 987 }; 988 989 struct e1000_shadow_ram { 990 u16 value; 991 bool modified; 992 }; 993 994 #define E1000_SHADOW_RAM_WORDS 2048 995 996 /* I218 PHY Ultra Low Power (ULP) states */ 997 enum e1000_ulp_state { 998 e1000_ulp_state_unknown, 999 e1000_ulp_state_off, 1000 e1000_ulp_state_on, 1001 }; 1002 1003 struct e1000_dev_spec_ich8lan { 1004 bool kmrn_lock_loss_workaround_enabled; 1005 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1006 E1000_MUTEX nvm_mutex; 1007 E1000_MUTEX swflag_mutex; 1008 bool nvm_k1_enabled; 1009 bool disable_k1_off; 1010 bool eee_disable; 1011 u16 eee_lp_ability; 1012 enum e1000_ulp_state ulp_state; 1013 bool ulp_capability_disabled; 1014 bool during_suspend_flow; 1015 bool during_dpg_exit; 1016 }; 1017 1018 struct e1000_dev_spec_82575 { 1019 bool sgmii_active; 1020 bool global_device_reset; 1021 bool eee_disable; 1022 bool module_plugged; 1023 bool clear_semaphore_once; 1024 u32 mtu; 1025 struct sfp_e1000_flags eth_flags; 1026 u8 media_port; 1027 bool media_changed; 1028 }; 1029 1030 struct e1000_dev_spec_vf { 1031 u32 vf_number; 1032 u32 v2p_mailbox; 1033 }; 1034 1035 struct e1000_hw { 1036 void *back; 1037 1038 u8 *hw_addr; 1039 u8 *flash_address; 1040 unsigned long io_base; 1041 1042 struct e1000_mac_info mac; 1043 struct e1000_fc_info fc; 1044 struct e1000_phy_info phy; 1045 struct e1000_nvm_info nvm; 1046 struct e1000_bus_info bus; 1047 struct e1000_mbx_info mbx; 1048 struct e1000_host_mng_dhcp_cookie mng_cookie; 1049 1050 union { 1051 struct e1000_dev_spec_82541 _82541; 1052 struct e1000_dev_spec_82542 _82542; 1053 struct e1000_dev_spec_82543 _82543; 1054 struct e1000_dev_spec_82571 _82571; 1055 struct e1000_dev_spec_80003es2lan _80003es2lan; 1056 struct e1000_dev_spec_ich8lan ich8lan; 1057 struct e1000_dev_spec_82575 _82575; 1058 struct e1000_dev_spec_vf vf; 1059 } dev_spec; 1060 1061 u16 device_id; 1062 u16 subsystem_vendor_id; 1063 u16 subsystem_device_id; 1064 u16 vendor_id; 1065 1066 u8 revision_id; 1067 }; 1068 1069 #include "e1000_82541.h" 1070 #include "e1000_82543.h" 1071 #include "e1000_82571.h" 1072 #include "e1000_80003es2lan.h" 1073 #include "e1000_ich8lan.h" 1074 #include "e1000_82575.h" 1075 #include "e1000_i210.h" 1076 1077 /* These functions must be implemented by drivers */ 1078 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1079 void e1000_pci_set_mwi(struct e1000_hw *hw); 1080 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1081 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1082 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1083 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1084 1085 #endif 1086