xref: /illumos-gate/usr/src/uts/common/io/e1000api/e1000_hw.h (revision 1d0ec46fafb49266ae79840a692bb48af60ade70)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2015, Intel Corporation
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5 
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_HW_H_
36 #define _E1000_HW_H_
37 
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
41 
42 struct e1000_hw;
43 
44 #define E1000_DEV_ID_82542			0x1000
45 #define E1000_DEV_ID_82543GC_FIBER		0x1001
46 #define E1000_DEV_ID_82543GC_COPPER		0x1004
47 #define E1000_DEV_ID_82544EI_COPPER		0x1008
48 #define E1000_DEV_ID_82544EI_FIBER		0x1009
49 #define E1000_DEV_ID_82544GC_COPPER		0x100C
50 #define E1000_DEV_ID_82544GC_LOM		0x100D
51 #define E1000_DEV_ID_82540EM			0x100E
52 #define E1000_DEV_ID_82540EM_LOM		0x1015
53 #define E1000_DEV_ID_82540EP_LOM		0x1016
54 #define E1000_DEV_ID_82540EP			0x1017
55 #define E1000_DEV_ID_82540EP_LP			0x101E
56 #define E1000_DEV_ID_82545EM_COPPER		0x100F
57 #define E1000_DEV_ID_82545EM_FIBER		0x1011
58 #define E1000_DEV_ID_82545GM_COPPER		0x1026
59 #define E1000_DEV_ID_82545GM_FIBER		0x1027
60 #define E1000_DEV_ID_82545GM_SERDES		0x1028
61 #define E1000_DEV_ID_82546EB_COPPER		0x1010
62 #define E1000_DEV_ID_82546EB_FIBER		0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
64 #define E1000_DEV_ID_82546GB_COPPER		0x1079
65 #define E1000_DEV_ID_82546GB_FIBER		0x107A
66 #define E1000_DEV_ID_82546GB_SERDES		0x107B
67 #define E1000_DEV_ID_82546GB_PCIE		0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
70 #define E1000_DEV_ID_82541EI			0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE		0x1018
72 #define E1000_DEV_ID_82541ER_LOM		0x1014
73 #define E1000_DEV_ID_82541ER			0x1078
74 #define E1000_DEV_ID_82541GI			0x1076
75 #define E1000_DEV_ID_82541GI_LF			0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE		0x1077
77 #define E1000_DEV_ID_82547EI			0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE		0x101A
79 #define E1000_DEV_ID_82547GI			0x1075
80 #define E1000_DEV_ID_82571EB_COPPER		0x105E
81 #define E1000_DEV_ID_82571EB_FIBER		0x105F
82 #define E1000_DEV_ID_82571EB_SERDES		0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER		0x107D
90 #define E1000_DEV_ID_82572EI_FIBER		0x107E
91 #define E1000_DEV_ID_82572EI_SERDES		0x107F
92 #define E1000_DEV_ID_82572EI			0x10B9
93 #define E1000_DEV_ID_82573E			0x108B
94 #define E1000_DEV_ID_82573E_IAMT		0x108C
95 #define E1000_DEV_ID_82573L			0x109A
96 #define E1000_DEV_ID_82574L			0x10D3
97 #define E1000_DEV_ID_82574LA			0x10F6
98 #define E1000_DEV_ID_82583V			0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3		0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C			0x104B
107 #define E1000_DEV_ID_ICH8_IFE			0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G			0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M			0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M			0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
115 #define E1000_DEV_ID_ICH9_BM			0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C			0x294C
117 #define E1000_DEV_ID_ICH9_IFE			0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G			0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
125 #define E1000_DEV_ID_ICH10_D_BM_V		0x1525
126 #define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
130 #define E1000_DEV_ID_PCH2_LV_LM			0x1502
131 #define E1000_DEV_ID_PCH2_LV_V			0x1503
132 #define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
133 #define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
135 #define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
136 #define E1000_DEV_ID_PCH_I218_LM2		0x15A0
137 #define E1000_DEV_ID_PCH_I218_V2		0x15A1
138 #define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F /* Sunrise Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_V		0x1570 /* Sunrise Point PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7 /* Sunrise Point-H PCH */
143 #define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8 /* Sunrise Point-H PCH */
144 #define E1000_DEV_ID_PCH_LBG_I219_LM3		0x15B9 /* LEWISBURG PCH */
145 #define E1000_DEV_ID_PCH_SPT_I219_LM4		0x15D7
146 #define E1000_DEV_ID_PCH_SPT_I219_V4		0x15D8
147 #define E1000_DEV_ID_PCH_SPT_I219_LM5		0x15E3
148 #define E1000_DEV_ID_PCH_SPT_I219_V5		0x15D6
149 #define E1000_DEV_ID_PCH_CNP_I219_LM6		0x15BD
150 #define E1000_DEV_ID_PCH_CNP_I219_V6		0x15BE
151 #define E1000_DEV_ID_PCH_CNP_I219_LM7		0x15BB
152 #define E1000_DEV_ID_PCH_CNP_I219_V7		0x15BC
153 #define E1000_DEV_ID_PCH_ICP_I219_LM8		0x15DF
154 #define E1000_DEV_ID_PCH_ICP_I219_V8		0x15E0
155 #define E1000_DEV_ID_PCH_ICP_I219_LM9		0x15E1
156 #define E1000_DEV_ID_PCH_ICP_I219_V9		0x15E2
157 #define E1000_DEV_ID_PCH_CMP_I219_LM10		0x0D4E
158 #define E1000_DEV_ID_PCH_CMP_I219_V10		0x0D4F
159 #define E1000_DEV_ID_PCH_CMP_I219_LM11		0x0D4C
160 #define E1000_DEV_ID_PCH_CMP_I219_V11		0x0D4D
161 #define E1000_DEV_ID_PCH_CMP_I219_LM12		0x0D53
162 #define E1000_DEV_ID_PCH_CMP_I219_V12		0x0D55
163 #define E1000_DEV_ID_PCH_TGP_I219_LM13		0x15FB
164 #define E1000_DEV_ID_PCH_TGP_I219_V13		0x15FC
165 #define E1000_DEV_ID_PCH_TGP_I219_LM14		0x15F9
166 #define E1000_DEV_ID_PCH_TGP_I219_V14		0x15FA
167 #define E1000_DEV_ID_PCH_TGP_I219_LM15		0x15F4
168 #define E1000_DEV_ID_PCH_TGP_I219_V15		0x15F5
169 #define E1000_DEV_ID_PCH_ADP_I219_LM16		0x1A1E
170 #define E1000_DEV_ID_PCH_ADP_I219_V16		0x1A1F
171 #define E1000_DEV_ID_PCH_ADP_I219_LM17		0x1A1C
172 #define E1000_DEV_ID_PCH_ADP_I219_V17		0x1A1D
173 #define E1000_DEV_ID_PCH_MTP_I219_LM18		0x550A
174 #define E1000_DEV_ID_PCH_MTP_I219_V18		0x550B
175 #define E1000_DEV_ID_PCH_MTP_I219_LM19		0x550C
176 #define E1000_DEV_ID_PCH_MTP_I219_V19		0x550D
177 #define E1000_DEV_ID_PCH_LNP_I219_LM20		0x550E
178 #define E1000_DEV_ID_PCH_LNP_I219_V20		0x550F
179 #define E1000_DEV_ID_PCH_LNP_I219_LM21		0x5510
180 #define E1000_DEV_ID_PCH_LNP_I219_V21		0x5511
181 #define E1000_DEV_ID_PCH_RPL_I219_LM22		0x0DC7
182 #define E1000_DEV_ID_PCH_RPL_I219_V22		0x0DC8
183 #define E1000_DEV_ID_PCH_RPL_I219_LM23		0x0DC5
184 #define E1000_DEV_ID_PCH_RPL_I219_V23		0x0DC6
185 #define E1000_DEV_ID_PCH_ARL_I219_LM24		0x57A0
186 #define E1000_DEV_ID_PCH_ARL_I219_V24		0x57A1
187 #define E1000_DEV_ID_PCH_PTP_I219_LM25		0x57B3
188 #define E1000_DEV_ID_PCH_PTP_I219_V25		0x57B4
189 #define E1000_DEV_ID_PCH_PTP_I219_LM26		0x57B5
190 #define E1000_DEV_ID_PCH_PTP_I219_V26		0x57B6
191 #define E1000_DEV_ID_PCH_PTP_I219_LM27		0x57B7
192 #define E1000_DEV_ID_PCH_PTP_I219_V27		0x57B8
193 #define E1000_DEV_ID_PCH_NVL_I219_LM29		0x57B9
194 #define E1000_DEV_ID_PCH_NVL_I219_V29		0x57BA
195 #define E1000_DEV_ID_82576			0x10C9
196 #define E1000_DEV_ID_82576_FIBER		0x10E6
197 #define E1000_DEV_ID_82576_SERDES		0x10E7
198 #define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
199 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
200 #define E1000_DEV_ID_82576_NS			0x150A
201 #define E1000_DEV_ID_82576_NS_SERDES		0x1518
202 #define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
203 #define E1000_DEV_ID_82576_VF			0x10CA
204 #define E1000_DEV_ID_82576_VF_HV		0x152D
205 #define E1000_DEV_ID_I350_VF			0x1520
206 #define E1000_DEV_ID_I350_VF_HV			0x152F
207 #define E1000_DEV_ID_82575EB_COPPER		0x10A7
208 #define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
209 #define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
210 #define E1000_DEV_ID_82580_COPPER		0x150E
211 #define E1000_DEV_ID_82580_FIBER		0x150F
212 #define E1000_DEV_ID_82580_SERDES		0x1510
213 #define E1000_DEV_ID_82580_SGMII		0x1511
214 #define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
215 #define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
216 #define E1000_DEV_ID_I350_COPPER		0x1521
217 #define E1000_DEV_ID_I350_FIBER			0x1522
218 #define E1000_DEV_ID_I350_SERDES		0x1523
219 #define E1000_DEV_ID_I350_SGMII			0x1524
220 #define E1000_DEV_ID_I350_DA4			0x1546
221 #define E1000_DEV_ID_I210_COPPER		0x1533
222 #define E1000_DEV_ID_I210_COPPER_OEM1		0x1534
223 #define E1000_DEV_ID_I210_COPPER_IT		0x1535
224 #define E1000_DEV_ID_I210_FIBER			0x1536
225 #define E1000_DEV_ID_I210_SERDES		0x1537
226 #define E1000_DEV_ID_I210_SGMII			0x1538
227 #define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
228 #define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
229 #define E1000_DEV_ID_I211_COPPER		0x1539
230 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
231 #define E1000_DEV_ID_I354_SGMII			0x1F41
232 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45
233 #define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
234 #define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
235 #define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
236 #define E1000_DEV_ID_DH89XXCC_SFP		0x0440
237 
238 #define E1000_REVISION_0	0
239 #define E1000_REVISION_1	1
240 #define E1000_REVISION_2	2
241 #define E1000_REVISION_3	3
242 #define E1000_REVISION_4	4
243 
244 #define E1000_FUNC_0		0
245 #define E1000_FUNC_1		1
246 #define E1000_FUNC_2		2
247 #define E1000_FUNC_3		3
248 
249 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
250 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
251 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
252 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
253 
254 /*
255  * This enumeration represents all of the different kinds of MAC chips that are
256  * used by both the e1000g and igb drivers. The ordering here is important as
257  * certain classes of MACs are very similar, but have minor differences and so
258  * are compared based on the ordering here. Changing the order here should not
259  * be done arbitrarily.
260  */
261 enum e1000_mac_type {
262 	e1000_undefined = 0,
263 	e1000_82542,
264 	e1000_82543,
265 	e1000_82544,
266 	e1000_82540,
267 	e1000_82545,
268 	e1000_82545_rev_3,
269 	e1000_82546,
270 	e1000_82546_rev_3,
271 	e1000_82541,
272 	e1000_82541_rev_2,
273 	e1000_82547,
274 	e1000_82547_rev_2,
275 	e1000_82571,
276 	e1000_82572,
277 	e1000_82573,
278 	e1000_82574,
279 	e1000_82583,
280 	e1000_80003es2lan,
281 	/*
282 	 * The following MACs all share the ich8 style of hardware and are
283 	 * implemented in ich8, though some are a little more different than
284 	 * others. The pch_lpt, pch_spt, pch_cnp, pch_tgp, pch_adp, pch_mtp,
285 	 * pch_lnp, pch_rpl, pch_arl, pch_ptp, and pch_nvl families are a bit
286 	 * more different than the others and just have slight variants in
287 	 * behavior between them. We call them out just in case we need to deal
288 	 * with the quirks between different device generations. They are
289 	 * ordered based on release.
290 	 */
291 	e1000_ich8lan,
292 	e1000_ich9lan,
293 	e1000_ich10lan,
294 	e1000_pchlan,
295 	e1000_pch2lan,
296 	e1000_pch_lpt,
297 	e1000_pch_spt,
298 	e1000_pch_cnp,
299 	e1000_pch_tgp,
300 	e1000_pch_adp,
301 	e1000_pch_mtp,
302 	e1000_pch_lnp,
303 	e1000_pch_rpl,
304 	e1000_pch_arl,
305 	e1000_pch_ptp,
306 	e1000_pch_nvl,
307 	/*
308 	 * After this point all MACs are used by the igb(4D) driver as opposed
309 	 * to e1000g(4D). If a new MAC is specific to e1000g series of devices,
310 	 * then it should be added above this.
311 	 */
312 	e1000_82575,
313 	e1000_82576,
314 	e1000_82580,
315 	e1000_i350,
316 	e1000_i354,
317 	e1000_i210,
318 	e1000_i211,
319 	e1000_vfadapt,
320 	e1000_vfadapt_i350,
321 	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
322 };
323 
324 enum e1000_media_type {
325 	e1000_media_type_unknown = 0,
326 	e1000_media_type_copper = 1,
327 	e1000_media_type_fiber = 2,
328 	e1000_media_type_internal_serdes = 3,
329 	e1000_num_media_types
330 };
331 
332 enum e1000_nvm_type {
333 	e1000_nvm_unknown = 0,
334 	e1000_nvm_none,
335 	e1000_nvm_eeprom_spi,
336 	e1000_nvm_eeprom_microwire,
337 	e1000_nvm_flash_hw,
338 	e1000_nvm_invm,
339 	e1000_nvm_flash_sw
340 };
341 
342 enum e1000_nvm_override {
343 	e1000_nvm_override_none = 0,
344 	e1000_nvm_override_spi_small,
345 	e1000_nvm_override_spi_large,
346 	e1000_nvm_override_microwire_small,
347 	e1000_nvm_override_microwire_large
348 };
349 
350 enum e1000_phy_type {
351 	e1000_phy_unknown = 0,
352 	e1000_phy_none,
353 	e1000_phy_m88,
354 	e1000_phy_igp,
355 	e1000_phy_igp_2,
356 	e1000_phy_gg82563,
357 	e1000_phy_igp_3,
358 	e1000_phy_ife,
359 	e1000_phy_bm,
360 	e1000_phy_82578,
361 	e1000_phy_82577,
362 	e1000_phy_82579,
363 	e1000_phy_i217,
364 	e1000_phy_82580,
365 	e1000_phy_vf,
366 	e1000_phy_i210,
367 };
368 
369 enum e1000_bus_type {
370 	e1000_bus_type_unknown = 0,
371 	e1000_bus_type_pci,
372 	e1000_bus_type_pcix,
373 	e1000_bus_type_pci_express,
374 	e1000_bus_type_reserved
375 };
376 
377 enum e1000_bus_speed {
378 	e1000_bus_speed_unknown = 0,
379 	e1000_bus_speed_33,
380 	e1000_bus_speed_66,
381 	e1000_bus_speed_100,
382 	e1000_bus_speed_120,
383 	e1000_bus_speed_133,
384 	e1000_bus_speed_2500,
385 	e1000_bus_speed_5000,
386 	e1000_bus_speed_reserved
387 };
388 
389 enum e1000_bus_width {
390 	e1000_bus_width_unknown = 0,
391 	e1000_bus_width_pcie_x1,
392 	e1000_bus_width_pcie_x2,
393 	e1000_bus_width_pcie_x4 = 4,
394 	e1000_bus_width_pcie_x8 = 8,
395 	e1000_bus_width_32,
396 	e1000_bus_width_64,
397 	e1000_bus_width_reserved
398 };
399 
400 enum e1000_1000t_rx_status {
401 	e1000_1000t_rx_status_not_ok = 0,
402 	e1000_1000t_rx_status_ok,
403 	e1000_1000t_rx_status_undefined = 0xFF
404 };
405 
406 enum e1000_rev_polarity {
407 	e1000_rev_polarity_normal = 0,
408 	e1000_rev_polarity_reversed,
409 	e1000_rev_polarity_undefined = 0xFF
410 };
411 
412 enum e1000_fc_mode {
413 	e1000_fc_none = 0,
414 	e1000_fc_rx_pause,
415 	e1000_fc_tx_pause,
416 	e1000_fc_full,
417 	e1000_fc_default = 0xFF
418 };
419 
420 enum e1000_ffe_config {
421 	e1000_ffe_config_enabled = 0,
422 	e1000_ffe_config_active,
423 	e1000_ffe_config_blocked
424 };
425 
426 enum e1000_dsp_config {
427 	e1000_dsp_config_disabled = 0,
428 	e1000_dsp_config_enabled,
429 	e1000_dsp_config_activated,
430 	e1000_dsp_config_undefined = 0xFF
431 };
432 
433 enum e1000_ms_type {
434 	e1000_ms_hw_default = 0,
435 	e1000_ms_force_master,
436 	e1000_ms_force_slave,
437 	e1000_ms_auto
438 };
439 
440 enum e1000_smart_speed {
441 	e1000_smart_speed_default = 0,
442 	e1000_smart_speed_on,
443 	e1000_smart_speed_off
444 };
445 
446 enum e1000_serdes_link_state {
447 	e1000_serdes_link_down = 0,
448 	e1000_serdes_link_autoneg_progress,
449 	e1000_serdes_link_autoneg_complete,
450 	e1000_serdes_link_forced_up
451 };
452 
453 #define __le16 u16
454 #define __le32 u32
455 #define __le64 u64
456 /* Receive Descriptor */
457 struct e1000_rx_desc {
458 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
459 	__le16 length;      /* Length of data DMAed into data buffer */
460 	__le16 csum; /* Packet checksum */
461 	u8  status;  /* Descriptor status */
462 	u8  errors;  /* Descriptor Errors */
463 	__le16 special;
464 };
465 
466 /* Receive Descriptor - Extended */
467 union e1000_rx_desc_extended {
468 	struct {
469 		__le64 buffer_addr;
470 		__le64 reserved;
471 	} read;
472 	struct {
473 		struct {
474 			__le32 mrq; /* Multiple Rx Queues */
475 			union {
476 				__le32 rss; /* RSS Hash */
477 				struct {
478 					__le16 ip_id;  /* IP id */
479 					__le16 csum;   /* Packet Checksum */
480 				} csum_ip;
481 			} hi_dword;
482 		} lower;
483 		struct {
484 			__le32 status_error;  /* ext status/error */
485 			__le16 length;
486 			__le16 vlan; /* VLAN tag */
487 		} upper;
488 	} wb;  /* writeback */
489 };
490 
491 #define MAX_PS_BUFFERS 4
492 
493 /* Number of packet split data buffers (not including the header buffer) */
494 #define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
495 
496 /* Receive Descriptor - Packet Split */
497 union e1000_rx_desc_packet_split {
498 	struct {
499 		/* one buffer for protocol header(s), three data buffers */
500 		__le64 buffer_addr[MAX_PS_BUFFERS];
501 	} read;
502 	struct {
503 		struct {
504 			__le32 mrq;  /* Multiple Rx Queues */
505 			union {
506 				__le32 rss; /* RSS Hash */
507 				struct {
508 					__le16 ip_id;    /* IP id */
509 					__le16 csum;     /* Packet Checksum */
510 				} csum_ip;
511 			} hi_dword;
512 		} lower;
513 		struct {
514 			__le32 status_error;  /* ext status/error */
515 			__le16 length0;  /* length of buffer 0 */
516 			__le16 vlan;  /* VLAN tag */
517 		} middle;
518 		struct {
519 			__le16 header_status;
520 			/* length of buffers 1-3 */
521 			__le16 length[PS_PAGE_BUFFERS];
522 		} upper;
523 		__le64 reserved;
524 	} wb; /* writeback */
525 };
526 
527 /* Transmit Descriptor */
528 struct e1000_tx_desc {
529 	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
530 	union {
531 		__le32 data;
532 		struct {
533 			__le16 length;  /* Data buffer length */
534 			u8 cso;  /* Checksum offset */
535 			u8 cmd;  /* Descriptor control */
536 		} flags;
537 	} lower;
538 	union {
539 		__le32 data;
540 		struct {
541 			u8 status; /* Descriptor status */
542 			u8 css;  /* Checksum start */
543 			__le16 special;
544 		} fields;
545 	} upper;
546 };
547 
548 /* Offload Context Descriptor */
549 struct e1000_context_desc {
550 	union {
551 		__le32 ip_config;
552 		struct {
553 			u8 ipcss;  /* IP checksum start */
554 			u8 ipcso;  /* IP checksum offset */
555 			__le16 ipcse;  /* IP checksum end */
556 		} ip_fields;
557 	} lower_setup;
558 	union {
559 		__le32 tcp_config;
560 		struct {
561 			u8 tucss;  /* TCP checksum start */
562 			u8 tucso;  /* TCP checksum offset */
563 			__le16 tucse;  /* TCP checksum end */
564 		} tcp_fields;
565 	} upper_setup;
566 	__le32 cmd_and_length;
567 	union {
568 		__le32 data;
569 		struct {
570 			u8 status;  /* Descriptor status */
571 			u8 hdr_len;  /* Header length */
572 			__le16 mss;  /* Maximum segment size */
573 		} fields;
574 	} tcp_seg_setup;
575 };
576 
577 /* Offload data descriptor */
578 struct e1000_data_desc {
579 	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
580 	union {
581 		__le32 data;
582 		struct {
583 			__le16 length;  /* Data buffer length */
584 			u8 typ_len_ext;
585 			u8 cmd;
586 		} flags;
587 	} lower;
588 	union {
589 		__le32 data;
590 		struct {
591 			u8 status;  /* Descriptor status */
592 			u8 popts;  /* Packet Options */
593 			__le16 special;
594 		} fields;
595 	} upper;
596 };
597 
598 /* Statistics counters collected by the MAC */
599 struct e1000_hw_stats {
600 	u64 crcerrs;
601 	u64 algnerrc;
602 	u64 symerrs;
603 	u64 rxerrc;
604 	u64 mpc;
605 	u64 scc;
606 	u64 ecol;
607 	u64 mcc;
608 	u64 latecol;
609 	u64 colc;
610 	u64 dc;
611 	u64 tncrs;
612 	u64 sec;
613 	u64 cexterr;
614 	u64 rlec;
615 	u64 xonrxc;
616 	u64 xontxc;
617 	u64 xoffrxc;
618 	u64 xofftxc;
619 	u64 fcruc;
620 	u64 prc64;
621 	u64 prc127;
622 	u64 prc255;
623 	u64 prc511;
624 	u64 prc1023;
625 	u64 prc1522;
626 	u64 gprc;
627 	u64 bprc;
628 	u64 mprc;
629 	u64 gptc;
630 	u64 gorc;
631 	u64 gotc;
632 	u64 rnbc;
633 	u64 ruc;
634 	u64 rfc;
635 	u64 roc;
636 	u64 rjc;
637 	u64 mgprc;
638 	u64 mgpdc;
639 	u64 mgptc;
640 	u64 tor;
641 	u64 tot;
642 	u64 tpr;
643 	u64 tpt;
644 	u64 ptc64;
645 	u64 ptc127;
646 	u64 ptc255;
647 	u64 ptc511;
648 	u64 ptc1023;
649 	u64 ptc1522;
650 	u64 mptc;
651 	u64 bptc;
652 	u64 tsctc;
653 	u64 tsctfc;
654 	u64 iac;
655 	u64 icrxptc;
656 	u64 icrxatc;
657 	u64 ictxptc;
658 	u64 ictxatc;
659 	u64 ictxqec;
660 	u64 ictxqmtc;
661 	u64 icrxdmtc;
662 	u64 icrxoc;
663 	u64 cbtmpc;
664 	u64 htdpmc;
665 	u64 cbrdpc;
666 	u64 cbrmpc;
667 	u64 rpthc;
668 	u64 hgptc;
669 	u64 htcbdpc;
670 	u64 hgorc;
671 	u64 hgotc;
672 	u64 lenerrs;
673 	u64 scvpc;
674 	u64 hrmpc;
675 	u64 doosync;
676 	u64 o2bgptc;
677 	u64 o2bspc;
678 	u64 b2ospc;
679 	u64 b2ogprc;
680 };
681 
682 struct e1000_vf_stats {
683 	u64 base_gprc;
684 	u64 base_gptc;
685 	u64 base_gorc;
686 	u64 base_gotc;
687 	u64 base_mprc;
688 	u64 base_gotlbc;
689 	u64 base_gptlbc;
690 	u64 base_gorlbc;
691 	u64 base_gprlbc;
692 
693 	u32 last_gprc;
694 	u32 last_gptc;
695 	u32 last_gorc;
696 	u32 last_gotc;
697 	u32 last_mprc;
698 	u32 last_gotlbc;
699 	u32 last_gptlbc;
700 	u32 last_gorlbc;
701 	u32 last_gprlbc;
702 
703 	u64 gprc;
704 	u64 gptc;
705 	u64 gorc;
706 	u64 gotc;
707 	u64 mprc;
708 	u64 gotlbc;
709 	u64 gptlbc;
710 	u64 gorlbc;
711 	u64 gprlbc;
712 };
713 
714 struct e1000_phy_stats {
715 	u32 idle_errors;
716 	u32 receive_errors;
717 };
718 
719 struct e1000_host_mng_dhcp_cookie {
720 	u32 signature;
721 	u8  status;
722 	u8  reserved0;
723 	u16 vlan_id;
724 	u32 reserved1;
725 	u16 reserved2;
726 	u8  reserved3;
727 	u8  checksum;
728 };
729 
730 /* Host Interface "Rev 1" */
731 struct e1000_host_command_header {
732 	u8 command_id;
733 	u8 command_length;
734 	u8 command_options;
735 	u8 checksum;
736 };
737 
738 #define E1000_HI_MAX_DATA_LENGTH	252
739 struct e1000_host_command_info {
740 	struct e1000_host_command_header command_header;
741 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
742 };
743 
744 /* Host Interface "Rev 2" */
745 struct e1000_host_mng_command_header {
746 	u8  command_id;
747 	u8  checksum;
748 	u16 reserved1;
749 	u16 reserved2;
750 	u16 command_length;
751 };
752 
753 #define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
754 struct e1000_host_mng_command_info {
755 	struct e1000_host_mng_command_header command_header;
756 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
757 };
758 
759 #include "e1000_mac.h"
760 #include "e1000_phy.h"
761 #include "e1000_nvm.h"
762 #include "e1000_manage.h"
763 #include "e1000_mbx.h"
764 
765 /* Function pointers for the MAC. */
766 struct e1000_mac_operations {
767 	s32  (*init_params)(struct e1000_hw *);
768 	s32  (*id_led_init)(struct e1000_hw *);
769 	s32  (*blink_led)(struct e1000_hw *);
770 	bool (*check_mng_mode)(struct e1000_hw *);
771 	s32  (*check_for_link)(struct e1000_hw *);
772 	s32  (*cleanup_led)(struct e1000_hw *);
773 	void (*clear_hw_cntrs)(struct e1000_hw *);
774 	void (*clear_vfta)(struct e1000_hw *);
775 	s32  (*get_bus_info)(struct e1000_hw *);
776 	void (*set_lan_id)(struct e1000_hw *);
777 	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
778 	s32  (*led_on)(struct e1000_hw *);
779 	s32  (*led_off)(struct e1000_hw *);
780 	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
781 	s32  (*reset_hw)(struct e1000_hw *);
782 	s32  (*init_hw)(struct e1000_hw *);
783 	void (*shutdown_serdes)(struct e1000_hw *);
784 	void (*power_up_serdes)(struct e1000_hw *);
785 	s32  (*setup_link)(struct e1000_hw *);
786 	s32  (*setup_physical_interface)(struct e1000_hw *);
787 	s32  (*setup_led)(struct e1000_hw *);
788 	void (*write_vfta)(struct e1000_hw *, u32, u32);
789 	void (*config_collision_dist)(struct e1000_hw *);
790 	int  (*rar_set)(struct e1000_hw *, u8*, u32);
791 	s32  (*read_mac_addr)(struct e1000_hw *);
792 	s32  (*validate_mdi_setting)(struct e1000_hw *);
793 	s32  (*set_obff_timer)(struct e1000_hw *, u32);
794 	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
795 	void (*release_swfw_sync)(struct e1000_hw *, u16);
796 };
797 
798 /* When to use various PHY register access functions:
799  *
800  *                 Func   Caller
801  *   Function      Does   Does    When to use
802  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
803  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
804  *   X_reg_locked  P,A    L       for multiple accesses of different regs
805  *                                on different pages
806  *   X_reg_page    A      L,P     for multiple accesses of different regs
807  *                                on the same page
808  *
809  * Where X=[read|write], L=locking, P=sets page, A=register access
810  *
811  */
812 struct e1000_phy_operations {
813 	s32  (*init_params)(struct e1000_hw *);
814 	s32  (*acquire)(struct e1000_hw *);
815 	s32  (*cfg_on_link_up)(struct e1000_hw *);
816 	s32  (*check_polarity)(struct e1000_hw *);
817 	s32  (*check_reset_block)(struct e1000_hw *);
818 	s32  (*commit)(struct e1000_hw *);
819 	s32  (*force_speed_duplex)(struct e1000_hw *);
820 	s32  (*get_cfg_done)(struct e1000_hw *hw);
821 	s32  (*get_cable_length)(struct e1000_hw *);
822 	s32  (*get_info)(struct e1000_hw *);
823 	s32  (*set_page)(struct e1000_hw *, u16);
824 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
825 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
826 	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
827 	void (*release)(struct e1000_hw *);
828 	s32  (*reset)(struct e1000_hw *);
829 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
830 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
831 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
832 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
833 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
834 	void (*power_up)(struct e1000_hw *);
835 	void (*power_down)(struct e1000_hw *);
836 	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
837 	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
838 };
839 
840 /* Function pointers for the NVM. */
841 struct e1000_nvm_operations {
842 	s32  (*init_params)(struct e1000_hw *);
843 	s32  (*acquire)(struct e1000_hw *);
844 	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
845 	void (*release)(struct e1000_hw *);
846 	void (*reload)(struct e1000_hw *);
847 	s32  (*update)(struct e1000_hw *);
848 	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
849 	s32  (*validate)(struct e1000_hw *);
850 	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
851 };
852 
853 struct e1000_mac_info {
854 	struct e1000_mac_operations ops;
855 	u8 addr[ETH_ADDR_LEN];
856 	u8 perm_addr[ETH_ADDR_LEN];
857 
858 	enum e1000_mac_type type;
859 
860 	u32 collision_delta;
861 	u32 ledctl_default;
862 	u32 ledctl_mode1;
863 	u32 ledctl_mode2;
864 	u32 mc_filter_type;
865 	u32 tx_packet_delta;
866 	u32 txcw;
867 
868 	u16 current_ifs_val;
869 	u16 ifs_max_val;
870 	u16 ifs_min_val;
871 	u16 ifs_ratio;
872 	u16 ifs_step_size;
873 	u16 mta_reg_count;
874 	u16 uta_reg_count;
875 
876 	/* Maximum size of the MTA register table in all supported adapters */
877 #define MAX_MTA_REG 128
878 	u32 mta_shadow[MAX_MTA_REG];
879 	u16 rar_entry_count;
880 
881 	u8  forced_speed_duplex;
882 
883 	bool adaptive_ifs;
884 	bool has_fwsm;
885 	bool arc_subsystem_valid;
886 	bool asf_firmware_present;
887 	bool autoneg;
888 	bool autoneg_failed;
889 	bool get_link_status;
890 	bool in_ifs_mode;
891 	bool report_tx_early;
892 	enum e1000_serdes_link_state serdes_link_state;
893 	bool serdes_has_link;
894 	bool tx_pkt_filtering;
895 	u32  max_frame_size;
896 };
897 
898 struct e1000_phy_info {
899 	struct e1000_phy_operations ops;
900 	enum e1000_phy_type type;
901 
902 	enum e1000_1000t_rx_status local_rx;
903 	enum e1000_1000t_rx_status remote_rx;
904 	enum e1000_ms_type ms_type;
905 	enum e1000_ms_type original_ms_type;
906 	enum e1000_rev_polarity cable_polarity;
907 	enum e1000_smart_speed smart_speed;
908 
909 	u32 addr;
910 	u32 id;
911 	u32 reset_delay_us; /* in usec */
912 	u32 revision;
913 
914 	enum e1000_media_type media_type;
915 
916 	u16 autoneg_advertised;
917 	u16 autoneg_mask;
918 	u16 cable_length;
919 	u16 max_cable_length;
920 	u16 min_cable_length;
921 
922 	u8 mdix;
923 
924 	bool disable_polarity_correction;
925 	bool is_mdix;
926 	bool polarity_correction;
927 	bool speed_downgraded;
928 	bool autoneg_wait_to_complete;
929 };
930 
931 struct e1000_nvm_info {
932 	struct e1000_nvm_operations ops;
933 	enum e1000_nvm_type type;
934 	enum e1000_nvm_override override;
935 
936 	u32 flash_bank_size;
937 	u32 flash_base_addr;
938 
939 	u16 word_size;
940 	u16 delay_usec;
941 	u16 address_bits;
942 	u16 opcode_bits;
943 	u16 page_size;
944 };
945 
946 struct e1000_bus_info {
947 	enum e1000_bus_type type;
948 	enum e1000_bus_speed speed;
949 	enum e1000_bus_width width;
950 
951 	u16 func;
952 	u16 pci_cmd_word;
953 };
954 
955 struct e1000_fc_info {
956 	u32 high_water;  /* Flow control high-water mark */
957 	u32 low_water;  /* Flow control low-water mark */
958 	u16 pause_time;  /* Flow control pause timer */
959 	u16 refresh_time;  /* Flow control refresh timer */
960 	bool send_xon;  /* Flow control send XON */
961 	bool strict_ieee;  /* Strict IEEE mode */
962 	enum e1000_fc_mode current_mode;  /* FC mode in effect */
963 	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
964 };
965 
966 struct e1000_mbx_operations {
967 	s32 (*init_params)(struct e1000_hw *hw);
968 	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
969 	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
970 	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
971 	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
972 	s32 (*check_for_msg)(struct e1000_hw *, u16);
973 	s32 (*check_for_ack)(struct e1000_hw *, u16);
974 	s32 (*check_for_rst)(struct e1000_hw *, u16);
975 };
976 
977 struct e1000_mbx_stats {
978 	u32 msgs_tx;
979 	u32 msgs_rx;
980 
981 	u32 acks;
982 	u32 reqs;
983 	u32 rsts;
984 };
985 
986 struct e1000_mbx_info {
987 	struct e1000_mbx_operations ops;
988 	struct e1000_mbx_stats stats;
989 	u32 timeout;
990 	u32 usec_delay;
991 	u16 size;
992 };
993 
994 struct e1000_dev_spec_82541 {
995 	enum e1000_dsp_config dsp_config;
996 	enum e1000_ffe_config ffe_config;
997 	u32 tx_fifo_head;
998 	u32 tx_fifo_start;
999 	u32 tx_fifo_size;
1000 	u16 dsp_reset_counter;
1001 	u16 spd_default;
1002 	bool phy_init_script;
1003 	bool ttl_workaround;
1004 };
1005 
1006 struct e1000_dev_spec_82542 {
1007 	bool dma_fairness;
1008 };
1009 
1010 struct e1000_dev_spec_82543 {
1011 	u32  tbi_compatibility;
1012 	bool dma_fairness;
1013 	bool init_phy_disabled;
1014 };
1015 
1016 struct e1000_dev_spec_82571 {
1017 	bool laa_is_present;
1018 	u32 smb_counter;
1019 	E1000_MUTEX swflag_mutex;
1020 };
1021 
1022 struct e1000_dev_spec_80003es2lan {
1023 	bool  mdic_wa_enable;
1024 };
1025 
1026 struct e1000_shadow_ram {
1027 	u16  value;
1028 	bool modified;
1029 };
1030 
1031 #define E1000_SHADOW_RAM_WORDS		2048
1032 
1033 /* I218 PHY Ultra Low Power (ULP) states */
1034 enum e1000_ulp_state {
1035 	e1000_ulp_state_unknown,
1036 	e1000_ulp_state_off,
1037 	e1000_ulp_state_on,
1038 };
1039 
1040 struct e1000_dev_spec_ich8lan {
1041 	bool kmrn_lock_loss_workaround_enabled;
1042 	struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
1043 	E1000_MUTEX nvm_mutex;
1044 	E1000_MUTEX swflag_mutex;
1045 	bool nvm_k1_enabled;
1046 	bool disable_k1_off;
1047 	bool eee_disable;
1048 	u16 eee_lp_ability;
1049 	enum e1000_ulp_state ulp_state;
1050 	bool ulp_capability_disabled;
1051 	bool during_suspend_flow;
1052 	bool during_dpg_exit;
1053 };
1054 
1055 struct e1000_dev_spec_82575 {
1056 	bool sgmii_active;
1057 	bool global_device_reset;
1058 	bool eee_disable;
1059 	bool module_plugged;
1060 	bool clear_semaphore_once;
1061 	u32 mtu;
1062 	struct sfp_e1000_flags eth_flags;
1063 	u8 media_port;
1064 	bool media_changed;
1065 };
1066 
1067 struct e1000_dev_spec_vf {
1068 	u32 vf_number;
1069 	u32 v2p_mailbox;
1070 };
1071 
1072 struct e1000_hw {
1073 	void *back;
1074 
1075 	u8 *hw_addr;
1076 	u8 *flash_address;
1077 	unsigned long io_base;
1078 
1079 	struct e1000_mac_info  mac;
1080 	struct e1000_fc_info   fc;
1081 	struct e1000_phy_info  phy;
1082 	struct e1000_nvm_info  nvm;
1083 	struct e1000_bus_info  bus;
1084 	struct e1000_mbx_info mbx;
1085 	struct e1000_host_mng_dhcp_cookie mng_cookie;
1086 
1087 	union {
1088 		struct e1000_dev_spec_82541 _82541;
1089 		struct e1000_dev_spec_82542 _82542;
1090 		struct e1000_dev_spec_82543 _82543;
1091 		struct e1000_dev_spec_82571 _82571;
1092 		struct e1000_dev_spec_80003es2lan _80003es2lan;
1093 		struct e1000_dev_spec_ich8lan ich8lan;
1094 		struct e1000_dev_spec_82575 _82575;
1095 		struct e1000_dev_spec_vf vf;
1096 	} dev_spec;
1097 
1098 	u16 device_id;
1099 	u16 subsystem_vendor_id;
1100 	u16 subsystem_device_id;
1101 	u16 vendor_id;
1102 
1103 	u8  revision_id;
1104 };
1105 
1106 #include "e1000_82541.h"
1107 #include "e1000_82543.h"
1108 #include "e1000_82571.h"
1109 #include "e1000_80003es2lan.h"
1110 #include "e1000_ich8lan.h"
1111 #include "e1000_82575.h"
1112 #include "e1000_i210.h"
1113 
1114 /* These functions must be implemented by drivers */
1115 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1116 void e1000_pci_set_mwi(struct e1000_hw *hw);
1117 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1118 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1119 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1120 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1121 
1122 #endif
1123