1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 131 #define E1000_DEV_ID_PCH2_LV_V 0x1503 132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 150 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 151 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 152 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 153 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 154 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 155 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 156 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 157 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 158 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 159 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 160 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 161 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 162 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 163 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 164 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 165 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 166 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 167 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 168 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 169 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E 170 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F 171 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C 172 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D 173 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 174 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 175 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 176 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 177 #define E1000_DEV_ID_PCH_LNP_I219_LM20 0x550E 178 #define E1000_DEV_ID_PCH_LNP_I219_V20 0x550F 179 #define E1000_DEV_ID_PCH_LNP_I219_LM21 0x5510 180 #define E1000_DEV_ID_PCH_LNP_I219_V21 0x5511 181 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 182 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 183 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 184 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 185 #define E1000_DEV_ID_82576 0x10C9 186 #define E1000_DEV_ID_82576_FIBER 0x10E6 187 #define E1000_DEV_ID_82576_SERDES 0x10E7 188 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 189 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 190 #define E1000_DEV_ID_82576_NS 0x150A 191 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 192 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 193 #define E1000_DEV_ID_82576_VF 0x10CA 194 #define E1000_DEV_ID_82576_VF_HV 0x152D 195 #define E1000_DEV_ID_I350_VF 0x1520 196 #define E1000_DEV_ID_I350_VF_HV 0x152F 197 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 198 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 199 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 200 #define E1000_DEV_ID_82580_COPPER 0x150E 201 #define E1000_DEV_ID_82580_FIBER 0x150F 202 #define E1000_DEV_ID_82580_SERDES 0x1510 203 #define E1000_DEV_ID_82580_SGMII 0x1511 204 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 205 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 206 #define E1000_DEV_ID_I350_COPPER 0x1521 207 #define E1000_DEV_ID_I350_FIBER 0x1522 208 #define E1000_DEV_ID_I350_SERDES 0x1523 209 #define E1000_DEV_ID_I350_SGMII 0x1524 210 #define E1000_DEV_ID_I350_DA4 0x1546 211 #define E1000_DEV_ID_I210_COPPER 0x1533 212 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 213 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 214 #define E1000_DEV_ID_I210_FIBER 0x1536 215 #define E1000_DEV_ID_I210_SERDES 0x1537 216 #define E1000_DEV_ID_I210_SGMII 0x1538 217 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 218 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 219 #define E1000_DEV_ID_I211_COPPER 0x1539 220 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 221 #define E1000_DEV_ID_I354_SGMII 0x1F41 222 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 223 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 224 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 225 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 226 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 227 228 #define E1000_REVISION_0 0 229 #define E1000_REVISION_1 1 230 #define E1000_REVISION_2 2 231 #define E1000_REVISION_3 3 232 #define E1000_REVISION_4 4 233 234 #define E1000_FUNC_0 0 235 #define E1000_FUNC_1 1 236 #define E1000_FUNC_2 2 237 #define E1000_FUNC_3 3 238 239 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 240 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 241 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 242 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 243 244 /* 245 * This enumeration represents all of the different kinds of MAC chips that are 246 * used by both the e1000g and igb drivers. The ordering here is important as 247 * certain classes of MACs are very similar, but have minor differences and so 248 * are compared based on the ordering here. Changing the order here should not 249 * be done arbitrarily. 250 */ 251 enum e1000_mac_type { 252 e1000_undefined = 0, 253 e1000_82542, 254 e1000_82543, 255 e1000_82544, 256 e1000_82540, 257 e1000_82545, 258 e1000_82545_rev_3, 259 e1000_82546, 260 e1000_82546_rev_3, 261 e1000_82541, 262 e1000_82541_rev_2, 263 e1000_82547, 264 e1000_82547_rev_2, 265 e1000_82571, 266 e1000_82572, 267 e1000_82573, 268 e1000_82574, 269 e1000_82583, 270 e1000_80003es2lan, 271 /* 272 * The following MACs all share the ich8 style of hardware and are 273 * implemented in ich8, though some are a little more different than 274 * others. The pch_lpt, pch_spt, pch_cnp, pch_tgp, pch_adp, pch_mtp, 275 * pch_lnp, and pch_rpl families are a bit more different than the 276 * others and just have slight variants in behavior between them. They 277 * are ordered based on release. 278 */ 279 e1000_ich8lan, 280 e1000_ich9lan, 281 e1000_ich10lan, 282 e1000_pchlan, 283 e1000_pch2lan, 284 e1000_pch_lpt, 285 e1000_pch_spt, 286 e1000_pch_cnp, 287 e1000_pch_tgp, 288 e1000_pch_adp, 289 e1000_pch_mtp, 290 e1000_pch_lnp, 291 e1000_pch_rpl, 292 /* 293 * After this point all MACs are used by the igb(4D) driver as opposed 294 * to e1000g(4D). If a new MAC is specific to e1000g series of devices, 295 * then it should be added above this. 296 */ 297 e1000_82575, 298 e1000_82576, 299 e1000_82580, 300 e1000_i350, 301 e1000_i354, 302 e1000_i210, 303 e1000_i211, 304 e1000_vfadapt, 305 e1000_vfadapt_i350, 306 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 307 }; 308 309 enum e1000_media_type { 310 e1000_media_type_unknown = 0, 311 e1000_media_type_copper = 1, 312 e1000_media_type_fiber = 2, 313 e1000_media_type_internal_serdes = 3, 314 e1000_num_media_types 315 }; 316 317 enum e1000_nvm_type { 318 e1000_nvm_unknown = 0, 319 e1000_nvm_none, 320 e1000_nvm_eeprom_spi, 321 e1000_nvm_eeprom_microwire, 322 e1000_nvm_flash_hw, 323 e1000_nvm_invm, 324 e1000_nvm_flash_sw 325 }; 326 327 enum e1000_nvm_override { 328 e1000_nvm_override_none = 0, 329 e1000_nvm_override_spi_small, 330 e1000_nvm_override_spi_large, 331 e1000_nvm_override_microwire_small, 332 e1000_nvm_override_microwire_large 333 }; 334 335 enum e1000_phy_type { 336 e1000_phy_unknown = 0, 337 e1000_phy_none, 338 e1000_phy_m88, 339 e1000_phy_igp, 340 e1000_phy_igp_2, 341 e1000_phy_gg82563, 342 e1000_phy_igp_3, 343 e1000_phy_ife, 344 e1000_phy_bm, 345 e1000_phy_82578, 346 e1000_phy_82577, 347 e1000_phy_82579, 348 e1000_phy_i217, 349 e1000_phy_82580, 350 e1000_phy_vf, 351 e1000_phy_i210, 352 }; 353 354 enum e1000_bus_type { 355 e1000_bus_type_unknown = 0, 356 e1000_bus_type_pci, 357 e1000_bus_type_pcix, 358 e1000_bus_type_pci_express, 359 e1000_bus_type_reserved 360 }; 361 362 enum e1000_bus_speed { 363 e1000_bus_speed_unknown = 0, 364 e1000_bus_speed_33, 365 e1000_bus_speed_66, 366 e1000_bus_speed_100, 367 e1000_bus_speed_120, 368 e1000_bus_speed_133, 369 e1000_bus_speed_2500, 370 e1000_bus_speed_5000, 371 e1000_bus_speed_reserved 372 }; 373 374 enum e1000_bus_width { 375 e1000_bus_width_unknown = 0, 376 e1000_bus_width_pcie_x1, 377 e1000_bus_width_pcie_x2, 378 e1000_bus_width_pcie_x4 = 4, 379 e1000_bus_width_pcie_x8 = 8, 380 e1000_bus_width_32, 381 e1000_bus_width_64, 382 e1000_bus_width_reserved 383 }; 384 385 enum e1000_1000t_rx_status { 386 e1000_1000t_rx_status_not_ok = 0, 387 e1000_1000t_rx_status_ok, 388 e1000_1000t_rx_status_undefined = 0xFF 389 }; 390 391 enum e1000_rev_polarity { 392 e1000_rev_polarity_normal = 0, 393 e1000_rev_polarity_reversed, 394 e1000_rev_polarity_undefined = 0xFF 395 }; 396 397 enum e1000_fc_mode { 398 e1000_fc_none = 0, 399 e1000_fc_rx_pause, 400 e1000_fc_tx_pause, 401 e1000_fc_full, 402 e1000_fc_default = 0xFF 403 }; 404 405 enum e1000_ffe_config { 406 e1000_ffe_config_enabled = 0, 407 e1000_ffe_config_active, 408 e1000_ffe_config_blocked 409 }; 410 411 enum e1000_dsp_config { 412 e1000_dsp_config_disabled = 0, 413 e1000_dsp_config_enabled, 414 e1000_dsp_config_activated, 415 e1000_dsp_config_undefined = 0xFF 416 }; 417 418 enum e1000_ms_type { 419 e1000_ms_hw_default = 0, 420 e1000_ms_force_master, 421 e1000_ms_force_slave, 422 e1000_ms_auto 423 }; 424 425 enum e1000_smart_speed { 426 e1000_smart_speed_default = 0, 427 e1000_smart_speed_on, 428 e1000_smart_speed_off 429 }; 430 431 enum e1000_serdes_link_state { 432 e1000_serdes_link_down = 0, 433 e1000_serdes_link_autoneg_progress, 434 e1000_serdes_link_autoneg_complete, 435 e1000_serdes_link_forced_up 436 }; 437 438 #define __le16 u16 439 #define __le32 u32 440 #define __le64 u64 441 /* Receive Descriptor */ 442 struct e1000_rx_desc { 443 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 444 __le16 length; /* Length of data DMAed into data buffer */ 445 __le16 csum; /* Packet checksum */ 446 u8 status; /* Descriptor status */ 447 u8 errors; /* Descriptor Errors */ 448 __le16 special; 449 }; 450 451 /* Receive Descriptor - Extended */ 452 union e1000_rx_desc_extended { 453 struct { 454 __le64 buffer_addr; 455 __le64 reserved; 456 } read; 457 struct { 458 struct { 459 __le32 mrq; /* Multiple Rx Queues */ 460 union { 461 __le32 rss; /* RSS Hash */ 462 struct { 463 __le16 ip_id; /* IP id */ 464 __le16 csum; /* Packet Checksum */ 465 } csum_ip; 466 } hi_dword; 467 } lower; 468 struct { 469 __le32 status_error; /* ext status/error */ 470 __le16 length; 471 __le16 vlan; /* VLAN tag */ 472 } upper; 473 } wb; /* writeback */ 474 }; 475 476 #define MAX_PS_BUFFERS 4 477 478 /* Number of packet split data buffers (not including the header buffer) */ 479 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 480 481 /* Receive Descriptor - Packet Split */ 482 union e1000_rx_desc_packet_split { 483 struct { 484 /* one buffer for protocol header(s), three data buffers */ 485 __le64 buffer_addr[MAX_PS_BUFFERS]; 486 } read; 487 struct { 488 struct { 489 __le32 mrq; /* Multiple Rx Queues */ 490 union { 491 __le32 rss; /* RSS Hash */ 492 struct { 493 __le16 ip_id; /* IP id */ 494 __le16 csum; /* Packet Checksum */ 495 } csum_ip; 496 } hi_dword; 497 } lower; 498 struct { 499 __le32 status_error; /* ext status/error */ 500 __le16 length0; /* length of buffer 0 */ 501 __le16 vlan; /* VLAN tag */ 502 } middle; 503 struct { 504 __le16 header_status; 505 /* length of buffers 1-3 */ 506 __le16 length[PS_PAGE_BUFFERS]; 507 } upper; 508 __le64 reserved; 509 } wb; /* writeback */ 510 }; 511 512 /* Transmit Descriptor */ 513 struct e1000_tx_desc { 514 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 515 union { 516 __le32 data; 517 struct { 518 __le16 length; /* Data buffer length */ 519 u8 cso; /* Checksum offset */ 520 u8 cmd; /* Descriptor control */ 521 } flags; 522 } lower; 523 union { 524 __le32 data; 525 struct { 526 u8 status; /* Descriptor status */ 527 u8 css; /* Checksum start */ 528 __le16 special; 529 } fields; 530 } upper; 531 }; 532 533 /* Offload Context Descriptor */ 534 struct e1000_context_desc { 535 union { 536 __le32 ip_config; 537 struct { 538 u8 ipcss; /* IP checksum start */ 539 u8 ipcso; /* IP checksum offset */ 540 __le16 ipcse; /* IP checksum end */ 541 } ip_fields; 542 } lower_setup; 543 union { 544 __le32 tcp_config; 545 struct { 546 u8 tucss; /* TCP checksum start */ 547 u8 tucso; /* TCP checksum offset */ 548 __le16 tucse; /* TCP checksum end */ 549 } tcp_fields; 550 } upper_setup; 551 __le32 cmd_and_length; 552 union { 553 __le32 data; 554 struct { 555 u8 status; /* Descriptor status */ 556 u8 hdr_len; /* Header length */ 557 __le16 mss; /* Maximum segment size */ 558 } fields; 559 } tcp_seg_setup; 560 }; 561 562 /* Offload data descriptor */ 563 struct e1000_data_desc { 564 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 565 union { 566 __le32 data; 567 struct { 568 __le16 length; /* Data buffer length */ 569 u8 typ_len_ext; 570 u8 cmd; 571 } flags; 572 } lower; 573 union { 574 __le32 data; 575 struct { 576 u8 status; /* Descriptor status */ 577 u8 popts; /* Packet Options */ 578 __le16 special; 579 } fields; 580 } upper; 581 }; 582 583 /* Statistics counters collected by the MAC */ 584 struct e1000_hw_stats { 585 u64 crcerrs; 586 u64 algnerrc; 587 u64 symerrs; 588 u64 rxerrc; 589 u64 mpc; 590 u64 scc; 591 u64 ecol; 592 u64 mcc; 593 u64 latecol; 594 u64 colc; 595 u64 dc; 596 u64 tncrs; 597 u64 sec; 598 u64 cexterr; 599 u64 rlec; 600 u64 xonrxc; 601 u64 xontxc; 602 u64 xoffrxc; 603 u64 xofftxc; 604 u64 fcruc; 605 u64 prc64; 606 u64 prc127; 607 u64 prc255; 608 u64 prc511; 609 u64 prc1023; 610 u64 prc1522; 611 u64 gprc; 612 u64 bprc; 613 u64 mprc; 614 u64 gptc; 615 u64 gorc; 616 u64 gotc; 617 u64 rnbc; 618 u64 ruc; 619 u64 rfc; 620 u64 roc; 621 u64 rjc; 622 u64 mgprc; 623 u64 mgpdc; 624 u64 mgptc; 625 u64 tor; 626 u64 tot; 627 u64 tpr; 628 u64 tpt; 629 u64 ptc64; 630 u64 ptc127; 631 u64 ptc255; 632 u64 ptc511; 633 u64 ptc1023; 634 u64 ptc1522; 635 u64 mptc; 636 u64 bptc; 637 u64 tsctc; 638 u64 tsctfc; 639 u64 iac; 640 u64 icrxptc; 641 u64 icrxatc; 642 u64 ictxptc; 643 u64 ictxatc; 644 u64 ictxqec; 645 u64 ictxqmtc; 646 u64 icrxdmtc; 647 u64 icrxoc; 648 u64 cbtmpc; 649 u64 htdpmc; 650 u64 cbrdpc; 651 u64 cbrmpc; 652 u64 rpthc; 653 u64 hgptc; 654 u64 htcbdpc; 655 u64 hgorc; 656 u64 hgotc; 657 u64 lenerrs; 658 u64 scvpc; 659 u64 hrmpc; 660 u64 doosync; 661 u64 o2bgptc; 662 u64 o2bspc; 663 u64 b2ospc; 664 u64 b2ogprc; 665 }; 666 667 struct e1000_vf_stats { 668 u64 base_gprc; 669 u64 base_gptc; 670 u64 base_gorc; 671 u64 base_gotc; 672 u64 base_mprc; 673 u64 base_gotlbc; 674 u64 base_gptlbc; 675 u64 base_gorlbc; 676 u64 base_gprlbc; 677 678 u32 last_gprc; 679 u32 last_gptc; 680 u32 last_gorc; 681 u32 last_gotc; 682 u32 last_mprc; 683 u32 last_gotlbc; 684 u32 last_gptlbc; 685 u32 last_gorlbc; 686 u32 last_gprlbc; 687 688 u64 gprc; 689 u64 gptc; 690 u64 gorc; 691 u64 gotc; 692 u64 mprc; 693 u64 gotlbc; 694 u64 gptlbc; 695 u64 gorlbc; 696 u64 gprlbc; 697 }; 698 699 struct e1000_phy_stats { 700 u32 idle_errors; 701 u32 receive_errors; 702 }; 703 704 struct e1000_host_mng_dhcp_cookie { 705 u32 signature; 706 u8 status; 707 u8 reserved0; 708 u16 vlan_id; 709 u32 reserved1; 710 u16 reserved2; 711 u8 reserved3; 712 u8 checksum; 713 }; 714 715 /* Host Interface "Rev 1" */ 716 struct e1000_host_command_header { 717 u8 command_id; 718 u8 command_length; 719 u8 command_options; 720 u8 checksum; 721 }; 722 723 #define E1000_HI_MAX_DATA_LENGTH 252 724 struct e1000_host_command_info { 725 struct e1000_host_command_header command_header; 726 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 727 }; 728 729 /* Host Interface "Rev 2" */ 730 struct e1000_host_mng_command_header { 731 u8 command_id; 732 u8 checksum; 733 u16 reserved1; 734 u16 reserved2; 735 u16 command_length; 736 }; 737 738 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 739 struct e1000_host_mng_command_info { 740 struct e1000_host_mng_command_header command_header; 741 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 742 }; 743 744 #include "e1000_mac.h" 745 #include "e1000_phy.h" 746 #include "e1000_nvm.h" 747 #include "e1000_manage.h" 748 #include "e1000_mbx.h" 749 750 /* Function pointers for the MAC. */ 751 struct e1000_mac_operations { 752 s32 (*init_params)(struct e1000_hw *); 753 s32 (*id_led_init)(struct e1000_hw *); 754 s32 (*blink_led)(struct e1000_hw *); 755 bool (*check_mng_mode)(struct e1000_hw *); 756 s32 (*check_for_link)(struct e1000_hw *); 757 s32 (*cleanup_led)(struct e1000_hw *); 758 void (*clear_hw_cntrs)(struct e1000_hw *); 759 void (*clear_vfta)(struct e1000_hw *); 760 s32 (*get_bus_info)(struct e1000_hw *); 761 void (*set_lan_id)(struct e1000_hw *); 762 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 763 s32 (*led_on)(struct e1000_hw *); 764 s32 (*led_off)(struct e1000_hw *); 765 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 766 s32 (*reset_hw)(struct e1000_hw *); 767 s32 (*init_hw)(struct e1000_hw *); 768 void (*shutdown_serdes)(struct e1000_hw *); 769 void (*power_up_serdes)(struct e1000_hw *); 770 s32 (*setup_link)(struct e1000_hw *); 771 s32 (*setup_physical_interface)(struct e1000_hw *); 772 s32 (*setup_led)(struct e1000_hw *); 773 void (*write_vfta)(struct e1000_hw *, u32, u32); 774 void (*config_collision_dist)(struct e1000_hw *); 775 int (*rar_set)(struct e1000_hw *, u8*, u32); 776 s32 (*read_mac_addr)(struct e1000_hw *); 777 s32 (*validate_mdi_setting)(struct e1000_hw *); 778 s32 (*set_obff_timer)(struct e1000_hw *, u32); 779 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 780 void (*release_swfw_sync)(struct e1000_hw *, u16); 781 }; 782 783 /* When to use various PHY register access functions: 784 * 785 * Func Caller 786 * Function Does Does When to use 787 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 788 * X_reg L,P,A n/a for simple PHY reg accesses 789 * X_reg_locked P,A L for multiple accesses of different regs 790 * on different pages 791 * X_reg_page A L,P for multiple accesses of different regs 792 * on the same page 793 * 794 * Where X=[read|write], L=locking, P=sets page, A=register access 795 * 796 */ 797 struct e1000_phy_operations { 798 s32 (*init_params)(struct e1000_hw *); 799 s32 (*acquire)(struct e1000_hw *); 800 s32 (*cfg_on_link_up)(struct e1000_hw *); 801 s32 (*check_polarity)(struct e1000_hw *); 802 s32 (*check_reset_block)(struct e1000_hw *); 803 s32 (*commit)(struct e1000_hw *); 804 s32 (*force_speed_duplex)(struct e1000_hw *); 805 s32 (*get_cfg_done)(struct e1000_hw *hw); 806 s32 (*get_cable_length)(struct e1000_hw *); 807 s32 (*get_info)(struct e1000_hw *); 808 s32 (*set_page)(struct e1000_hw *, u16); 809 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 810 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 811 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 812 void (*release)(struct e1000_hw *); 813 s32 (*reset)(struct e1000_hw *); 814 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 815 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 816 s32 (*write_reg)(struct e1000_hw *, u32, u16); 817 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 818 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 819 void (*power_up)(struct e1000_hw *); 820 void (*power_down)(struct e1000_hw *); 821 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 822 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 823 }; 824 825 /* Function pointers for the NVM. */ 826 struct e1000_nvm_operations { 827 s32 (*init_params)(struct e1000_hw *); 828 s32 (*acquire)(struct e1000_hw *); 829 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 830 void (*release)(struct e1000_hw *); 831 void (*reload)(struct e1000_hw *); 832 s32 (*update)(struct e1000_hw *); 833 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 834 s32 (*validate)(struct e1000_hw *); 835 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 836 }; 837 838 struct e1000_mac_info { 839 struct e1000_mac_operations ops; 840 u8 addr[ETH_ADDR_LEN]; 841 u8 perm_addr[ETH_ADDR_LEN]; 842 843 enum e1000_mac_type type; 844 845 u32 collision_delta; 846 u32 ledctl_default; 847 u32 ledctl_mode1; 848 u32 ledctl_mode2; 849 u32 mc_filter_type; 850 u32 tx_packet_delta; 851 u32 txcw; 852 853 u16 current_ifs_val; 854 u16 ifs_max_val; 855 u16 ifs_min_val; 856 u16 ifs_ratio; 857 u16 ifs_step_size; 858 u16 mta_reg_count; 859 u16 uta_reg_count; 860 861 /* Maximum size of the MTA register table in all supported adapters */ 862 #define MAX_MTA_REG 128 863 u32 mta_shadow[MAX_MTA_REG]; 864 u16 rar_entry_count; 865 866 u8 forced_speed_duplex; 867 868 bool adaptive_ifs; 869 bool has_fwsm; 870 bool arc_subsystem_valid; 871 bool asf_firmware_present; 872 bool autoneg; 873 bool autoneg_failed; 874 bool get_link_status; 875 bool in_ifs_mode; 876 bool report_tx_early; 877 enum e1000_serdes_link_state serdes_link_state; 878 bool serdes_has_link; 879 bool tx_pkt_filtering; 880 u32 max_frame_size; 881 }; 882 883 struct e1000_phy_info { 884 struct e1000_phy_operations ops; 885 enum e1000_phy_type type; 886 887 enum e1000_1000t_rx_status local_rx; 888 enum e1000_1000t_rx_status remote_rx; 889 enum e1000_ms_type ms_type; 890 enum e1000_ms_type original_ms_type; 891 enum e1000_rev_polarity cable_polarity; 892 enum e1000_smart_speed smart_speed; 893 894 u32 addr; 895 u32 id; 896 u32 reset_delay_us; /* in usec */ 897 u32 revision; 898 899 enum e1000_media_type media_type; 900 901 u16 autoneg_advertised; 902 u16 autoneg_mask; 903 u16 cable_length; 904 u16 max_cable_length; 905 u16 min_cable_length; 906 907 u8 mdix; 908 909 bool disable_polarity_correction; 910 bool is_mdix; 911 bool polarity_correction; 912 bool speed_downgraded; 913 bool autoneg_wait_to_complete; 914 }; 915 916 struct e1000_nvm_info { 917 struct e1000_nvm_operations ops; 918 enum e1000_nvm_type type; 919 enum e1000_nvm_override override; 920 921 u32 flash_bank_size; 922 u32 flash_base_addr; 923 924 u16 word_size; 925 u16 delay_usec; 926 u16 address_bits; 927 u16 opcode_bits; 928 u16 page_size; 929 }; 930 931 struct e1000_bus_info { 932 enum e1000_bus_type type; 933 enum e1000_bus_speed speed; 934 enum e1000_bus_width width; 935 936 u16 func; 937 u16 pci_cmd_word; 938 }; 939 940 struct e1000_fc_info { 941 u32 high_water; /* Flow control high-water mark */ 942 u32 low_water; /* Flow control low-water mark */ 943 u16 pause_time; /* Flow control pause timer */ 944 u16 refresh_time; /* Flow control refresh timer */ 945 bool send_xon; /* Flow control send XON */ 946 bool strict_ieee; /* Strict IEEE mode */ 947 enum e1000_fc_mode current_mode; /* FC mode in effect */ 948 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 949 }; 950 951 struct e1000_mbx_operations { 952 s32 (*init_params)(struct e1000_hw *hw); 953 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 954 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 955 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 956 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 957 s32 (*check_for_msg)(struct e1000_hw *, u16); 958 s32 (*check_for_ack)(struct e1000_hw *, u16); 959 s32 (*check_for_rst)(struct e1000_hw *, u16); 960 }; 961 962 struct e1000_mbx_stats { 963 u32 msgs_tx; 964 u32 msgs_rx; 965 966 u32 acks; 967 u32 reqs; 968 u32 rsts; 969 }; 970 971 struct e1000_mbx_info { 972 struct e1000_mbx_operations ops; 973 struct e1000_mbx_stats stats; 974 u32 timeout; 975 u32 usec_delay; 976 u16 size; 977 }; 978 979 struct e1000_dev_spec_82541 { 980 enum e1000_dsp_config dsp_config; 981 enum e1000_ffe_config ffe_config; 982 u32 tx_fifo_head; 983 u32 tx_fifo_start; 984 u32 tx_fifo_size; 985 u16 dsp_reset_counter; 986 u16 spd_default; 987 bool phy_init_script; 988 bool ttl_workaround; 989 }; 990 991 struct e1000_dev_spec_82542 { 992 bool dma_fairness; 993 }; 994 995 struct e1000_dev_spec_82543 { 996 u32 tbi_compatibility; 997 bool dma_fairness; 998 bool init_phy_disabled; 999 }; 1000 1001 struct e1000_dev_spec_82571 { 1002 bool laa_is_present; 1003 u32 smb_counter; 1004 E1000_MUTEX swflag_mutex; 1005 }; 1006 1007 struct e1000_dev_spec_80003es2lan { 1008 bool mdic_wa_enable; 1009 }; 1010 1011 struct e1000_shadow_ram { 1012 u16 value; 1013 bool modified; 1014 }; 1015 1016 #define E1000_SHADOW_RAM_WORDS 2048 1017 1018 /* I218 PHY Ultra Low Power (ULP) states */ 1019 enum e1000_ulp_state { 1020 e1000_ulp_state_unknown, 1021 e1000_ulp_state_off, 1022 e1000_ulp_state_on, 1023 }; 1024 1025 struct e1000_dev_spec_ich8lan { 1026 bool kmrn_lock_loss_workaround_enabled; 1027 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1028 E1000_MUTEX nvm_mutex; 1029 E1000_MUTEX swflag_mutex; 1030 bool nvm_k1_enabled; 1031 bool disable_k1_off; 1032 bool eee_disable; 1033 u16 eee_lp_ability; 1034 enum e1000_ulp_state ulp_state; 1035 bool ulp_capability_disabled; 1036 bool during_suspend_flow; 1037 bool during_dpg_exit; 1038 }; 1039 1040 struct e1000_dev_spec_82575 { 1041 bool sgmii_active; 1042 bool global_device_reset; 1043 bool eee_disable; 1044 bool module_plugged; 1045 bool clear_semaphore_once; 1046 u32 mtu; 1047 struct sfp_e1000_flags eth_flags; 1048 u8 media_port; 1049 bool media_changed; 1050 }; 1051 1052 struct e1000_dev_spec_vf { 1053 u32 vf_number; 1054 u32 v2p_mailbox; 1055 }; 1056 1057 struct e1000_hw { 1058 void *back; 1059 1060 u8 *hw_addr; 1061 u8 *flash_address; 1062 unsigned long io_base; 1063 1064 struct e1000_mac_info mac; 1065 struct e1000_fc_info fc; 1066 struct e1000_phy_info phy; 1067 struct e1000_nvm_info nvm; 1068 struct e1000_bus_info bus; 1069 struct e1000_mbx_info mbx; 1070 struct e1000_host_mng_dhcp_cookie mng_cookie; 1071 1072 union { 1073 struct e1000_dev_spec_82541 _82541; 1074 struct e1000_dev_spec_82542 _82542; 1075 struct e1000_dev_spec_82543 _82543; 1076 struct e1000_dev_spec_82571 _82571; 1077 struct e1000_dev_spec_80003es2lan _80003es2lan; 1078 struct e1000_dev_spec_ich8lan ich8lan; 1079 struct e1000_dev_spec_82575 _82575; 1080 struct e1000_dev_spec_vf vf; 1081 } dev_spec; 1082 1083 u16 device_id; 1084 u16 subsystem_vendor_id; 1085 u16 subsystem_device_id; 1086 u16 vendor_id; 1087 1088 u8 revision_id; 1089 }; 1090 1091 #include "e1000_82541.h" 1092 #include "e1000_82543.h" 1093 #include "e1000_82571.h" 1094 #include "e1000_80003es2lan.h" 1095 #include "e1000_ich8lan.h" 1096 #include "e1000_82575.h" 1097 #include "e1000_i210.h" 1098 1099 /* These functions must be implemented by drivers */ 1100 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1101 void e1000_pci_set_mwi(struct e1000_hw *hw); 1102 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1103 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1104 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1105 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1106 1107 #endif 1108