xref: /illumos-gate/usr/src/uts/common/io/e1000api/e1000_82541.c (revision 49b7860084dbba18bc00b29413d6182197f9fe93)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2015, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 /*
36  * 82541EI Gigabit Ethernet Controller
37  * 82541ER Gigabit Ethernet Controller
38  * 82541GI Gigabit Ethernet Controller
39  * 82541PI Gigabit Ethernet Controller
40  * 82547EI Gigabit Ethernet Controller
41  * 82547GI Gigabit Ethernet Controller
42  */
43 
44 #include "e1000_api.h"
45 
46 static s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
47 static s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
48 static s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
49 static s32  e1000_reset_hw_82541(struct e1000_hw *hw);
50 static s32  e1000_init_hw_82541(struct e1000_hw *hw);
51 static s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
52 					 u16 *duplex);
53 static s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
54 static s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
55 static s32  e1000_check_for_link_82541(struct e1000_hw *hw);
56 static s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
57 static s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
58 					  bool active);
59 static s32  e1000_setup_led_82541(struct e1000_hw *hw);
60 static s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
62 static s32  e1000_read_mac_addr_82541(struct e1000_hw *hw);
63 static s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
64 						     bool link_up);
65 static s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
66 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
67 
68 static const u16 e1000_igp_cable_length_table[] = {
69 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
70 	10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
71 	40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
72 	60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,
73 	80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,
74 	100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,
75 	110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,
76 	120, 120, 120, 120, 120, 120, 120, 120};
77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
78 		(sizeof(e1000_igp_cable_length_table) / \
79 		 sizeof(e1000_igp_cable_length_table[0]))
80 
81 /**
82  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
83  *  @hw: pointer to the HW structure
84  **/
e1000_init_phy_params_82541(struct e1000_hw * hw)85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86 {
87 	struct e1000_phy_info *phy = &hw->phy;
88 	s32 ret_val;
89 
90 	DEBUGFUNC("e1000_init_phy_params_82541");
91 
92 	phy->addr		= 1;
93 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 	phy->reset_delay_us	= 10000;
95 	phy->type		= e1000_phy_igp;
96 
97 	/* Function Pointers */
98 	phy->ops.check_polarity	= e1000_check_polarity_igp;
99 	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
100 	phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
101 	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
102 	phy->ops.get_info	= e1000_get_phy_info_igp;
103 	phy->ops.read_reg	= e1000_read_phy_reg_igp;
104 	phy->ops.reset		= e1000_phy_hw_reset_82541;
105 	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
106 	phy->ops.write_reg	= e1000_write_phy_reg_igp;
107 	phy->ops.power_up	= e1000_power_up_phy_copper;
108 	phy->ops.power_down	= e1000_power_down_phy_copper_82541;
109 
110 	ret_val = e1000_get_phy_id(hw);
111 	if (ret_val)
112 		goto out;
113 
114 	/* Verify phy id */
115 	if (phy->id != IGP01E1000_I_PHY_ID) {
116 		ret_val = -E1000_ERR_PHY;
117 		goto out;
118 	}
119 
120 out:
121 	return ret_val;
122 }
123 
124 /**
125  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
126  *  @hw: pointer to the HW structure
127  **/
e1000_init_nvm_params_82541(struct e1000_hw * hw)128 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
129 {
130 	struct e1000_nvm_info *nvm = &hw->nvm;
131 	s32 ret_val = E1000_SUCCESS;
132 	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
133 	u16 size;
134 
135 	DEBUGFUNC("e1000_init_nvm_params_82541");
136 
137 	switch (nvm->override) {
138 	case e1000_nvm_override_spi_large:
139 		nvm->type = e1000_nvm_eeprom_spi;
140 		eecd |= E1000_EECD_ADDR_BITS;
141 		break;
142 	case e1000_nvm_override_spi_small:
143 		nvm->type = e1000_nvm_eeprom_spi;
144 		eecd &= ~E1000_EECD_ADDR_BITS;
145 		break;
146 	case e1000_nvm_override_microwire_large:
147 		nvm->type = e1000_nvm_eeprom_microwire;
148 		eecd |= E1000_EECD_SIZE;
149 		break;
150 	case e1000_nvm_override_microwire_small:
151 		nvm->type = e1000_nvm_eeprom_microwire;
152 		eecd &= ~E1000_EECD_SIZE;
153 		break;
154 	default:
155 		nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
156 			    : e1000_nvm_eeprom_microwire;
157 		break;
158 	}
159 
160 	if (nvm->type == e1000_nvm_eeprom_spi) {
161 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
162 		nvm->delay_usec = 1;
163 		nvm->opcode_bits = 8;
164 		nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
165 
166 		/* Function Pointers */
167 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
168 		nvm->ops.read		= e1000_read_nvm_spi;
169 		nvm->ops.release	= e1000_release_nvm_generic;
170 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
171 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
172 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
173 		nvm->ops.write		= e1000_write_nvm_spi;
174 
175 		/*
176 		 * nvm->word_size must be discovered after the pointers
177 		 * are set so we can verify the size from the nvm image
178 		 * itself.  Temporarily set it to a dummy value so the
179 		 * read will work.
180 		 */
181 		nvm->word_size = 64;
182 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
183 		if (ret_val)
184 			goto out;
185 		size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
186 		/*
187 		 * if size != 0, it can be added to a constant and become
188 		 * the left-shift value to set the word_size.  Otherwise,
189 		 * word_size stays at 64.
190 		 */
191 		if (size) {
192 			size += NVM_WORD_SIZE_BASE_SHIFT_82541;
193 			nvm->word_size = 1 << size;
194 		}
195 	} else {
196 		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
197 		nvm->delay_usec = 50;
198 		nvm->opcode_bits = 3;
199 		nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
200 
201 		/* Function Pointers */
202 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
203 		nvm->ops.read		= e1000_read_nvm_microwire;
204 		nvm->ops.release	= e1000_release_nvm_generic;
205 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
206 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
207 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
208 		nvm->ops.write		= e1000_write_nvm_microwire;
209 	}
210 
211 out:
212 	return ret_val;
213 }
214 
215 /**
216  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
217  *  @hw: pointer to the HW structure
218  **/
e1000_init_mac_params_82541(struct e1000_hw * hw)219 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
220 {
221 	struct e1000_mac_info *mac = &hw->mac;
222 
223 	DEBUGFUNC("e1000_init_mac_params_82541");
224 
225 	/* Set media type */
226 	hw->phy.media_type = e1000_media_type_copper;
227 	/* Set mta register count */
228 	mac->mta_reg_count = 128;
229 	/* Set rar entry count */
230 	mac->rar_entry_count = E1000_RAR_ENTRIES;
231 	/* Set if part includes ASF firmware */
232 	mac->asf_firmware_present = TRUE;
233 
234 	/* Function Pointers */
235 
236 	/* bus type/speed/width */
237 	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
238 	/* function id */
239 	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
240 	/* reset */
241 	mac->ops.reset_hw = e1000_reset_hw_82541;
242 	/* hw initialization */
243 	mac->ops.init_hw = e1000_init_hw_82541;
244 	/* link setup */
245 	mac->ops.setup_link = e1000_setup_link_generic;
246 	/* physical interface link setup */
247 	mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
248 	/* check for link */
249 	mac->ops.check_for_link = e1000_check_for_link_82541;
250 	/* link info */
251 	mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
252 	/* multicast address update */
253 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
254 	/* writing VFTA */
255 	mac->ops.write_vfta = e1000_write_vfta_generic;
256 	/* clearing VFTA */
257 	mac->ops.clear_vfta = e1000_clear_vfta_generic;
258 	/* read mac address */
259 	mac->ops.read_mac_addr = e1000_read_mac_addr_82541;
260 	/* ID LED init */
261 	mac->ops.id_led_init = e1000_id_led_init_generic;
262 	/* setup LED */
263 	mac->ops.setup_led = e1000_setup_led_82541;
264 	/* cleanup LED */
265 	mac->ops.cleanup_led = e1000_cleanup_led_82541;
266 	/* turn on/off LED */
267 	mac->ops.led_on = e1000_led_on_generic;
268 	mac->ops.led_off = e1000_led_off_generic;
269 	/* clear hardware counters */
270 	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
271 
272 	return E1000_SUCCESS;
273 }
274 
275 /**
276  *  e1000_init_function_pointers_82541 - Init func ptrs.
277  *  @hw: pointer to the HW structure
278  *
279  *  Called to initialize all function pointers and parameters.
280  **/
e1000_init_function_pointers_82541(struct e1000_hw * hw)281 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
282 {
283 	DEBUGFUNC("e1000_init_function_pointers_82541");
284 
285 	hw->mac.ops.init_params = e1000_init_mac_params_82541;
286 	hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
287 	hw->phy.ops.init_params = e1000_init_phy_params_82541;
288 }
289 
290 /**
291  *  e1000_reset_hw_82541 - Reset hardware
292  *  @hw: pointer to the HW structure
293  *
294  *  This resets the hardware into a known state.
295  **/
e1000_reset_hw_82541(struct e1000_hw * hw)296 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
297 {
298 	u32 ledctl, ctrl, manc;
299 
300 	DEBUGFUNC("e1000_reset_hw_82541");
301 
302 	DEBUGOUT("Masking off all interrupts\n");
303 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
304 
305 	E1000_WRITE_REG(hw, E1000_RCTL, 0);
306 	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
307 	E1000_WRITE_FLUSH(hw);
308 
309 	/*
310 	 * Delay to allow any outstanding PCI transactions to complete
311 	 * before resetting the device.
312 	 */
313 	msec_delay(10);
314 
315 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
316 
317 	/* Must reset the Phy before resetting the MAC */
318 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
319 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
320 		E1000_WRITE_FLUSH(hw);
321 		msec_delay(5);
322 	}
323 
324 	DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
325 	switch (hw->mac.type) {
326 	case e1000_82541:
327 	case e1000_82541_rev_2:
328 		/*
329 		 * These controllers can't ack the 64-bit write when
330 		 * issuing the reset, so we use IO-mapping as a
331 		 * workaround to issue the reset.
332 		 */
333 		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
334 		break;
335 	default:
336 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
337 		break;
338 	}
339 
340 	/* Wait for NVM reload */
341 	msec_delay(20);
342 
343 	/* Disable HW ARPs on ASF enabled adapters */
344 	manc = E1000_READ_REG(hw, E1000_MANC);
345 	manc &= ~E1000_MANC_ARP_EN;
346 	E1000_WRITE_REG(hw, E1000_MANC, manc);
347 
348 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
349 		e1000_phy_init_script_82541(hw);
350 
351 		/* Configure activity LED after Phy reset */
352 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
353 		ledctl &= IGP_ACTIVITY_LED_MASK;
354 		ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
355 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
356 	}
357 
358 	/* Once again, mask the interrupts */
359 	DEBUGOUT("Masking off all interrupts\n");
360 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
361 
362 	/* Clear any pending interrupt events. */
363 	E1000_READ_REG(hw, E1000_ICR);
364 
365 	return E1000_SUCCESS;
366 }
367 
368 /**
369  *  e1000_init_hw_82541 - Initialize hardware
370  *  @hw: pointer to the HW structure
371  *
372  *  This inits the hardware readying it for operation.
373  **/
e1000_init_hw_82541(struct e1000_hw * hw)374 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
375 {
376 	struct e1000_mac_info *mac = &hw->mac;
377 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
378 	u32 i, txdctl;
379 	s32 ret_val;
380 
381 	DEBUGFUNC("e1000_init_hw_82541");
382 
383 	/* Initialize identification LED */
384 	ret_val = mac->ops.id_led_init(hw);
385 	if (ret_val) {
386 		DEBUGOUT("Error initializing identification LED\n");
387 		/* This is not fatal and we should not stop init due to this */
388 	}
389 
390 	/* Storing the Speed Power Down  value for later use */
391 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
392 				       &dev_spec->spd_default);
393 	if (ret_val)
394 		goto out;
395 
396 	/* Disabling VLAN filtering */
397 	DEBUGOUT("Initializing the IEEE VLAN\n");
398 	mac->ops.clear_vfta(hw);
399 
400 	/* Setup the receive address. */
401 	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
402 
403 	/* Zero out the Multicast HASH table */
404 	DEBUGOUT("Zeroing the MTA\n");
405 	for (i = 0; i < mac->mta_reg_count; i++) {
406 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
407 		/*
408 		 * Avoid back to back register writes by adding the register
409 		 * read (flush).  This is to protect against some strange
410 		 * bridge configurations that may issue Memory Write Block
411 		 * (MWB) to our register space.
412 		 */
413 		E1000_WRITE_FLUSH(hw);
414 	}
415 
416 	/* Setup link and flow control */
417 	ret_val = mac->ops.setup_link(hw);
418 
419 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
420 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
421 		  E1000_TXDCTL_FULL_TX_DESC_WB;
422 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
423 
424 	/*
425 	 * Clear all of the statistics registers (clear on read).  It is
426 	 * important that we do this after we have tried to establish link
427 	 * because the symbol error count will increment wildly if there
428 	 * is no link.
429 	 */
430 	e1000_clear_hw_cntrs_82541(hw);
431 
432 out:
433 	return ret_val;
434 }
435 
436 /**
437  * e1000_get_link_up_info_82541 - Report speed and duplex
438  * @hw: pointer to the HW structure
439  * @speed: pointer to speed buffer
440  * @duplex: pointer to duplex buffer
441  *
442  * Retrieve the current speed and duplex configuration.
443  **/
e1000_get_link_up_info_82541(struct e1000_hw * hw,u16 * speed,u16 * duplex)444 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
445 					u16 *duplex)
446 {
447 	struct e1000_phy_info *phy = &hw->phy;
448 	s32 ret_val;
449 	u16 data;
450 
451 	DEBUGFUNC("e1000_get_link_up_info_82541");
452 
453 	ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
454 	if (ret_val)
455 		goto out;
456 
457 	if (!phy->speed_downgraded)
458 		goto out;
459 
460 	/*
461 	 * IGP01 PHY may advertise full duplex operation after speed
462 	 * downgrade even if it is operating at half duplex.
463 	 * Here we set the duplex settings to match the duplex in the
464 	 * link partner's capabilities.
465 	 */
466 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
467 	if (ret_val)
468 		goto out;
469 
470 	if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
471 		*duplex = HALF_DUPLEX;
472 	} else {
473 		ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
474 		if (ret_val)
475 			goto out;
476 
477 		if (*speed == SPEED_100) {
478 			if (!(data & NWAY_LPAR_100TX_FD_CAPS))
479 				*duplex = HALF_DUPLEX;
480 		} else if (*speed == SPEED_10) {
481 			if (!(data & NWAY_LPAR_10T_FD_CAPS))
482 				*duplex = HALF_DUPLEX;
483 		}
484 	}
485 
486 out:
487 	return ret_val;
488 }
489 
490 /**
491  *  e1000_phy_hw_reset_82541 - PHY hardware reset
492  *  @hw: pointer to the HW structure
493  *
494  *  Verify the reset block is not blocking us from resetting.  Acquire
495  *  semaphore (if necessary) and read/set/write the device control reset
496  *  bit in the PHY.  Wait the appropriate delay time for the device to
497  *  reset and release the semaphore (if necessary).
498  **/
e1000_phy_hw_reset_82541(struct e1000_hw * hw)499 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
500 {
501 	s32 ret_val;
502 	u32 ledctl;
503 
504 	DEBUGFUNC("e1000_phy_hw_reset_82541");
505 
506 	ret_val = e1000_phy_hw_reset_generic(hw);
507 	if (ret_val)
508 		goto out;
509 
510 	e1000_phy_init_script_82541(hw);
511 
512 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
513 		/* Configure activity LED after PHY reset */
514 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
515 		ledctl &= IGP_ACTIVITY_LED_MASK;
516 		ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
517 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
518 	}
519 
520 out:
521 	return ret_val;
522 }
523 
524 /**
525  *  e1000_setup_copper_link_82541 - Configure copper link settings
526  *  @hw: pointer to the HW structure
527  *
528  *  Calls the appropriate function to configure the link for auto-neg or forced
529  *  speed and duplex.  Then we check for link, once link is established calls
530  *  to configure collision distance and flow control are called.  If link is
531  *  not established, we return -E1000_ERR_PHY (-2).
532  **/
e1000_setup_copper_link_82541(struct e1000_hw * hw)533 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
534 {
535 	struct e1000_phy_info *phy = &hw->phy;
536 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
537 	s32  ret_val;
538 	u32 ctrl, ledctl;
539 
540 	DEBUGFUNC("e1000_setup_copper_link_82541");
541 
542 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
543 	ctrl |= E1000_CTRL_SLU;
544 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
545 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
546 
547 
548 	/* Earlier revs of the IGP phy require us to force MDI. */
549 	if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
550 		dev_spec->dsp_config = e1000_dsp_config_disabled;
551 		phy->mdix = 1;
552 	} else {
553 		dev_spec->dsp_config = e1000_dsp_config_enabled;
554 	}
555 
556 	ret_val = e1000_copper_link_setup_igp(hw);
557 	if (ret_val)
558 		goto out;
559 
560 	if (hw->mac.autoneg) {
561 		if (dev_spec->ffe_config == e1000_ffe_config_active)
562 			dev_spec->ffe_config = e1000_ffe_config_enabled;
563 	}
564 
565 	/* Configure activity LED after Phy reset */
566 	ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
567 	ledctl &= IGP_ACTIVITY_LED_MASK;
568 	ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
569 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
570 
571 	ret_val = e1000_setup_copper_link_generic(hw);
572 
573 out:
574 	return ret_val;
575 }
576 
577 /**
578  *  e1000_check_for_link_82541 - Check/Store link connection
579  *  @hw: pointer to the HW structure
580  *
581  *  This checks the link condition of the adapter and stores the
582  *  results in the hw->mac structure.
583  **/
e1000_check_for_link_82541(struct e1000_hw * hw)584 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
585 {
586 	struct e1000_mac_info *mac = &hw->mac;
587 	s32 ret_val;
588 	bool link;
589 
590 	DEBUGFUNC("e1000_check_for_link_82541");
591 
592 	/*
593 	 * We only want to go out to the PHY registers to see if Auto-Neg
594 	 * has completed and/or if our link status has changed.  The
595 	 * get_link_status flag is set upon receiving a Link Status
596 	 * Change or Rx Sequence Error interrupt.
597 	 */
598 	if (!mac->get_link_status) {
599 		ret_val = E1000_SUCCESS;
600 		goto out;
601 	}
602 
603 	/*
604 	 * First we want to see if the MII Status Register reports
605 	 * link.  If so, then we want to get the current speed/duplex
606 	 * of the PHY.
607 	 */
608 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
609 	if (ret_val)
610 		goto out;
611 
612 	if (!link) {
613 		ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
614 		goto out; /* No link detected */
615 	}
616 
617 	mac->get_link_status = FALSE;
618 
619 	/*
620 	 * Check if there was DownShift, must be checked
621 	 * immediately after link-up
622 	 */
623 	e1000_check_downshift_generic(hw);
624 
625 	/*
626 	 * If we are forcing speed/duplex, then we simply return since
627 	 * we have already determined whether we have link or not.
628 	 */
629 	if (!mac->autoneg) {
630 		ret_val = -E1000_ERR_CONFIG;
631 		goto out;
632 	}
633 
634 	ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
635 
636 	/*
637 	 * Auto-Neg is enabled.  Auto Speed Detection takes care
638 	 * of MAC speed/duplex configuration.  So we only need to
639 	 * configure Collision Distance in the MAC.
640 	 */
641 	mac->ops.config_collision_dist(hw);
642 
643 	/*
644 	 * Configure Flow Control now that Auto-Neg has completed.
645 	 * First, we need to restore the desired flow control
646 	 * settings because we may have had to re-autoneg with a
647 	 * different link partner.
648 	 */
649 	ret_val = e1000_config_fc_after_link_up_generic(hw);
650 	if (ret_val)
651 		DEBUGOUT("Error configuring flow control\n");
652 
653 out:
654 	return ret_val;
655 }
656 
657 /**
658  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
659  *  @hw: pointer to the HW structure
660  *  @link_up: boolean flag for link up status
661  *
662  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
663  *  at any other case.
664  *
665  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
666  *  gigabit link is achieved to improve link quality.
667  **/
e1000_config_dsp_after_link_change_82541(struct e1000_hw * hw,bool link_up)668 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
669 						    bool link_up)
670 {
671 	struct e1000_phy_info *phy = &hw->phy;
672 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
673 	s32 ret_val;
674 	u32 idle_errs = 0;
675 	u16 phy_data, phy_saved_data, speed, duplex, i;
676 	u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
677 	u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
678 						IGP01E1000_PHY_AGC_PARAM_A,
679 						IGP01E1000_PHY_AGC_PARAM_B,
680 						IGP01E1000_PHY_AGC_PARAM_C,
681 						IGP01E1000_PHY_AGC_PARAM_D};
682 
683 	DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
684 
685 	if (link_up) {
686 		ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
687 		if (ret_val) {
688 			DEBUGOUT("Error getting link speed and duplex\n");
689 			goto out;
690 		}
691 
692 		if (speed != SPEED_1000) {
693 			ret_val = E1000_SUCCESS;
694 			goto out;
695 		}
696 
697 		ret_val = phy->ops.get_cable_length(hw);
698 		if (ret_val)
699 			goto out;
700 
701 		if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
702 		    phy->min_cable_length >= 50) {
703 
704 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
705 				ret_val = phy->ops.read_reg(hw,
706 							    dsp_reg_array[i],
707 							    &phy_data);
708 				if (ret_val)
709 					goto out;
710 
711 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
712 
713 				ret_val = phy->ops.write_reg(hw,
714 							     dsp_reg_array[i],
715 							     phy_data);
716 				if (ret_val)
717 					goto out;
718 			}
719 			dev_spec->dsp_config = e1000_dsp_config_activated;
720 		}
721 
722 		if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
723 		    (phy->min_cable_length >= 50)) {
724 			ret_val = E1000_SUCCESS;
725 			goto out;
726 		}
727 
728 		/* clear previous idle error counts */
729 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
730 		if (ret_val)
731 			goto out;
732 
733 		for (i = 0; i < ffe_idle_err_timeout; i++) {
734 			usec_delay(1000);
735 			ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
736 						    &phy_data);
737 			if (ret_val)
738 				goto out;
739 
740 			idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
741 			if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
742 				dev_spec->ffe_config = e1000_ffe_config_active;
743 
744 				ret_val = phy->ops.write_reg(hw,
745 						  IGP01E1000_PHY_DSP_FFE,
746 						  IGP01E1000_PHY_DSP_FFE_CM_CP);
747 				if (ret_val)
748 					goto out;
749 				break;
750 			}
751 
752 			if (idle_errs)
753 				ffe_idle_err_timeout =
754 						 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
755 		}
756 	} else {
757 		if (dev_spec->dsp_config == e1000_dsp_config_activated) {
758 			/*
759 			 * Save off the current value of register 0x2F5B
760 			 * to be restored at the end of the routines.
761 			 */
762 			ret_val = phy->ops.read_reg(hw, 0x2F5B,
763 						    &phy_saved_data);
764 			if (ret_val)
765 				goto out;
766 
767 			/* Disable the PHY transmitter */
768 			ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
769 			if (ret_val)
770 				goto out;
771 
772 			msec_delay_irq(20);
773 
774 			ret_val = phy->ops.write_reg(hw, 0x0000,
775 						     IGP01E1000_IEEE_FORCE_GIG);
776 			if (ret_val)
777 				goto out;
778 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
779 				ret_val = phy->ops.read_reg(hw,
780 							    dsp_reg_array[i],
781 							    &phy_data);
782 				if (ret_val)
783 					goto out;
784 
785 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
786 				phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
787 
788 				ret_val = phy->ops.write_reg(hw,
789 							     dsp_reg_array[i],
790 							     phy_data);
791 				if (ret_val)
792 					goto out;
793 			}
794 
795 			ret_val = phy->ops.write_reg(hw, 0x0000,
796 					       IGP01E1000_IEEE_RESTART_AUTONEG);
797 			if (ret_val)
798 				goto out;
799 
800 			msec_delay_irq(20);
801 
802 			/* Now enable the transmitter */
803 			ret_val = phy->ops.write_reg(hw, 0x2F5B,
804 						     phy_saved_data);
805 			if (ret_val)
806 				goto out;
807 
808 			dev_spec->dsp_config = e1000_dsp_config_enabled;
809 		}
810 
811 		if (dev_spec->ffe_config != e1000_ffe_config_active) {
812 			ret_val = E1000_SUCCESS;
813 			goto out;
814 		}
815 
816 		/*
817 		 * Save off the current value of register 0x2F5B
818 		 * to be restored at the end of the routines.
819 		 */
820 		ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
821 		if (ret_val)
822 			goto out;
823 
824 		/* Disable the PHY transmitter */
825 		ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
826 		if (ret_val)
827 			goto out;
828 
829 		msec_delay_irq(20);
830 
831 		ret_val = phy->ops.write_reg(hw, 0x0000,
832 					     IGP01E1000_IEEE_FORCE_GIG);
833 		if (ret_val)
834 			goto out;
835 
836 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
837 					     IGP01E1000_PHY_DSP_FFE_DEFAULT);
838 		if (ret_val)
839 			goto out;
840 
841 		ret_val = phy->ops.write_reg(hw, 0x0000,
842 					     IGP01E1000_IEEE_RESTART_AUTONEG);
843 		if (ret_val)
844 			goto out;
845 
846 		msec_delay_irq(20);
847 
848 		/* Now enable the transmitter */
849 		ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
850 
851 		if (ret_val)
852 			goto out;
853 
854 		dev_spec->ffe_config = e1000_ffe_config_enabled;
855 	}
856 
857 out:
858 	return ret_val;
859 }
860 
861 /**
862  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
863  *  @hw: pointer to the HW structure
864  *
865  *  The automatic gain control (agc) normalizes the amplitude of the
866  *  received signal, adjusting for the attenuation produced by the
867  *  cable.  By reading the AGC registers, which represent the
868  *  combination of coarse and fine gain value, the value can be put
869  *  into a lookup table to obtain the approximate cable length
870  *  for each channel.
871  **/
e1000_get_cable_length_igp_82541(struct e1000_hw * hw)872 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
873 {
874 	struct e1000_phy_info *phy = &hw->phy;
875 	s32 ret_val = E1000_SUCCESS;
876 	u16 i, data;
877 	u16 cur_agc_value, agc_value = 0;
878 	u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
879 	u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,
880 							 IGP01E1000_PHY_AGC_B,
881 							 IGP01E1000_PHY_AGC_C,
882 							 IGP01E1000_PHY_AGC_D};
883 
884 	DEBUGFUNC("e1000_get_cable_length_igp_82541");
885 
886 	/* Read the AGC registers for all channels */
887 	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
888 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
889 		if (ret_val)
890 			goto out;
891 
892 		cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
893 
894 		/* Bounds checking */
895 		if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
896 		    (cur_agc_value == 0)) {
897 			ret_val = -E1000_ERR_PHY;
898 			goto out;
899 		}
900 
901 		agc_value += cur_agc_value;
902 
903 		if (min_agc_value > cur_agc_value)
904 			min_agc_value = cur_agc_value;
905 	}
906 
907 	/* Remove the minimal AGC result for length < 50m */
908 	if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
909 		agc_value -= min_agc_value;
910 		/* Average the three remaining channels for the length. */
911 		agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
912 	} else {
913 		/* Average the channels for the length. */
914 		agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
915 	}
916 
917 	phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
918 				 IGP01E1000_AGC_RANGE)
919 				? (e1000_igp_cable_length_table[agc_value] -
920 				   IGP01E1000_AGC_RANGE)
921 				: 0;
922 	phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
923 				IGP01E1000_AGC_RANGE;
924 
925 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
926 
927 out:
928 	return ret_val;
929 }
930 
931 /**
932  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
933  *  @hw: pointer to the HW structure
934  *  @active: boolean used to enable/disable lplu
935  *
936  *  Success returns 0, Failure returns 1
937  *
938  *  The low power link up (lplu) state is set to the power management level D3
939  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
940  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
941  *  is used during Dx states where the power conservation is most important.
942  *  During driver activity, SmartSpeed should be enabled so performance is
943  *  maintained.
944  **/
e1000_set_d3_lplu_state_82541(struct e1000_hw * hw,bool active)945 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
946 {
947 	struct e1000_phy_info *phy = &hw->phy;
948 	s32 ret_val;
949 	u16 data;
950 
951 	DEBUGFUNC("e1000_set_d3_lplu_state_82541");
952 
953 	switch (hw->mac.type) {
954 	case e1000_82541_rev_2:
955 	case e1000_82547_rev_2:
956 		break;
957 	default:
958 		ret_val = e1000_set_d3_lplu_state_generic(hw, active);
959 		goto out;
960 		break;
961 	}
962 
963 	ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
964 	if (ret_val)
965 		goto out;
966 
967 	if (!active) {
968 		data &= ~IGP01E1000_GMII_FLEX_SPD;
969 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
970 		if (ret_val)
971 			goto out;
972 
973 		/*
974 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
975 		 * during Dx states where the power conservation is most
976 		 * important.  During driver activity we should enable
977 		 * SmartSpeed, so performance is maintained.
978 		 */
979 		if (phy->smart_speed == e1000_smart_speed_on) {
980 			ret_val = phy->ops.read_reg(hw,
981 						    IGP01E1000_PHY_PORT_CONFIG,
982 						    &data);
983 			if (ret_val)
984 				goto out;
985 
986 			data |= IGP01E1000_PSCFR_SMART_SPEED;
987 			ret_val = phy->ops.write_reg(hw,
988 						     IGP01E1000_PHY_PORT_CONFIG,
989 						     data);
990 			if (ret_val)
991 				goto out;
992 		} else if (phy->smart_speed == e1000_smart_speed_off) {
993 			ret_val = phy->ops.read_reg(hw,
994 						    IGP01E1000_PHY_PORT_CONFIG,
995 						    &data);
996 			if (ret_val)
997 				goto out;
998 
999 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1000 			ret_val = phy->ops.write_reg(hw,
1001 						     IGP01E1000_PHY_PORT_CONFIG,
1002 						     data);
1003 			if (ret_val)
1004 				goto out;
1005 		}
1006 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1007 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1008 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1009 		data |= IGP01E1000_GMII_FLEX_SPD;
1010 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1011 		if (ret_val)
1012 			goto out;
1013 
1014 		/* When LPLU is enabled, we should disable SmartSpeed */
1015 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1016 					    &data);
1017 		if (ret_val)
1018 			goto out;
1019 
1020 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1021 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1022 					     data);
1023 	}
1024 
1025 out:
1026 	return ret_val;
1027 }
1028 
1029 /**
1030  *  e1000_setup_led_82541 - Configures SW controllable LED
1031  *  @hw: pointer to the HW structure
1032  *
1033  *  This prepares the SW controllable LED for use and saves the current state
1034  *  of the LED so it can be later restored.
1035  **/
e1000_setup_led_82541(struct e1000_hw * hw)1036 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1037 {
1038 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1039 	s32 ret_val;
1040 
1041 	DEBUGFUNC("e1000_setup_led_82541");
1042 
1043 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1044 				       &dev_spec->spd_default);
1045 	if (ret_val)
1046 		goto out;
1047 
1048 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1049 					(u16)(dev_spec->spd_default &
1050 					~IGP01E1000_GMII_SPD));
1051 	if (ret_val)
1052 		goto out;
1053 
1054 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1055 
1056 out:
1057 	return ret_val;
1058 }
1059 
1060 /**
1061  *  e1000_cleanup_led_82541 - Set LED config to default operation
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  Remove the current LED configuration and set the LED configuration
1065  *  to the default value, saved from the EEPROM.
1066  **/
e1000_cleanup_led_82541(struct e1000_hw * hw)1067 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1068 {
1069 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1070 	s32 ret_val;
1071 
1072 	DEBUGFUNC("e1000_cleanup_led_82541");
1073 
1074 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1075 					dev_spec->spd_default);
1076 	if (ret_val)
1077 		goto out;
1078 
1079 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1080 
1081 out:
1082 	return ret_val;
1083 }
1084 
1085 /**
1086  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1087  *  @hw: pointer to the HW structure
1088  *
1089  *  Initializes the IGP PHY.
1090  **/
e1000_phy_init_script_82541(struct e1000_hw * hw)1091 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1092 {
1093 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1094 	u32 ret_val;
1095 	u16 phy_saved_data;
1096 
1097 	DEBUGFUNC("e1000_phy_init_script_82541");
1098 
1099 	if (!dev_spec->phy_init_script) {
1100 		ret_val = E1000_SUCCESS;
1101 		goto out;
1102 	}
1103 
1104 	/* Delay after phy reset to enable NVM configuration to load */
1105 	msec_delay(20);
1106 
1107 	/*
1108 	 * Save off the current value of register 0x2F5B to be restored at
1109 	 * the end of this routine.
1110 	 */
1111 	ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1112 
1113 	/* Disabled the PHY transmitter */
1114 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1115 
1116 	msec_delay(20);
1117 
1118 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1119 
1120 	msec_delay(5);
1121 
1122 	switch (hw->mac.type) {
1123 	case e1000_82541:
1124 	case e1000_82547:
1125 		hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1126 
1127 		hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1128 
1129 		hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1130 
1131 		hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1132 
1133 		hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1134 
1135 		hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1136 
1137 		hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1138 
1139 		hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1140 
1141 		hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1142 		break;
1143 	case e1000_82541_rev_2:
1144 	case e1000_82547_rev_2:
1145 		hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1146 		break;
1147 	default:
1148 		break;
1149 	}
1150 
1151 	hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1152 
1153 	msec_delay(20);
1154 
1155 	/* Now enable the transmitter */
1156 	hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1157 
1158 	if (hw->mac.type == e1000_82547) {
1159 		u16 fused, fine, coarse;
1160 
1161 		/* Move to analog registers page */
1162 		hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1163 				     &fused);
1164 
1165 		if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1166 			hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1167 					     &fused);
1168 
1169 			fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1170 			coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1171 
1172 			if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1173 				coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1174 				fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1175 			} else if (coarse ==
1176 				   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1177 				fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1178 
1179 			fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1180 				(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1181 				(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1182 
1183 			hw->phy.ops.write_reg(hw,
1184 					      IGP01E1000_ANALOG_FUSE_CONTROL,
1185 					      fused);
1186 			hw->phy.ops.write_reg(hw,
1187 				      IGP01E1000_ANALOG_FUSE_BYPASS,
1188 				      IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1189 		}
1190 	}
1191 
1192 out:
1193 	return ret_val;
1194 }
1195 
1196 /**
1197  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1198  *  @hw: pointer to the HW structure
1199  *  @state: boolean value used to enable/disable PHY init script
1200  *
1201  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1202  *  IGP PHY.
1203  **/
e1000_init_script_state_82541(struct e1000_hw * hw,bool state)1204 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1205 {
1206 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1207 
1208 	DEBUGFUNC("e1000_init_script_state_82541");
1209 
1210 	if (hw->phy.type != e1000_phy_igp) {
1211 		DEBUGOUT("Initialization script not necessary.\n");
1212 		goto out;
1213 	}
1214 
1215 	dev_spec->phy_init_script = state;
1216 
1217 out:
1218 	return;
1219 }
1220 
1221 /**
1222  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1223  * @hw: pointer to the HW structure
1224  *
1225  * In the case of a PHY power down to save power, or to turn off link during a
1226  * driver unload, or wake on lan is not enabled, remove the link.
1227  **/
e1000_power_down_phy_copper_82541(struct e1000_hw * hw)1228 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1229 {
1230 	/* If the management interface is not enabled, then power down */
1231 	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1232 		e1000_power_down_phy_copper(hw);
1233 
1234 	return;
1235 }
1236 
1237 /**
1238  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1239  *  @hw: pointer to the HW structure
1240  *
1241  *  Clears the hardware counters by reading the counter registers.
1242  **/
e1000_clear_hw_cntrs_82541(struct e1000_hw * hw)1243 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1244 {
1245 	DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1246 
1247 	e1000_clear_hw_cntrs_base_generic(hw);
1248 
1249 	E1000_READ_REG(hw, E1000_PRC64);
1250 	E1000_READ_REG(hw, E1000_PRC127);
1251 	E1000_READ_REG(hw, E1000_PRC255);
1252 	E1000_READ_REG(hw, E1000_PRC511);
1253 	E1000_READ_REG(hw, E1000_PRC1023);
1254 	E1000_READ_REG(hw, E1000_PRC1522);
1255 	E1000_READ_REG(hw, E1000_PTC64);
1256 	E1000_READ_REG(hw, E1000_PTC127);
1257 	E1000_READ_REG(hw, E1000_PTC255);
1258 	E1000_READ_REG(hw, E1000_PTC511);
1259 	E1000_READ_REG(hw, E1000_PTC1023);
1260 	E1000_READ_REG(hw, E1000_PTC1522);
1261 
1262 	E1000_READ_REG(hw, E1000_ALGNERRC);
1263 	E1000_READ_REG(hw, E1000_RXERRC);
1264 	E1000_READ_REG(hw, E1000_TNCRS);
1265 	E1000_READ_REG(hw, E1000_CEXTERR);
1266 	E1000_READ_REG(hw, E1000_TSCTC);
1267 	E1000_READ_REG(hw, E1000_TSCTFC);
1268 
1269 	E1000_READ_REG(hw, E1000_MGTPRC);
1270 	E1000_READ_REG(hw, E1000_MGTPDC);
1271 	E1000_READ_REG(hw, E1000_MGTPTC);
1272 }
1273 
1274 /**
1275  *  e1000_read_mac_addr_82541 - Read device MAC address
1276  *  @hw: pointer to the HW structure
1277  *
1278  *  Reads the device MAC address from the EEPROM and stores the value.
1279  **/
e1000_read_mac_addr_82541(struct e1000_hw * hw)1280 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw)
1281 {
1282 	s32  ret_val = E1000_SUCCESS;
1283 	u16 offset, nvm_data, i;
1284 
1285 	DEBUGFUNC("e1000_read_mac_addr");
1286 
1287 	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1288 		offset = i >> 1;
1289 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1290 		if (ret_val) {
1291 			DEBUGOUT("NVM Read Error\n");
1292 			goto out;
1293 		}
1294 		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1295 		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1296 	}
1297 
1298 	for (i = 0; i < ETH_ADDR_LEN; i++)
1299 		hw->mac.addr[i] = hw->mac.perm_addr[i];
1300 
1301 out:
1302 	return ret_val;
1303 }
1304 
1305