xref: /illumos-gate/usr/src/test/util-tests/tests/libjedec/hex2spd/libjedec_hex2spd_lp5.c (revision 8119dad84d6416f13557b0ba8e2aaf9064cbcfd3) 
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2024 Oxide Computer Company
14  */
15 
16 /*
17  * LPDDR5/X SPD tests
18  */
19 
20 #include <libjedec.h>
21 #include "libjedec_hex2spd.h"
22 
23 const hex2spd_test_t micron_lp5 = {
24 	.ht_file = "lpddr5/MT62F4G32D8DV-023",
25 	.ht_checks = { {
26 		.hs_key = SPD_KEY_DRAM_TYPE,
27 		.hs_type = DATA_TYPE_UINT32,
28 		.hs_val = { .hs_u32 = SPD_DT_LPDDR5_SDRAM }
29 	}, {
30 		.hs_key = SPD_KEY_MOD_TYPE,
31 		.hs_type = DATA_TYPE_UINT32,
32 		.hs_val = { .hs_u32 = SPD_MOD_TYPE_SOLDER }
33 	}, {
34 		.hs_key = SPD_KEY_NBYTES_TOTAL,
35 		.hs_type = DATA_TYPE_UINT32,
36 		.hs_val = { .hs_u32 = 1024 }
37 	}, {
38 		.hs_key = SPD_KEY_REV_ENC,
39 		.hs_type = DATA_TYPE_UINT32,
40 		.hs_val = { .hs_u32 = 1 }
41 	}, {
42 		.hs_key = SPD_KEY_REV_ADD,
43 		.hs_type = DATA_TYPE_UINT32,
44 		.hs_val = { .hs_u32 = 0 }
45 	}, {
46 		.hs_key = SPD_KEY_MOD_REV_ENC,
47 		.hs_type = DATA_TYPE_UINT32,
48 		.hs_val = { .hs_u32 = 1 }
49 	}, {
50 		.hs_key = SPD_KEY_MOD_REV_ADD,
51 		.hs_type = DATA_TYPE_UINT32,
52 		.hs_val = { .hs_u32 = 0 }
53 	}, {
54 		.hs_key = SPD_KEY_MOD_HYBRID_TYPE,
55 		.hs_type = DATA_TYPE_UINT32,
56 		.hs_val = { .hs_u32 = SPD_MOD_NOT_HYBRID }
57 	}, {
58 		.hs_key = SPD_KEY_NROW_BITS,
59 		.hs_type = DATA_TYPE_UINT32,
60 		.hs_val = { .hs_u32 = 17 }
61 	}, {
62 		.hs_key = SPD_KEY_NCOL_BITS,
63 		.hs_type = DATA_TYPE_UINT32,
64 		.hs_val = { .hs_u32 = 6 }
65 	}, {
66 		.hs_key = SPD_KEY_NBGRP_BITS,
67 		.hs_type = DATA_TYPE_UINT32,
68 		.hs_val = { .hs_u32 = 2 }
69 	}, {
70 		.hs_key = SPD_KEY_NBANK_BITS,
71 		.hs_type = DATA_TYPE_UINT32,
72 		.hs_val = { .hs_u32 = 2 }
73 	}, {
74 		.hs_key = SPD_KEY_DIE_SIZE,
75 		.hs_type = DATA_TYPE_UINT64,
76 		.hs_val = { .hs_u64 = 16ULL * 1024ULL * 1024ULL * 1024ULL }
77 	}, {
78 		.hs_key = SPD_KEY_PKG_NDIE,
79 		.hs_type = DATA_TYPE_UINT32,
80 		.hs_val = { .hs_u32 = 8 }
81 	}, {
82 		.hs_key = SPD_KEY_RANK_ASYM,
83 		.hs_type = DATA_TYPE_BOOLEAN,
84 		.hs_val = { .hs_bool = false }
85 	}, {
86 		.hs_key = SPD_KEY_NRANKS,
87 		.hs_type = DATA_TYPE_UINT32,
88 		.hs_val = { .hs_u32 = 2 }
89 	}, {
90 		.hs_key = SPD_KEY_DRAM_WIDTH,
91 		.hs_type = DATA_TYPE_UINT32,
92 		.hs_val = { .hs_u32 = 8 }
93 	}, {
94 		/*
95 		 * While the datasheet describes itself as having 4 channels, in
96 		 * the SPD data this is only thought of as sub-channels.
97 		 */
98 		.hs_key = SPD_KEY_DRAM_NCHAN,
99 		.hs_type = DATA_TYPE_UINT32,
100 		.hs_val = { .hs_u32 = 1 }
101 	}, {
102 		.hs_key = SPD_KEY_NSUBCHAN,
103 		.hs_type = DATA_TYPE_UINT32,
104 		.hs_val = { .hs_u32 = 4 }
105 	}, {
106 		.hs_key = SPD_KEY_DATA_WIDTH,
107 		.hs_type = DATA_TYPE_UINT32,
108 		.hs_val = { .hs_u32 = 16 }
109 	}, {
110 		.hs_key = SPD_KEY_ECC_WIDTH,
111 		.hs_type = DATA_TYPE_UINT32,
112 		.hs_val = { .hs_u32 = 0 }
113 	}, {
114 		.hs_key = SPD_KEY_TCKAVG_MIN,
115 		.hs_type = DATA_TYPE_UINT64,
116 		.hs_val = { .hs_u64 = 938 }
117 	}, {
118 		.hs_key = SPD_KEY_TCKAVG_MAX,
119 		.hs_type = DATA_TYPE_UINT64,
120 		.hs_val = { .hs_u64 = 0x7c83 }
121 	}, {
122 		.hs_key = SPD_KEY_TAA_MIN,
123 		.hs_type = DATA_TYPE_UINT64,
124 		.hs_val = { .hs_u64 = 21270 }
125 	}, {
126 		.hs_key = SPD_KEY_TRCD_MIN,
127 		.hs_type = DATA_TYPE_UINT64,
128 		.hs_val = { .hs_u64 = 18000 }
129 	}, {
130 		.hs_key = SPD_KEY_TRPAB_MIN,
131 		.hs_type = DATA_TYPE_UINT64,
132 		.hs_val = { .hs_u64 = 21000 }
133 	}, {
134 		.hs_key = SPD_KEY_TRPPB_MIN,
135 		.hs_type = DATA_TYPE_UINT64,
136 		.hs_val = { .hs_u64 = 18000 }
137 	}, {
138 		.hs_key = SPD_KEY_TRFCAB_MIN,
139 		.hs_type = DATA_TYPE_UINT64,
140 		.hs_val = { .hs_u64 = 280000 }
141 	}, {
142 		.hs_key = SPD_KEY_TRFCPB_MIN,
143 		.hs_type = DATA_TYPE_UINT64,
144 		.hs_val = { .hs_u64 = 140000 }
145 	}, {
146 		.hs_key = SPD_KEY_MOD_OPER_TEMP,
147 		.hs_type = DATA_TYPE_UINT32,
148 		.hs_val = { .hs_u32 = JEDEC_TEMP_CASE_IT }
149 	}, {
150 		.hs_key = NULL,
151 	} }
152 };
153 
154 const hex2spd_test_t fake_lp5_camm2 = {
155 	.ht_file = "lpddr5/CAMM2",
156 	.ht_checks = { {
157 		.hs_key = SPD_KEY_DRAM_TYPE,
158 		.hs_type = DATA_TYPE_UINT32,
159 		.hs_val = { .hs_u32 = SPD_DT_LPDDR5X_SDRAM }
160 	}, {
161 		.hs_key = SPD_KEY_MOD_TYPE,
162 		.hs_type = DATA_TYPE_UINT32,
163 		.hs_val = { .hs_u32 = SPD_MOD_TYPE_CAMM2 }
164 	}, {
165 		.hs_key = SPD_KEY_NBYTES_TOTAL,
166 		.hs_type = DATA_TYPE_UINT32,
167 		.hs_val = { .hs_u32 = 1024 }
168 	}, {
169 		.hs_key = SPD_KEY_REV_ENC,
170 		.hs_type = DATA_TYPE_UINT32,
171 		.hs_val = { .hs_u32 = 1 }
172 	}, {
173 		.hs_key = SPD_KEY_REV_ADD,
174 		.hs_type = DATA_TYPE_UINT32,
175 		.hs_val = { .hs_u32 = 0 }
176 	}, {
177 		.hs_key = SPD_KEY_MOD_REV_ENC,
178 		.hs_type = DATA_TYPE_UINT32,
179 		.hs_val = { .hs_u32 = 1 }
180 	}, {
181 		.hs_key = SPD_KEY_MOD_REV_ADD,
182 		.hs_type = DATA_TYPE_UINT32,
183 		.hs_val = { .hs_u32 = 0 }
184 	}, {
185 		.hs_key = SPD_KEY_MOD_HYBRID_TYPE,
186 		.hs_type = DATA_TYPE_UINT32,
187 		.hs_val = { .hs_u32 = SPD_MOD_NOT_HYBRID }
188 	}, {
189 		.hs_key = SPD_KEY_NROW_BITS,
190 		.hs_type = DATA_TYPE_UINT32,
191 		.hs_val = { .hs_u32 = 16 }
192 	}, {
193 		.hs_key = SPD_KEY_NCOL_BITS,
194 		.hs_type = DATA_TYPE_UINT32,
195 		.hs_val = { .hs_u32 = 6 }
196 	}, {
197 		.hs_key = SPD_KEY_NBGRP_BITS,
198 		.hs_type = DATA_TYPE_UINT32,
199 		.hs_val = { .hs_u32 = 0 }
200 	}, {
201 		.hs_key = SPD_KEY_NBANK_BITS,
202 		.hs_type = DATA_TYPE_UINT32,
203 		.hs_val = { .hs_u32 = 3 }
204 	}, {
205 		.hs_key = SPD_KEY_DIE_SIZE,
206 		.hs_type = DATA_TYPE_UINT64,
207 		.hs_val = { .hs_u64 = 16ULL * 1024ULL * 1024ULL * 1024ULL }
208 	}, {
209 		.hs_key = SPD_KEY_PKG_NDIE,
210 		.hs_type = DATA_TYPE_UINT32,
211 		.hs_val = { .hs_u32 = 2 }
212 	}, {
213 		.hs_key = SPD_KEY_PPR,
214 		.hs_type = DATA_TYPE_UINT32,
215 		.hs_val = { .hs_u32 = SPD_PPR_F_HARD_PPR | SPD_PPR_F_SOFT_PPR }
216 	}, {
217 		.hs_key = SPD_KEY_RANK_ASYM,
218 		.hs_type = DATA_TYPE_BOOLEAN,
219 		.hs_val = { .hs_bool = false }
220 	}, {
221 		.hs_key = SPD_KEY_NRANKS,
222 		.hs_type = DATA_TYPE_UINT32,
223 		.hs_val = { .hs_u32 = 1 }
224 	}, {
225 		.hs_key = SPD_KEY_DRAM_WIDTH,
226 		.hs_type = DATA_TYPE_UINT32,
227 		.hs_val = { .hs_u32 = 16 }
228 	}, {
229 		/*
230 		 * LPDDR5 SPD doesn't provide a way to usefully break this into
231 		 * channels. Even though CAMM2 is defined as 2 64-bit channels,
232 		 * it doesn't say so in the SPD.
233 		 */
234 		.hs_key = SPD_KEY_DRAM_NCHAN,
235 		.hs_type = DATA_TYPE_UINT32,
236 		.hs_val = { .hs_u32 = 1 }
237 	}, {
238 		.hs_key = SPD_KEY_NSUBCHAN,
239 		.hs_type = DATA_TYPE_UINT32,
240 		.hs_val = { .hs_u32 = 8 }
241 	}, {
242 		.hs_key = SPD_KEY_DATA_WIDTH,
243 		.hs_type = DATA_TYPE_UINT32,
244 		.hs_val = { .hs_u32 = 16 }
245 	}, {
246 		.hs_key = SPD_KEY_ECC_WIDTH,
247 		.hs_type = DATA_TYPE_UINT32,
248 		.hs_val = { .hs_u32 = 0 }
249 	}, {
250 		.hs_key = SPD_KEY_TCKAVG_MIN,
251 		.hs_type = DATA_TYPE_UINT64,
252 		.hs_val = { .hs_u64 = 777 }
253 	}, {
254 		.hs_key = SPD_KEY_TCKAVG_MAX,
255 		.hs_type = DATA_TYPE_UINT64,
256 		.hs_val = { .hs_u64 = 0x7c83 }
257 	}, {
258 		.hs_key = SPD_KEY_TAA_MIN,
259 		.hs_type = DATA_TYPE_UINT64,
260 		.hs_val = { .hs_u64 = 23230 }
261 	}, {
262 		.hs_key = SPD_KEY_TRCD_MIN,
263 		.hs_type = DATA_TYPE_UINT64,
264 		.hs_val = { .hs_u64 = 19000 }
265 	}, {
266 		.hs_key = SPD_KEY_TRPAB_MIN,
267 		.hs_type = DATA_TYPE_UINT64,
268 		.hs_val = { .hs_u64 = 21000 }
269 	}, {
270 		.hs_key = SPD_KEY_TRPPB_MIN,
271 		.hs_type = DATA_TYPE_UINT64,
272 		.hs_val = { .hs_u64 = 18000 }
273 	}, {
274 		.hs_key = SPD_KEY_TRFCAB_MIN,
275 		.hs_type = DATA_TYPE_UINT64,
276 		.hs_val = { .hs_u64 = 380000 }
277 	}, {
278 		.hs_key = SPD_KEY_TRFCPB_MIN,
279 		.hs_type = DATA_TYPE_UINT64,
280 		.hs_val = { .hs_u64 = 90000 }
281 	}, {
282 		.hs_key = SPD_KEY_DEVS,
283 		.hs_type = DATA_TYPE_UINT32,
284 		.hs_val = { .hs_u32 = SPD_DEVICE_TEMP_1 | SPD_DEVICE_PMIC_0 |
285 		    SPD_DEVICE_SPD | SPD_DEVICE_CD_0 | SPD_DEVICE_CD_1 }
286 	}, {
287 		.hs_key = SPD_KEY_DEV_SPD_MFG_NAME,
288 		.hs_type = DATA_TYPE_STRING,
289 		.hs_val = { .hs_str = "AMD" }
290 	}, {
291 		.hs_key = SPD_KEY_DEV_SPD_TYPE,
292 		.hs_type = DATA_TYPE_UINT32,
293 		.hs_val = { .hs_u32 = SPD_SPD_T_SPD5118 },
294 	}, {
295 		.hs_key = SPD_KEY_DEV_SPD_REV,
296 		.hs_type = DATA_TYPE_STRING,
297 		.hs_val = { .hs_str = "A.0" }
298 	}, {
299 		.hs_key = SPD_KEY_DEV_PMIC0_MFG_NAME,
300 		.hs_type = DATA_TYPE_STRING,
301 		.hs_val = { .hs_str = "Hitachi" }
302 	}, {
303 		.hs_key = SPD_KEY_DEV_PMIC0_TYPE,
304 		.hs_type = DATA_TYPE_UINT32,
305 		.hs_val = { .hs_u32 = SPD_PMIC_T_PMIC5200 },
306 	}, {
307 		.hs_key = SPD_KEY_DEV_PMIC0_REV,
308 		.hs_type = DATA_TYPE_STRING,
309 		.hs_val = { .hs_str = "B.0" }
310 	}, {
311 		.hs_key = SPD_KEY_DEV_TEMP_MFG_NAME,
312 		.hs_type = DATA_TYPE_STRING,
313 		.hs_val = { .hs_str = "Fairchild" }
314 	}, {
315 		.hs_key = SPD_KEY_DEV_TEMP_TYPE,
316 		.hs_type = DATA_TYPE_UINT32,
317 		.hs_val = { .hs_u32 = SPD_TEMP_T_TS5210 },
318 	}, {
319 		.hs_key = SPD_KEY_DEV_TEMP_REV,
320 		.hs_type = DATA_TYPE_STRING,
321 		.hs_val = { .hs_str = "C.0" }
322 	}, {
323 		.hs_key = SPD_KEY_DEV_CD0_MFG_NAME,
324 		.hs_type = DATA_TYPE_STRING,
325 		.hs_val = { .hs_str = "Fujitsu" }
326 	}, {
327 		.hs_key = SPD_KEY_DEV_CD0_TYPE,
328 		.hs_type = DATA_TYPE_UINT32,
329 		.hs_val = { .hs_u32 = SPD_CD_T_DDR5CK01 },
330 	}, {
331 		.hs_key = SPD_KEY_DEV_CD0_REV,
332 		.hs_type = DATA_TYPE_STRING,
333 		.hs_val = { .hs_str = "D.0" }
334 	}, {
335 		.hs_key = SPD_KEY_DEV_CD1_MFG_NAME,
336 		.hs_type = DATA_TYPE_STRING,
337 		.hs_val = { .hs_str = "Intel" }
338 	}, {
339 		.hs_key = SPD_KEY_DEV_CD1_TYPE,
340 		.hs_type = DATA_TYPE_UINT32,
341 		.hs_val = { .hs_u32 = SPD_CD_T_DDR5CK01 },
342 	}, {
343 		.hs_key = SPD_KEY_DEV_CD1_REV,
344 		.hs_type = DATA_TYPE_STRING,
345 		.hs_val = { .hs_str = "E.0" }
346 	}, {
347 		.hs_key = SPD_KEY_MOD_HEIGHT,
348 		.hs_type = DATA_TYPE_UINT32,
349 		.hs_val = { .hs_u32 = 34 }
350 	}, {
351 		.hs_key = SPD_KEY_MOD_FRONT_THICK,
352 		.hs_type = DATA_TYPE_UINT32,
353 		.hs_val = { .hs_u32 = 5 }
354 	}, {
355 		.hs_key = SPD_KEY_MOD_BACK_THICK,
356 		.hs_type = DATA_TYPE_UINT32,
357 		.hs_val = { .hs_u32 = 2 }
358 	}, {
359 		.hs_key = SPD_KEY_MOD_REF_DESIGN,
360 		.hs_type = DATA_TYPE_STRING,
361 		.hs_val = { .hs_str = "G" }
362 	}, {
363 		.hs_key = SPD_KEY_MOD_DESIGN_REV,
364 		.hs_type = DATA_TYPE_UINT32,
365 		.hs_val = { .hs_u32 = 3 }
366 	}, {
367 		.hs_key = SPD_KEY_MOD_OPER_TEMP,
368 		.hs_type = DATA_TYPE_UINT32,
369 		.hs_val = { .hs_u32 = JEDEC_TEMP_CASE_NT }
370 	}, {
371 		.hs_key = SPD_KEY_MOD_NROWS,
372 		.hs_type = DATA_TYPE_UINT32,
373 		.hs_val = { .hs_u32 = 1 }
374 	}, {
375 		.hs_key = NULL,
376 	} }
377 };
378