1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Oxide Computer Company 14 */ 15 16 /* 17 * This works at performing remap tests across both the DFv3 and DFv4 variants. 18 */ 19 20 #include "zen_umc_test.h" 21 22 static const zen_umc_t zen_umc_remap_v3 = { 23 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 24 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 25 .umc_df_rev = DF_REV_3, 26 .umc_decomp = { 27 .dfd_sock_mask = 0x01, 28 .dfd_die_mask = 0x00, 29 .dfd_node_mask = 0x20, 30 .dfd_comp_mask = 0x1f, 31 .dfd_sock_shift = 0, 32 .dfd_die_shift = 0, 33 .dfd_node_shift = 5, 34 .dfd_comp_shift = 0 35 }, 36 .umc_ndfs = 1, 37 .umc_dfs = { { 38 .zud_dfno = 0, 39 .zud_dram_nrules = 1, 40 .zud_nchan = 4, 41 .zud_cs_nremap = 2, 42 .zud_hole_base = 0, 43 .zud_rules = { { 44 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 45 DF_DRAM_F_REMAP_SOCK, 46 .ddr_base = 0, 47 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 48 .ddr_dest_fabid = 0, 49 .ddr_sock_ileave_bits = 0, 50 .ddr_die_ileave_bits = 0, 51 .ddr_addr_start = 12, 52 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 53 } }, 54 .zud_remap = { { 55 .csr_nremaps = ZEN_UMC_MILAN_REMAP_ENTS, 56 .csr_remaps = { 0x3, 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, 0x7, 57 0x8, 0x9, 0xa, 0xb }, 58 }, { 59 .csr_nremaps = ZEN_UMC_MILAN_REMAP_ENTS, 60 .csr_remaps = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 61 0x8, 0x9, 0xa, 0xb }, 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 0, 66 .chan_instid = 0, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_type = UMC_DIMM_T_DDR4, 70 .chan_rules = { { 71 .ddr_flags = DF_DRAM_F_VALID | 72 DF_DRAM_F_REMAP_EN | 73 DF_DRAM_F_REMAP_SOCK, 74 .ddr_base = 0, 75 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 76 1024ULL, 77 .ddr_dest_fabid = 0, 78 .ddr_sock_ileave_bits = 0, 79 .ddr_die_ileave_bits = 0, 80 .ddr_addr_start = 12, 81 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 82 } }, 83 .chan_dimms = { { 84 .ud_flags = UMC_DIMM_F_VALID, 85 .ud_width = UMC_DIMM_W_X4, 86 .ud_kind = UMC_DIMM_K_RDIMM, 87 .ud_dimmno = 0, 88 .ud_cs = { { 89 .ucs_base = { 90 .udb_base = 0, 91 .udb_valid = B_TRUE 92 }, 93 .ucs_base_mask = 0x3ffffffff, 94 .ucs_nbanks = 0x4, 95 .ucs_ncol = 0xa, 96 .ucs_nrow_lo = 0x11, 97 .ucs_nbank_groups = 0x2, 98 .ucs_row_hi_bit = 0x18, 99 .ucs_row_low_bit = 0x11, 100 .ucs_bank_bits = { 0xf, 0x10, 0xd, 101 0xe }, 102 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 103 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 104 } } 105 } }, 106 }, { 107 .chan_flags = UMC_CHAN_F_ECC_EN, 108 .chan_fabid = 1, 109 .chan_instid = 1, 110 .chan_logid = 1, 111 .chan_nrules = 1, 112 .chan_type = UMC_DIMM_T_DDR4, 113 .chan_rules = { { 114 .ddr_flags = DF_DRAM_F_VALID | 115 DF_DRAM_F_REMAP_EN | 116 DF_DRAM_F_REMAP_SOCK, 117 .ddr_base = 0, 118 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 119 1024ULL, 120 .ddr_dest_fabid = 0, 121 .ddr_sock_ileave_bits = 0, 122 .ddr_die_ileave_bits = 0, 123 .ddr_addr_start = 12, 124 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 125 } }, 126 .chan_dimms = { { 127 .ud_flags = UMC_DIMM_F_VALID, 128 .ud_width = UMC_DIMM_W_X4, 129 .ud_kind = UMC_DIMM_K_RDIMM, 130 .ud_dimmno = 0, 131 .ud_cs = { { 132 .ucs_base = { 133 .udb_base = 0, 134 .udb_valid = B_TRUE 135 }, 136 .ucs_base_mask = 0x3ffffffff, 137 .ucs_nbanks = 0x4, 138 .ucs_ncol = 0xa, 139 .ucs_nrow_lo = 0x11, 140 .ucs_nbank_groups = 0x2, 141 .ucs_row_hi_bit = 0x18, 142 .ucs_row_low_bit = 0x11, 143 .ucs_bank_bits = { 0xf, 0x10, 0xd, 144 0xe }, 145 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 146 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 147 } } 148 } }, 149 }, { 150 .chan_flags = UMC_CHAN_F_ECC_EN, 151 .chan_fabid = 2, 152 .chan_instid = 2, 153 .chan_logid = 2, 154 .chan_nrules = 1, 155 .chan_type = UMC_DIMM_T_DDR4, 156 .chan_rules = { { 157 .ddr_flags = DF_DRAM_F_VALID | 158 DF_DRAM_F_REMAP_EN | 159 DF_DRAM_F_REMAP_SOCK, 160 .ddr_base = 0, 161 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 162 1024ULL, 163 .ddr_dest_fabid = 0, 164 .ddr_sock_ileave_bits = 0, 165 .ddr_die_ileave_bits = 0, 166 .ddr_addr_start = 12, 167 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 168 } }, 169 .chan_dimms = { { 170 .ud_flags = UMC_DIMM_F_VALID, 171 .ud_width = UMC_DIMM_W_X4, 172 .ud_kind = UMC_DIMM_K_RDIMM, 173 .ud_dimmno = 0, 174 .ud_cs = { { 175 .ucs_base = { 176 .udb_base = 0, 177 .udb_valid = B_TRUE 178 }, 179 .ucs_base_mask = 0x3ffffffff, 180 .ucs_nbanks = 0x4, 181 .ucs_ncol = 0xa, 182 .ucs_nrow_lo = 0x11, 183 .ucs_nbank_groups = 0x2, 184 .ucs_row_hi_bit = 0x18, 185 .ucs_row_low_bit = 0x11, 186 .ucs_bank_bits = { 0xf, 0x10, 0xd, 187 0xe }, 188 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 189 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 190 } } 191 } }, 192 }, { 193 .chan_flags = UMC_CHAN_F_ECC_EN, 194 .chan_fabid = 3, 195 .chan_instid = 3, 196 .chan_logid = 3, 197 .chan_nrules = 1, 198 .chan_type = UMC_DIMM_T_DDR4, 199 .chan_rules = { { 200 .ddr_flags = DF_DRAM_F_VALID | 201 DF_DRAM_F_REMAP_EN | 202 DF_DRAM_F_REMAP_SOCK, 203 .ddr_base = 0, 204 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 205 1024ULL, 206 .ddr_dest_fabid = 0, 207 .ddr_sock_ileave_bits = 0, 208 .ddr_die_ileave_bits = 0, 209 .ddr_addr_start = 12, 210 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 211 } }, 212 .chan_dimms = { { 213 .ud_flags = UMC_DIMM_F_VALID, 214 .ud_width = UMC_DIMM_W_X4, 215 .ud_kind = UMC_DIMM_K_RDIMM, 216 .ud_dimmno = 0, 217 .ud_cs = { { 218 .ucs_base = { 219 .udb_base = 0, 220 .udb_valid = B_TRUE 221 }, 222 .ucs_base_mask = 0x3ffffffff, 223 .ucs_nbanks = 0x4, 224 .ucs_ncol = 0xa, 225 .ucs_nrow_lo = 0x11, 226 .ucs_nbank_groups = 0x2, 227 .ucs_row_hi_bit = 0x18, 228 .ucs_row_low_bit = 0x11, 229 .ucs_bank_bits = { 0xf, 0x10, 0xd, 230 0xe }, 231 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 232 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 233 } } 234 } }, 235 } } 236 } } 237 }; 238 239 /* 240 * This sets up a DFv4 capable remap engine. The important difference we want to 241 * test here is that the remap rules can be selected on a per-DRAM rule basis. 242 * This leads us to split our rules in half and end up with two totally 243 * different remapping schemes. In comparison, DFv3 is target socket based. 244 */ 245 static const zen_umc_t zen_umc_remap_v4 = { 246 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 247 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 248 .umc_df_rev = DF_REV_4, 249 .umc_decomp = { 250 .dfd_sock_mask = 0x01, 251 .dfd_die_mask = 0x00, 252 .dfd_node_mask = 0x20, 253 .dfd_comp_mask = 0x1f, 254 .dfd_sock_shift = 0, 255 .dfd_die_shift = 0, 256 .dfd_node_shift = 5, 257 .dfd_comp_shift = 0 258 }, 259 .umc_ndfs = 1, 260 .umc_dfs = { { 261 .zud_dfno = 0, 262 .zud_dram_nrules = 2, 263 .zud_nchan = 4, 264 .zud_cs_nremap = 2, 265 .zud_hole_base = 0, 266 .zud_rules = { { 267 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 268 .ddr_base = 0, 269 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 1024ULL, 270 .ddr_dest_fabid = 0, 271 .ddr_sock_ileave_bits = 0, 272 .ddr_die_ileave_bits = 0, 273 .ddr_addr_start = 12, 274 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 275 .ddr_remap_ent = 0 276 }, { 277 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 278 .ddr_base = 32ULL * 1024ULL * 1024ULL * 1024ULL, 279 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 280 .ddr_dest_fabid = 0, 281 .ddr_sock_ileave_bits = 0, 282 .ddr_die_ileave_bits = 0, 283 .ddr_addr_start = 12, 284 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 285 .ddr_remap_ent = 1 286 } }, 287 .zud_remap = { { 288 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 289 .csr_remaps = { 0x3, 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, 0x7, 290 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }, 291 }, { 292 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 293 .csr_remaps = { 0x2, 0x1, 0x3, 0x0, 0x4, 0x5, 0x6, 0x7, 294 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }, 295 } }, 296 .zud_chan = { { 297 .chan_flags = UMC_CHAN_F_ECC_EN, 298 .chan_fabid = 0, 299 .chan_instid = 0, 300 .chan_logid = 0, 301 .chan_nrules = 2, 302 .chan_type = UMC_DIMM_T_DDR4, 303 .chan_rules = { { 304 .ddr_flags = DF_DRAM_F_VALID | 305 DF_DRAM_F_REMAP_EN, 306 .ddr_base = 0, 307 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 308 1024ULL, 309 .ddr_dest_fabid = 0, 310 .ddr_sock_ileave_bits = 0, 311 .ddr_die_ileave_bits = 0, 312 .ddr_addr_start = 12, 313 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 314 .ddr_remap_ent = 0 315 }, { 316 .ddr_flags = DF_DRAM_F_VALID | 317 DF_DRAM_F_REMAP_EN, 318 .ddr_base = 32ULL * 1024ULL * 1024ULL * 319 1024ULL, 320 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 321 1024ULL, 322 .ddr_dest_fabid = 0, 323 .ddr_sock_ileave_bits = 0, 324 .ddr_die_ileave_bits = 0, 325 .ddr_addr_start = 12, 326 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 327 .ddr_remap_ent = 1 328 } }, 329 .chan_offsets = { { 330 .cho_valid = B_TRUE, 331 .cho_offset = 0x200000000, 332 } }, 333 .chan_dimms = { { 334 .ud_flags = UMC_DIMM_F_VALID, 335 .ud_width = UMC_DIMM_W_X4, 336 .ud_kind = UMC_DIMM_K_RDIMM, 337 .ud_dimmno = 0, 338 .ud_cs = { { 339 .ucs_base = { 340 .udb_base = 0, 341 .udb_valid = B_TRUE 342 }, 343 .ucs_base_mask = 0x3ffffffff, 344 .ucs_nbanks = 0x4, 345 .ucs_ncol = 0xa, 346 .ucs_nrow_lo = 0x11, 347 .ucs_nbank_groups = 0x2, 348 .ucs_row_hi_bit = 0x18, 349 .ucs_row_low_bit = 0x11, 350 .ucs_bank_bits = { 0xf, 0x10, 0xd, 351 0xe }, 352 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 353 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 354 } } 355 } }, 356 }, { 357 .chan_flags = UMC_CHAN_F_ECC_EN, 358 .chan_fabid = 1, 359 .chan_instid = 1, 360 .chan_logid = 1, 361 .chan_nrules = 2, 362 .chan_type = UMC_DIMM_T_DDR4, 363 .chan_rules = { { 364 .ddr_flags = DF_DRAM_F_VALID | 365 DF_DRAM_F_REMAP_EN, 366 .ddr_base = 0, 367 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 368 1024ULL, 369 .ddr_dest_fabid = 0, 370 .ddr_sock_ileave_bits = 0, 371 .ddr_die_ileave_bits = 0, 372 .ddr_addr_start = 12, 373 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 374 .ddr_remap_ent = 0 375 }, { 376 .ddr_flags = DF_DRAM_F_VALID | 377 DF_DRAM_F_REMAP_EN, 378 .ddr_base = 32ULL * 1024ULL * 1024ULL * 379 1024ULL, 380 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 381 1024ULL, 382 .ddr_dest_fabid = 0, 383 .ddr_sock_ileave_bits = 0, 384 .ddr_die_ileave_bits = 0, 385 .ddr_addr_start = 12, 386 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 387 .ddr_remap_ent = 1 388 } }, 389 .chan_offsets = { { 390 .cho_valid = B_TRUE, 391 .cho_offset = 0x200000000, 392 } }, 393 .chan_dimms = { { 394 .ud_flags = UMC_DIMM_F_VALID, 395 .ud_width = UMC_DIMM_W_X4, 396 .ud_kind = UMC_DIMM_K_RDIMM, 397 .ud_dimmno = 0, 398 .ud_cs = { { 399 .ucs_base = { 400 .udb_base = 0, 401 .udb_valid = B_TRUE 402 }, 403 .ucs_base_mask = 0x3ffffffff, 404 .ucs_nbanks = 0x4, 405 .ucs_ncol = 0xa, 406 .ucs_nrow_lo = 0x11, 407 .ucs_nbank_groups = 0x2, 408 .ucs_row_hi_bit = 0x18, 409 .ucs_row_low_bit = 0x11, 410 .ucs_bank_bits = { 0xf, 0x10, 0xd, 411 0xe }, 412 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 413 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 414 } } 415 } }, 416 }, { 417 .chan_flags = UMC_CHAN_F_ECC_EN, 418 .chan_fabid = 2, 419 .chan_instid = 2, 420 .chan_logid = 2, 421 .chan_nrules = 2, 422 .chan_type = UMC_DIMM_T_DDR4, 423 .chan_rules = { { 424 .ddr_flags = DF_DRAM_F_VALID | 425 DF_DRAM_F_REMAP_EN, 426 .ddr_base = 0, 427 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 428 1024ULL, 429 .ddr_dest_fabid = 0, 430 .ddr_sock_ileave_bits = 0, 431 .ddr_die_ileave_bits = 0, 432 .ddr_addr_start = 12, 433 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 434 .ddr_remap_ent = 0 435 }, { 436 .ddr_flags = DF_DRAM_F_VALID | 437 DF_DRAM_F_REMAP_EN, 438 .ddr_base = 32ULL * 1024ULL * 1024ULL * 439 1024ULL, 440 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 441 1024ULL, 442 .ddr_dest_fabid = 0, 443 .ddr_sock_ileave_bits = 0, 444 .ddr_die_ileave_bits = 0, 445 .ddr_addr_start = 12, 446 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 447 .ddr_remap_ent = 1 448 } }, 449 .chan_offsets = { { 450 .cho_valid = B_TRUE, 451 .cho_offset = 0x200000000, 452 } }, 453 .chan_dimms = { { 454 .ud_flags = UMC_DIMM_F_VALID, 455 .ud_width = UMC_DIMM_W_X4, 456 .ud_kind = UMC_DIMM_K_RDIMM, 457 .ud_dimmno = 0, 458 .ud_cs = { { 459 .ucs_base = { 460 .udb_base = 0, 461 .udb_valid = B_TRUE 462 }, 463 .ucs_base_mask = 0x3ffffffff, 464 .ucs_nbanks = 0x4, 465 .ucs_ncol = 0xa, 466 .ucs_nrow_lo = 0x11, 467 .ucs_nbank_groups = 0x2, 468 .ucs_row_hi_bit = 0x18, 469 .ucs_row_low_bit = 0x11, 470 .ucs_bank_bits = { 0xf, 0x10, 0xd, 471 0xe }, 472 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 473 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 474 } } 475 } }, 476 }, { 477 .chan_flags = UMC_CHAN_F_ECC_EN, 478 .chan_fabid = 3, 479 .chan_instid = 3, 480 .chan_logid = 3, 481 .chan_nrules = 2, 482 .chan_type = UMC_DIMM_T_DDR4, 483 .chan_rules = { { 484 .ddr_flags = DF_DRAM_F_VALID | 485 DF_DRAM_F_REMAP_EN, 486 .ddr_base = 0, 487 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 488 1024ULL, 489 .ddr_dest_fabid = 0, 490 .ddr_sock_ileave_bits = 0, 491 .ddr_die_ileave_bits = 0, 492 .ddr_addr_start = 12, 493 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 494 .ddr_remap_ent = 0 495 }, { 496 .ddr_flags = DF_DRAM_F_VALID | 497 DF_DRAM_F_REMAP_EN, 498 .ddr_base = 32ULL * 1024ULL * 1024ULL * 499 1024ULL, 500 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 501 1024ULL, 502 .ddr_dest_fabid = 0, 503 .ddr_sock_ileave_bits = 0, 504 .ddr_die_ileave_bits = 0, 505 .ddr_addr_start = 12, 506 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 507 .ddr_remap_ent = 1 508 } }, 509 .chan_offsets = { { 510 .cho_valid = B_TRUE, 511 .cho_offset = 0x200000000, 512 } }, 513 .chan_dimms = { { 514 .ud_flags = UMC_DIMM_F_VALID, 515 .ud_width = UMC_DIMM_W_X4, 516 .ud_kind = UMC_DIMM_K_RDIMM, 517 .ud_dimmno = 0, 518 .ud_cs = { { 519 .ucs_base = { 520 .udb_base = 0, 521 .udb_valid = B_TRUE 522 }, 523 .ucs_base_mask = 0x3ffffffff, 524 .ucs_nbanks = 0x4, 525 .ucs_ncol = 0xa, 526 .ucs_nrow_lo = 0x11, 527 .ucs_nbank_groups = 0x2, 528 .ucs_row_hi_bit = 0x18, 529 .ucs_row_low_bit = 0x11, 530 .ucs_bank_bits = { 0xf, 0x10, 0xd, 531 0xe }, 532 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 533 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 534 } } 535 } }, 536 } } 537 } } 538 }; 539 540 const umc_decode_test_t zen_umc_test_remap[] = { { 541 .udt_desc = "Milan Remap (0)", 542 .udt_umc = &zen_umc_remap_v3, 543 .udt_pa = 0x138, 544 .udt_pass = B_TRUE, 545 .udt_norm_addr = 0x138, 546 .udt_sock = 0, 547 .udt_die = 0, 548 .udt_comp = 3, 549 .udt_dimm_no = 0, 550 .udt_dimm_col = 0x27, 551 .udt_dimm_row = 0, 552 .udt_dimm_bank = 0, 553 .udt_dimm_bank_group = 0, 554 .udt_dimm_subchan = UINT8_MAX, 555 .udt_dimm_rm = 0, 556 .udt_dimm_cs = 0 557 }, { 558 .udt_desc = "Milan Remap (1)", 559 .udt_umc = &zen_umc_remap_v3, 560 .udt_pa = 0x1138, 561 .udt_pass = B_TRUE, 562 .udt_norm_addr = 0x138, 563 .udt_sock = 0, 564 .udt_die = 0, 565 .udt_comp = 2, 566 .udt_dimm_no = 0, 567 .udt_dimm_col = 0x27, 568 .udt_dimm_row = 0, 569 .udt_dimm_bank = 0, 570 .udt_dimm_bank_group = 0, 571 .udt_dimm_subchan = UINT8_MAX, 572 .udt_dimm_rm = 0, 573 .udt_dimm_cs = 0 574 }, { 575 .udt_desc = "Milan Remap (2)", 576 .udt_umc = &zen_umc_remap_v3, 577 .udt_pa = 0x2138, 578 .udt_pass = B_TRUE, 579 .udt_norm_addr = 0x138, 580 .udt_sock = 0, 581 .udt_die = 0, 582 .udt_comp = 1, 583 .udt_dimm_no = 0, 584 .udt_dimm_col = 0x27, 585 .udt_dimm_row = 0, 586 .udt_dimm_bank = 0, 587 .udt_dimm_bank_group = 0, 588 .udt_dimm_subchan = UINT8_MAX, 589 .udt_dimm_rm = 0, 590 .udt_dimm_cs = 0 591 }, { 592 .udt_desc = "Milan Remap (3)", 593 .udt_umc = &zen_umc_remap_v3, 594 .udt_pa = 0x3138, 595 .udt_pass = B_TRUE, 596 .udt_norm_addr = 0x138, 597 .udt_sock = 0, 598 .udt_die = 0, 599 .udt_comp = 0, 600 .udt_dimm_no = 0, 601 .udt_dimm_col = 0x27, 602 .udt_dimm_row = 0, 603 .udt_dimm_bank = 0, 604 .udt_dimm_bank_group = 0, 605 .udt_dimm_subchan = UINT8_MAX, 606 .udt_dimm_rm = 0, 607 .udt_dimm_cs = 0 608 }, { 609 .udt_desc = "DFv4 Remap (0)", 610 .udt_umc = &zen_umc_remap_v4, 611 .udt_pa = 0x163, 612 .udt_pass = B_TRUE, 613 .udt_norm_addr = 0x163, 614 .udt_sock = 0, 615 .udt_die = 0, 616 .udt_comp = 3, 617 .udt_dimm_no = 0, 618 .udt_dimm_col = 0x2c, 619 .udt_dimm_row = 0, 620 .udt_dimm_bank = 0, 621 .udt_dimm_bank_group = 0, 622 .udt_dimm_subchan = UINT8_MAX, 623 .udt_dimm_rm = 0, 624 .udt_dimm_cs = 0 625 }, { 626 .udt_desc = "DFv4 Remap (1)", 627 .udt_umc = &zen_umc_remap_v4, 628 .udt_pa = 0x1163, 629 .udt_pass = B_TRUE, 630 .udt_norm_addr = 0x163, 631 .udt_sock = 0, 632 .udt_die = 0, 633 .udt_comp = 2, 634 .udt_dimm_no = 0, 635 .udt_dimm_col = 0x2c, 636 .udt_dimm_row = 0, 637 .udt_dimm_bank = 0, 638 .udt_dimm_bank_group = 0, 639 .udt_dimm_subchan = UINT8_MAX, 640 .udt_dimm_rm = 0, 641 .udt_dimm_cs = 0 642 }, { 643 .udt_desc = "DFv4 Remap (2)", 644 .udt_umc = &zen_umc_remap_v4, 645 .udt_pa = 0x2163, 646 .udt_pass = B_TRUE, 647 .udt_norm_addr = 0x163, 648 .udt_sock = 0, 649 .udt_die = 0, 650 .udt_comp = 1, 651 .udt_dimm_no = 0, 652 .udt_dimm_col = 0x2c, 653 .udt_dimm_row = 0, 654 .udt_dimm_bank = 0, 655 .udt_dimm_bank_group = 0, 656 .udt_dimm_subchan = UINT8_MAX, 657 .udt_dimm_rm = 0, 658 .udt_dimm_cs = 0 659 }, { 660 .udt_desc = "DFv4 Remap (3)", 661 .udt_umc = &zen_umc_remap_v4, 662 .udt_pa = 0x3163, 663 .udt_pass = B_TRUE, 664 .udt_norm_addr = 0x163, 665 .udt_sock = 0, 666 .udt_die = 0, 667 .udt_comp = 0, 668 .udt_dimm_no = 0, 669 .udt_dimm_col = 0x2c, 670 .udt_dimm_row = 0, 671 .udt_dimm_bank = 0, 672 .udt_dimm_bank_group = 0, 673 .udt_dimm_subchan = UINT8_MAX, 674 .udt_dimm_rm = 0, 675 .udt_dimm_cs = 0 676 }, { 677 .udt_desc = "DFv4 Remap (4)", 678 .udt_umc = &zen_umc_remap_v4, 679 .udt_pa = 0x900000163, 680 .udt_pass = B_TRUE, 681 .udt_norm_addr = 0x240000163, 682 .udt_sock = 0, 683 .udt_die = 0, 684 .udt_comp = 2, 685 .udt_dimm_no = 0, 686 .udt_dimm_col = 0x2c, 687 .udt_dimm_row = 0x12000, 688 .udt_dimm_bank = 0, 689 .udt_dimm_bank_group = 0, 690 .udt_dimm_subchan = UINT8_MAX, 691 .udt_dimm_rm = 0, 692 .udt_dimm_cs = 0 693 }, { 694 .udt_desc = "DFv4 Remap (5)", 695 .udt_umc = &zen_umc_remap_v4, 696 .udt_pa = 0x900001163, 697 .udt_pass = B_TRUE, 698 .udt_norm_addr = 0x240000163, 699 .udt_sock = 0, 700 .udt_die = 0, 701 .udt_comp = 1, 702 .udt_dimm_no = 0, 703 .udt_dimm_col = 0x2c, 704 .udt_dimm_row = 0x12000, 705 .udt_dimm_bank = 0, 706 .udt_dimm_bank_group = 0, 707 .udt_dimm_subchan = UINT8_MAX, 708 .udt_dimm_rm = 0, 709 .udt_dimm_cs = 0 710 }, { 711 .udt_desc = "DFv4 Remap (6)", 712 .udt_umc = &zen_umc_remap_v4, 713 .udt_pa = 0x900002163, 714 .udt_pass = B_TRUE, 715 .udt_norm_addr = 0x240000163, 716 .udt_sock = 0, 717 .udt_die = 0, 718 .udt_comp = 3, 719 .udt_dimm_no = 0, 720 .udt_dimm_col = 0x2c, 721 .udt_dimm_row = 0x12000, 722 .udt_dimm_bank = 0, 723 .udt_dimm_bank_group = 0, 724 .udt_dimm_subchan = UINT8_MAX, 725 .udt_dimm_rm = 0, 726 .udt_dimm_cs = 0 727 }, { 728 .udt_desc = "DFv4 Remap (7)", 729 .udt_umc = &zen_umc_remap_v4, 730 .udt_pa = 0x900003163, 731 .udt_pass = B_TRUE, 732 .udt_norm_addr = 0x240000163, 733 .udt_sock = 0, 734 .udt_die = 0, 735 .udt_comp = 0, 736 .udt_dimm_no = 0, 737 .udt_dimm_col = 0x2c, 738 .udt_dimm_row = 0x12000, 739 .udt_dimm_bank = 0, 740 .udt_dimm_bank_group = 0, 741 .udt_dimm_subchan = UINT8_MAX, 742 .udt_dimm_rm = 0, 743 .udt_dimm_cs = 0 744 }, { 745 .udt_desc = NULL 746 } }; 747