1*c1733db1SRobert Mustacchi.\" 2*c1733db1SRobert Mustacchi.\" This file and its contents are supplied under the terms of the 3*c1733db1SRobert Mustacchi.\" Common Development and Distribution License ("CDDL"), version 1.0. 4*c1733db1SRobert Mustacchi.\" You may only use this file in accordance with the terms of version 5*c1733db1SRobert Mustacchi.\" 1.0 of the CDDL. 6*c1733db1SRobert Mustacchi.\" 7*c1733db1SRobert Mustacchi.\" A full copy of the text of the CDDL should have accompanied this 8*c1733db1SRobert Mustacchi.\" source. A copy of the CDDL is also available via the Internet at 9*c1733db1SRobert Mustacchi.\" http://www.illumos.org/license/CDDL. 10*c1733db1SRobert Mustacchi.\" 11*c1733db1SRobert Mustacchi.\" 12*c1733db1SRobert Mustacchi.\" Copyright 2025 Oxide Computer Company 13*c1733db1SRobert Mustacchi.\" 14*c1733db1SRobert Mustacchi.Dd October 4, 2025 15*c1733db1SRobert Mustacchi.Dt PCHSMBUS 4D 16*c1733db1SRobert Mustacchi.Os 17*c1733db1SRobert Mustacchi.Sh NAME 18*c1733db1SRobert Mustacchi.Nm pchsmbus 19*c1733db1SRobert Mustacchi.Nd Intel PCH SMBus Controller 20*c1733db1SRobert Mustacchi.Sh DESCRIPTION 21*c1733db1SRobert MustacchiThe 22*c1733db1SRobert Mustacchi.Nm 23*c1733db1SRobert Mustacchidriver is an SMBus 2.0 controller that supports many generations of 24*c1733db1SRobert MustacchiIntel chipsets. 25*c1733db1SRobert MustacchiSupported device families include the original Intel Controller Hub 26*c1733db1SRobert Mustacchifamily 27*c1733db1SRobert Mustacchi.Pq ICH , 28*c1733db1SRobert Mustacchithe Intel Platfrom Controller Hub family 29*c1733db1SRobert Mustacchi.Pq PCH , 30*c1733db1SRobert Mustacchivarious on-package chipsets, and a variety of Atom and other processors. 31*c1733db1SRobert Mustacchi.Pp 32*c1733db1SRobert MustacchiThe 33*c1733db1SRobert Mustacchi.Nm 34*c1733db1SRobert Mustacchidriver is part of the system's I2C framework and is accessible 35*c1733db1SRobert Mustacchithrough common tools such as 36*c1733db1SRobert Mustacchi.Xr i2cadm 8 . 37*c1733db1SRobert MustacchiThe controller supports all SMBus 2.0 operations and has a 32-byte block 38*c1733db1SRobert Mustacchibuffer. 39*c1733db1SRobert MustacchiIn addition, it has compatibility options to generate I2C-based block 40*c1733db1SRobert Mustacchireads and writes. 41*c1733db1SRobert MustacchiThe driver does not support changing any SMBus parameter timings and the 42*c1733db1SRobert Mustacchicontroller generally only operates at 100 kHz. 43*c1733db1SRobert Mustacchi.Sh ARCHITECTURE 44*c1733db1SRobert Mustacchi.Sy x86 45*c1733db1SRobert Mustacchi.Sh FILES 46*c1733db1SRobert Mustacchi.Bl -tag -width Pa 47*c1733db1SRobert Mustacchi.It Pa /kernel/drv/amd64/pchsmbus 48*c1733db1SRobert MustacchiDevice driver (x86) 49*c1733db1SRobert Mustacchi.El 50*c1733db1SRobert Mustacchi.Sh SEE ALSO 51*c1733db1SRobert Mustacchi.Xr ismt 4D , 52*c1733db1SRobert Mustacchi.Xr i2cadm 8 53