1.\" 2.\" This file and its contents are supplied under the terms of the 3.\" Common Development and Distribution License ("CDDL"), version 1.0. 4.\" You may only use this file in accordance with the terms of version 5.\" 1.0 of the CDDL. 6.\" 7.\" A full copy of the text of the CDDL should have accompanied this 8.\" source. A copy of the CDDL is also available via the Internet at 9.\" http://www.illumos.org/license/CDDL. 10.\" 11.\" 12.\" Copyright 2025 Oxide Computer Company 13.\" 14.Dd October 4, 2025 15.Dt PCHSMBUS 4D 16.Os 17.Sh NAME 18.Nm pchsmbus 19.Nd Intel PCH SMBus Controller 20.Sh DESCRIPTION 21The 22.Nm 23driver is an SMBus 2.0 controller that supports many generations of 24Intel chipsets. 25Supported device families include the original Intel Controller Hub 26family 27.Pq ICH , 28the Intel Platfrom Controller Hub family 29.Pq PCH , 30various on-package chipsets, and a variety of Atom and other processors. 31.Pp 32The 33.Nm 34driver is part of the system's I2C framework and is accessible 35through common tools such as 36.Xr i2cadm 8 . 37The controller supports all SMBus 2.0 operations and has a 32-byte block 38buffer. 39In addition, it has compatibility options to generate I2C-based block 40reads and writes. 41The driver does not support changing any SMBus parameter timings and the 42controller generally only operates at 100 kHz. 43.Sh ARCHITECTURE 44.Sy x86 45.Sh FILES 46.Bl -tag -width Pa 47.It Pa /kernel/drv/amd64/pchsmbus 48Device driver (x86) 49.El 50.Sh SEE ALSO 51.Xr ismt 4D , 52.Xr i2cadm 8 53