1*c1733db1SRobert Mustacchi.\" 2*c1733db1SRobert Mustacchi.\" This file and its contents are supplied under the terms of the 3*c1733db1SRobert Mustacchi.\" Common Development and Distribution License ("CDDL"), version 1.0. 4*c1733db1SRobert Mustacchi.\" You may only use this file in accordance with the terms of version 5*c1733db1SRobert Mustacchi.\" 1.0 of the CDDL. 6*c1733db1SRobert Mustacchi.\" 7*c1733db1SRobert Mustacchi.\" A full copy of the text of the CDDL should have accompanied this 8*c1733db1SRobert Mustacchi.\" source. A copy of the CDDL is also available via the Internet at 9*c1733db1SRobert Mustacchi.\" http://www.illumos.org/license/CDDL. 10*c1733db1SRobert Mustacchi.\" 11*c1733db1SRobert Mustacchi.\" 12*c1733db1SRobert Mustacchi.\" Copyright 2025 Oxide Computer Company 13*c1733db1SRobert Mustacchi.\" 14*c1733db1SRobert Mustacchi.Dd October 4, 2025 15*c1733db1SRobert Mustacchi.Dt ISMT 4D 16*c1733db1SRobert Mustacchi.Os 17*c1733db1SRobert Mustacchi.Sh NAME 18*c1733db1SRobert Mustacchi.Nm ismt 19*c1733db1SRobert Mustacchi.Nd Intel SMBus Message Transport driver 20*c1733db1SRobert Mustacchi.Sh DESCRIPTION 21*c1733db1SRobert MustacchiThe 22*c1733db1SRobert Mustacchi.Nm 23*c1733db1SRobert Mustacchidriver is an SMBus 3.0 controller with I2C support that is present on 24*c1733db1SRobert Mustacchivarious Intel Atom and Xeon-D platforms. 25*c1733db1SRobert Mustacchi.Pp 26*c1733db1SRobert MustacchiThe 27*c1733db1SRobert Mustacchi.Nm 28*c1733db1SRobert Mustacchidriver is part of the system's I2C framework and is accessible 29*c1733db1SRobert Mustacchithrough common tools such as 30*c1733db1SRobert Mustacchi.Xr i2cadm 8 . 31*c1733db1SRobert MustacchiThe controller ssupports a mixture of SMBus 2.0 and 3.0 features, but is 32*c1733db1SRobert Mustacchistill limited to a 32-byte block buffer and does not support the SMBus 33*c1733db1SRobert Mustacchi32-bit and 64-bit protocols directly in its SMBus operation. 34*c1733db1SRobert MustacchiUnlike 35*c1733db1SRobert Mustacchi.Xr pchsmbus 4D , 36*c1733db1SRobert Mustacchi.Nm 37*c1733db1SRobert Mustacchialso has support for I2C based operations and can use up to a 240-byte 38*c1733db1SRobert Mustacchibuffer for them. 39*c1733db1SRobert MustacchiThe 40*c1733db1SRobert Mustacchi.Nm 41*c1733db1SRobert Mustacchidriver currently only has read-only properties. 42*c1733db1SRobert MustacchiWhile the controller supports a variable bus frequency, these are 43*c1733db1SRobert Mustacchisupposed to only be set by fuses by the platform implementor. 44*c1733db1SRobert Mustacchi.Sh ARCHITECTURE 45*c1733db1SRobert Mustacchi.Sy x86 46*c1733db1SRobert Mustacchi.Sh FILES 47*c1733db1SRobert Mustacchi.Bl -tag -width Pa 48*c1733db1SRobert Mustacchi.It Pa /kernel/drv/amd64/ismt 49*c1733db1SRobert MustacchiDevice driver (x86) 50*c1733db1SRobert Mustacchi.El 51*c1733db1SRobert Mustacchi.Sh SEE ALSO 52*c1733db1SRobert Mustacchi.Xr pchsmbus 4D , 53*c1733db1SRobert Mustacchi.Xr i2cadm 8 54