1.\" 2.\" This file and its contents are supplied under the terms of the 3.\" Common Development and Distribution License ("CDDL"), version 1.0. 4.\" You may only use this file in accordance with the terms of version 5.\" 1.0 of the CDDL. 6.\" 7.\" A full copy of the text of the CDDL should have accompanied this 8.\" source. A copy of the CDDL is also available via the Internet at 9.\" http://www.illumos.org/license/CDDL. 10.\" 11.\" 12.\" Copyright 2025 Oxide Computer Company 13.\" 14.Dd October 4, 2025 15.Dt ISMT 4D 16.Os 17.Sh NAME 18.Nm ismt 19.Nd Intel SMBus Message Transport driver 20.Sh DESCRIPTION 21The 22.Nm 23driver is an SMBus 3.0 controller with I2C support that is present on 24various Intel Atom and Xeon-D platforms. 25.Pp 26The 27.Nm 28driver is part of the system's I2C framework and is accessible 29through common tools such as 30.Xr i2cadm 8 . 31The controller ssupports a mixture of SMBus 2.0 and 3.0 features, but is 32still limited to a 32-byte block buffer and does not support the SMBus 3332-bit and 64-bit protocols directly in its SMBus operation. 34Unlike 35.Xr pchsmbus 4D , 36.Nm 37also has support for I2C based operations and can use up to a 240-byte 38buffer for them. 39The 40.Nm 41driver currently only has read-only properties. 42While the controller supports a variable bus frequency, these are 43supposed to only be set by fuses by the platform implementor. 44.Sh ARCHITECTURE 45.Sy x86 46.Sh FILES 47.Bl -tag -width Pa 48.It Pa /kernel/drv/amd64/ismt 49Device driver (x86) 50.El 51.Sh SEE ALSO 52.Xr pchsmbus 4D , 53.Xr i2cadm 8 54