1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2026 Oxide Computer Company 14 */ 15 16 #ifndef _TOPO_PCIE_H 17 #define _TOPO_PCIE_H 18 19 #include <fm/topo_hc.h> 20 21 /* 22 * Common PCIe module header file. 23 */ 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Topology properties. 31 * Where they exist, we use the same property names as are used for HC nodes 32 * for consistency across the different trees. 33 */ 34 35 /* io group */ 36 #define TOPO_PCIE_PGROUP_IO TOPO_PGROUP_IO 37 #define TOPO_PCIE_IO_DEV_PATH TOPO_IO_DEV_PATH 38 #define TOPO_PCIE_IO_DRIVER TOPO_IO_DRIVER 39 #define TOPO_PCIE_IO_INSTANCE TOPO_IO_INSTANCE 40 #define TOPO_PCIE_IO_DEVTYPE TOPO_IO_DEVTYPE 41 42 /* 43 * pci-cfg 44 * Contains properties which relate to data that the OS has programmed into the 45 * PCI device, such as its B/D/F. 46 */ 47 #define TOPO_PCIE_PGROUP_PCI_CFG "pci-cfg" 48 #define TOPO_PCIE_PCI_BUS "bus" 49 #define TOPO_PCIE_PCI_DEVICE "device" 50 #define TOPO_PCIE_PCI_FUNCTION "function" 51 #define TOPO_PCIE_PCI_SEGMENT "segment" 52 #define TOPO_PCIE_PCI_BUS_RANGE "bus-range" 53 #define TOPO_PCIE_PCI_ASSIGNED_ADDR TOPO_PCI_AADDR 54 55 /* 56 * pci 57 * This is used for both PCI and PCIe devices. It contains properties which are 58 * obtained from the device itself, and some synthetic ones derived from them 59 * such as the strings obtained via lookups in the PCI database. 60 */ 61 #define TOPO_PCIE_PGROUP_PCI TOPO_PGROUP_PCI 62 #define TOPO_PCIE_PCI_TYPE "type" 63 #define TOPO_PCIE_PCI_SLOT "slot" 64 #define TOPO_PCIE_PCI_CLASS "class" 65 #define TOPO_PCIE_PCI_SUBCLASS "subclass" 66 #define TOPO_PCIE_PCI_INTERFACE "interface" 67 #define TOPO_PCIE_PCI_VENDOR_NAME TOPO_PCI_VENDNM 68 #define TOPO_PCIE_PCI_DEV_NAME TOPO_PCI_DEVNM 69 #define TOPO_PCIE_PCI_SUBSYSTEM_NAME TOPO_PCI_SUBSYSNM 70 #define TOPO_PCIE_PCI_VENDOR_ID TOPO_PCI_VENDID 71 #define TOPO_PCIE_PCI_DEV_ID TOPO_PCI_DEVID 72 #define TOPO_PCIE_PCI_SSVENDORID "subsystem-vendor-id" 73 #define TOPO_PCIE_PCI_SSID "subsystem-id" 74 #define TOPO_PCIE_PCI_REVID "revision-id" 75 #define TOPO_PCIE_PCI_CLASS_STRING "class-string" 76 77 /* port group */ 78 #define TOPO_PCIE_PGROUP_PORT "port" 79 #define TOPO_PCIE_PORT_TYPE "type" 80 #define TOPO_PCIE_PORT_TYPE_US "upstream" 81 #define TOPO_PCIE_PORT_TYPE_DS "downstream" 82 83 /* 84 * Link properties. 85 * 86 * Depending on whether a link is a PCI or PCIe link, one of these property 87 * groups will be present. Not all properties apply equally to both link types. 88 */ 89 #define TOPO_PCIE_PGROUP_PCIE_LINK "pcie-link" 90 #define TOPO_PCIE_PGROUP_PCI_LINK "pci-link" 91 92 /* Common properties */ 93 #define TOPO_PCIE_LINK_STATE "link-state" 94 #define TOPO_PCIE_LINK_SUBSTRATE "substrate" 95 96 /* pcie-specific link properties */ 97 #define TOPO_PCIE_LINK_CUR_SPEED TOPO_PCI_CUR_SPEED 98 #define TOPO_PCIE_LINK_CUR_WIDTH TOPO_PCI_CUR_WIDTH 99 #define TOPO_PCIE_LINK_MAX_SPEED TOPO_PCI_MAX_SPEED 100 #define TOPO_PCIE_LINK_MAX_WIDTH TOPO_PCI_MAX_WIDTH 101 #define TOPO_PCIE_LINK_SUP_SPEED TOPO_PCI_SUP_SPEED 102 #define TOPO_PCIE_LINK_ADMIN_SPEED TOPO_PCI_ADMIN_SPEED 103 104 /* pci-specific link properties */ 105 #define TOPO_PCIE_LINK_66MHZ_CAPABLE "66mhz-capable" 106 107 #ifdef __cplusplus 108 } 109 #endif 110 111 #endif /* _TOPO_PCIE_H */ 112