xref: /illumos-gate/usr/src/cmd/cxgbetool/cudbg_view.c (revision 7e6ad4690aa1d3cbf260ef54d5e9632ae40a782e)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright (c) 2019 by Chelsio Communications, Inc.
14  */
15 
16 #include <stdio.h>
17 #include <stddef.h>
18 #include <stdlib.h>
19 #include <string.h>
20 #include <ctype.h>
21 #include <fcntl.h>
22 #include <unistd.h>
23 #include <assert.h>
24 
25 #include "t4_regs.h"
26 #include "t4_chip_type.h"
27 #include "cudbg_view.h"
28 #include "osdep.h"
29 #include "t4fw_interface.h"
30 
31 #include "cudbg_view_entity.h"
32 #include "cudbg_entity.h"
33 #include "cudbg.h"
34 #include "cudbg_lib_common.h"
35 #include "fastlz.h"
36 
37 extern struct reg_info t6_sge_regs[];
38 extern struct reg_info t6_pcie_regs[];
39 extern struct reg_info t6_dbg_regs[];
40 extern struct reg_info t6_ma_regs[];
41 extern struct reg_info t6_cim_regs[];
42 extern struct reg_info t6_tp_regs[];
43 extern struct reg_info t6_ulp_tx_regs[];
44 extern struct reg_info t6_pm_rx_regs[];
45 extern struct reg_info t6_pm_tx_regs[];
46 extern struct reg_info t6_mps_regs[];
47 extern struct reg_info t6_cpl_switch_regs[];
48 extern struct reg_info t6_smb_regs[];
49 extern struct reg_info t6_i2cm_regs[];
50 extern struct reg_info t6_mi_regs[];
51 extern struct reg_info t6_uart_regs[];
52 extern struct reg_info t6_pmu_regs[];
53 extern struct reg_info t6_ulp_rx_regs[];
54 extern struct reg_info t6_sf_regs[];
55 extern struct reg_info t6_pl_regs[];
56 extern struct reg_info t6_le_regs[];
57 extern struct reg_info t6_ncsi_regs[];
58 extern struct reg_info t6_mac_regs[];
59 extern struct reg_info t6_mc_0_regs[];
60 extern struct reg_info t6_edc_t60_regs[];
61 extern struct reg_info t6_edc_t61_regs[];
62 extern struct reg_info t6_hma_t6_regs[];
63 
64 extern struct reg_info t5_sge_regs[];
65 extern struct reg_info t5_pcie_regs[];
66 extern struct reg_info t5_dbg_regs[];
67 extern struct reg_info t5_ma_regs[];
68 extern struct reg_info t5_cim_regs[];
69 extern struct reg_info t5_tp_regs[];
70 extern struct reg_info t5_ulp_tx_regs[];
71 extern struct reg_info t5_pm_rx_regs[];
72 extern struct reg_info t5_pm_tx_regs[];
73 extern struct reg_info t5_mps_regs[];
74 extern struct reg_info t5_cpl_switch_regs[];
75 extern struct reg_info t5_smb_regs[];
76 extern struct reg_info t5_i2cm_regs[];
77 extern struct reg_info t5_mi_regs[];
78 extern struct reg_info t5_uart_regs[];
79 extern struct reg_info t5_pmu_regs[];
80 extern struct reg_info t5_ulp_rx_regs[];
81 extern struct reg_info t5_sf_regs[];
82 extern struct reg_info t5_pl_regs[];
83 extern struct reg_info t5_le_regs[];
84 extern struct reg_info t5_ncsi_regs[];
85 extern struct reg_info t5_mac_regs[];
86 extern struct reg_info t5_mc_0_regs[];
87 extern struct reg_info t5_mc_1_regs[];
88 extern struct reg_info t5_edc_t50_regs[];
89 extern struct reg_info t5_edc_t51_regs[];
90 extern struct reg_info t5_hma_t5_regs[];
91 
92 #include "reg_defs_t5.c"
93 #include "reg_defs_t6.c"
94 
95 #include <time.h>
96 #include <stdarg.h>
97 
is_t5(enum chip_type chip)98 int is_t5(enum chip_type chip)
99 {
100 	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
101 }
102 
is_t6(enum chip_type chip)103 int is_t6(enum chip_type chip)
104 {
105 	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
106 }
107 
108 enum {                                 /* adapter flags */
109 	FULL_INIT_DONE     = (1 << 0),
110 	USING_MSI          = (1 << 1),
111 	USING_MSIX         = (1 << 2),
112 	QUEUES_BOUND       = (1 << 3),
113 	FW_OK              = (1 << 4),
114 	RSS_TNLALLLOOKUP   = (1 << 5),
115 	USING_SOFT_PARAMS  = (1 << 6),
116 	MASTER_PF          = (1 << 7),
117 	BYPASS_DROP        = (1 << 8),
118 	FW_OFLD_CONN       = (1 << 9),
119 };
120 
121 static struct ver_cs {
122 	int major;
123 	int minor;
124 	int changeset;
125 } ver_to_cs[] = {
126 	{1, 9, 12852},
127 	{1, 10, 13182},
128 	{1, 11, 13257},
129 	{1, 12, 13495},
130 	{1, 13, 13905},
131 	{1, 14, 13969},
132 };
133 
134 static bool flash_info_banner = true;
135 
136 #include "cudbg_view_compat.c"
137 
138 int
cudbg_sge_ctxt_check_valid(u32 * buf,int type)139 cudbg_sge_ctxt_check_valid(u32 *buf, int type)
140 {
141 	int index, bit, bit_pos = 0;
142 
143 	switch (type) {
144 		case CTXT_EGRESS:
145 			bit_pos = 176;
146 			break;
147 		case CTXT_INGRESS:
148 			bit_pos = 141;
149 			break;
150 		case CTXT_FLM:
151 			bit_pos = 89;
152 			break;
153 	}
154 	index = bit_pos / 32;
155 	bit =  bit_pos % 32;
156 	return buf[index] & (1U << bit);
157 }
158 
159 int
cudbg_view_decompress_buff(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * c_buff,struct cudbg_buffer * dc_buff)160 cudbg_view_decompress_buff(char *pbuf,
161 			   struct cudbg_entity_hdr *entity_hdr,
162 			   struct cudbg_buffer *c_buff,
163 			   struct cudbg_buffer *dc_buff)
164 {
165 	int rc = 0;
166 
167 	c_buff->data = pbuf + entity_hdr->start_offset;
168 	/* Remove padding bytes, if any */
169 	if (entity_hdr->num_pad)
170 		c_buff->size = entity_hdr->size - entity_hdr->num_pad;
171 	else
172 		c_buff->size = entity_hdr->size;
173 	c_buff->offset = 0;
174 	memset(dc_buff, 0, sizeof(struct cudbg_buffer));
175 
176 	rc = validate_buffer(c_buff);
177 	if (rc)
178 		return rc;
179 
180 	rc = decompress_buffer_wrapper(c_buff, dc_buff);
181 	if (rc) {
182 		free(dc_buff->data);
183 		return rc;
184 	}
185 	return rc;
186 }
187 
188 int
get_entity_rev(struct cudbg_ver_hdr * ver_hdr)189 get_entity_rev(struct cudbg_ver_hdr *ver_hdr)
190 {
191 	if (ver_hdr->signature == CUDBG_ENTITY_SIGNATURE)
192 		return ver_hdr->revision;
193 	return 0;
194 }
195 
196 /* Find Mercurial sw repo changeset number
197  * where major or minor number set to given number
198  * */
199 int
cudbg_find_changeset(int major,int minor)200 cudbg_find_changeset(int major, int minor)
201 {
202 	int i;
203 
204 	for (i = 0; i < sizeof(ver_to_cs)/sizeof(struct ver_cs); i++) {
205 		if (ver_to_cs[i].major == major &&
206 		    ver_to_cs[i].minor == minor)
207 			return ver_to_cs[i].changeset;
208 	}
209 
210 	return -1;
211 }
212 
213 /* Format a value in a unit that differs from the
214  * value's native unit by the
215  * given factor.
216  */
217 static void
unit_conv(char * buf,size_t len,unsigned int val,unsigned int factor)218 unit_conv(char *buf, size_t len, unsigned int val,
219 	  unsigned int factor)
220 {
221 	unsigned int rem = val % factor;
222 
223 	if (rem == 0)
224 		(void) snprintf(buf, len, "%u", val / factor);
225 	else {
226 		while (rem % 10 == 0)
227 			rem /= 10;
228 		(void) snprintf(buf, len, "%u.%u", val / factor, rem);
229 	}
230 }
231 
232 int
validate_next_rec_offset(void * pinbuf,u32 inbuf_size,u32 next_rec_offset)233 validate_next_rec_offset(void *pinbuf, u32 inbuf_size, u32
234 			 next_rec_offset)
235 {
236 	struct cudbg_hdr *cudbg_hdr;
237 
238 	if (inbuf_size <= next_rec_offset)
239 		return 0;
240 
241 	cudbg_hdr = (struct cudbg_hdr *)((char *)pinbuf + next_rec_offset);
242 	if ((cudbg_hdr->signature != CUDBG_SIGNATURE) &&
243 	    (cudbg_hdr->signature != CUDBG_LEGACY_SIGNATURE))
244 		return 0; /* no next rec */
245 
246 	return next_rec_offset;
247 }
248 
249 int
view_ext_entity(char * pinbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)250 view_ext_entity(char *pinbuf, struct cudbg_entity_hdr *ent_hdr,
251 		struct cudbg_buffer *cudbg_poutbuf,
252 		enum chip_type chip)
253 {
254 	struct cudbg_entity_hdr *entity_hdr = NULL;
255 	u32 size, total_size = 0;
256 	u32 next_ext_offset = 0;
257 	u32 entity_type;
258 	int rc = 0;
259 
260 	entity_hdr = (struct cudbg_entity_hdr *)
261 		     (pinbuf + ent_hdr->start_offset);
262 	/* Remove padding bytes, if any */
263 	size = ent_hdr->num_pad ? ent_hdr->size - ent_hdr->num_pad :
264 				  ent_hdr->size;
265 	while ((entity_hdr->flag & CUDBG_EXT_DATA_VALID)
266 		&& (total_size < size)) {
267 		entity_type = entity_hdr->entity_type;
268 		if (entity_hdr->sys_warn)
269 			printf("Entity warning: Type %s , %d\n",
270 			       entity_list[entity_type].name,
271 			       entity_hdr->sys_warn);
272 
273 		if (entity_hdr->hdr_flags) {
274 			printf("Entity error: Type %s, %s\n",
275 			       entity_list[entity_type].name,
276 			       err_msg[-entity_hdr->hdr_flags]);
277 			if (entity_hdr->sys_err)
278 				printf("System error  %d\n",
279 				       entity_hdr->sys_err);
280 
281 			next_ext_offset = entity_hdr->next_ext_offset;
282 			entity_hdr = (struct cudbg_entity_hdr *)
283 				     (pinbuf + ent_hdr->start_offset +
284 				      next_ext_offset);
285 			continue;
286 		}
287 		if (entity_hdr->size > 0) {
288 			total_size += entity_hdr->size +
289 					sizeof(struct cudbg_entity_hdr);
290 
291 			rc = view_entity[entity_type - 1]
292 				(pinbuf + ent_hdr->start_offset,
293 				 entity_hdr,
294 				 cudbg_poutbuf,
295 				 chip);
296 			if (rc < 0)
297 				goto out;
298 		}
299 		next_ext_offset = entity_hdr->next_ext_offset;
300 		entity_hdr = (struct cudbg_entity_hdr *)
301 			     (pinbuf + ent_hdr->start_offset + next_ext_offset);
302 	}
303 
304 	if (total_size != size)
305 		printf("Entity warning: Extended entity size mismatch\n");
306 
307 out:
308 	return rc;
309 }
310 
311 static void
cudbg_print_cudbg_header(struct cudbg_hdr * hdr)312 cudbg_print_cudbg_header(struct cudbg_hdr *hdr)
313 {
314 	printf("\n/***************Header Information***************/\n");
315 	printf("Library Version: %u.%u\n", hdr->major_ver, hdr->minor_ver);
316 	printf("Compressed with: ");
317 	printf("Chip Version: ");
318 	switch (CHELSIO_CHIP_VERSION(hdr->chip_ver)) {
319 	case CHELSIO_T4:
320 		printf("T4 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
321 		break;
322 	case CHELSIO_T5:
323 		printf("T5 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
324 		break;
325 	case CHELSIO_T6:
326 		printf("T6 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
327 		break;
328 	default:
329 		printf("%u (unknown)\n", hdr->chip_ver);
330 		break;
331 	}
332 	printf("/************************************************/\n\n");
333 }
334 
335 void
cudbg_print_flash_header(void * pinbuf)336 cudbg_print_flash_header(void *pinbuf)
337 {
338 	struct cudbg_flash_hdr *fl_hdr = (struct cudbg_flash_hdr *)pinbuf;
339 
340 	if (fl_hdr->signature == CUDBG_FL_SIGNATURE && flash_info_banner) {
341 		printf("\n/***************Flash Header information***************/\n");
342 		printf("Flash signature: %c%c%c%c\n",
343 		       (fl_hdr->signature  >> 24) & 0xFF,
344 		       (fl_hdr->signature  >> 16) & 0xFF,
345 		       (fl_hdr->signature  >> 8) & 0xFF,
346 		       fl_hdr->signature & 0xFF);
347 
348 		printf("Flash payload timestamp (GMT): %s",
349 		       asctime(gmtime((time_t *)&fl_hdr->timestamp)));
350 		printf("Flash payload size: %u bytes\n", fl_hdr->data_len);
351 		printf("/******************************************************/\n");
352 		flash_info_banner = false;
353 	}
354 }
355 
356 int
cudbg_view(void * handle,void * pinbuf,u32 inbuf_size,void * poutbuf,s64 * poutbuf_size)357 cudbg_view(void *handle, void *pinbuf, u32 inbuf_size,
358 	   void *poutbuf, s64 *poutbuf_size)
359 {
360 
361 	struct cudbg_buffer cudbg_poutbuf = {0};
362 	struct cudbg_entity_hdr *entity_hdr;
363 	u32 info, offset, max_entities, i;
364 	struct cudbg_hdr *tmp_hdr;
365 	u32 next_rec_offset = 0;
366 	int index, bit, all;
367 	int rc = 0, cs;
368 	u8 *dbg_bitmap;
369 	int count = 0;
370 
371 	dbg_bitmap = ((struct cudbg_private *)handle)->dbg_init.dbg_bitmap;
372 	info = ((struct cudbg_private *)handle)->dbg_init.info;
373 
374 	if (inbuf_size < (sizeof(struct cudbg_entity_hdr) +
375 			  sizeof(struct cudbg_hdr))) {
376 		printf("\n\tInvalid cudbg dump file\n");
377 		return CUDBG_STATUS_NO_SIGNATURE;
378 	}
379 
380 	tmp_hdr  = (struct cudbg_hdr *)pinbuf;
381 	if ((tmp_hdr->signature != CUDBG_SIGNATURE) &&
382 	    (tmp_hdr->signature != CUDBG_LEGACY_SIGNATURE)) {
383 		printf("\n\tInvalid cudbg dump file\n");
384 		return CUDBG_STATUS_NO_SIGNATURE;
385 	}
386 
387 	if ((tmp_hdr->major_ver != CUDBG_MAJOR_VERSION) ||
388 	    (tmp_hdr->minor_ver != CUDBG_MINOR_VERSION)) {
389 		printf("\n\tMeta data version mismatch\n");
390 		printf("\tMeta data version expected %d.%d\n",
391 		       CUDBG_MAJOR_VERSION, CUDBG_MINOR_VERSION);
392 		printf("\tMeta data version in dump %d.%d\n",
393 		       tmp_hdr->major_ver, tmp_hdr->minor_ver);
394 
395 		cs = cudbg_find_changeset(tmp_hdr->major_ver,
396 					  tmp_hdr->minor_ver);
397 		if (cs != -1) {
398 			printf("\n\tPlease use changeset %d in sw Mercurial "\
399 			       "repo to build cudbg_app with version %d.%d\n",
400 			       cs, tmp_hdr->major_ver, tmp_hdr->minor_ver);
401 
402 			printf("\n\tOr\n\n\tUse precompiled cudbg_app binary for RHEL 5.x from "\
403 			       "vnc52:/home/surendra/vnc52/"\
404 			       "cudbg_app/cudbg_app_<version>\"\n\n");
405 
406 
407 		}
408 		return CUDBG_METADATA_VERSION_MISMATCH;
409 	}
410 
411 	if (info)
412 		cudbg_print_cudbg_header(tmp_hdr);
413 
414 	next_rec_offset += tmp_hdr->data_len;
415 	offset = tmp_hdr->hdr_len;
416 	all = dbg_bitmap[0] & (1 << CUDBG_ALL);
417 	max_entities = min(tmp_hdr->max_entities, CUDBG_MAX_ENTITY);
418 
419 	for (i = 1; i < max_entities; i++) {
420 		index = i / 8;
421 		bit = i % 8;
422 
423 		if (all || (dbg_bitmap[index] & (1 << bit))) {
424 			entity_hdr =
425 				(struct cudbg_entity_hdr *)((char *)pinbuf + offset);
426 
427 			if (entity_hdr->sys_warn)
428 				printf("Entity warning: Type %s , %d\n",
429 				       entity_list[i].name,
430 				       entity_hdr->sys_warn);
431 
432 			if (entity_hdr->hdr_flags) {
433 				offset += sizeof(struct cudbg_entity_hdr);
434 				printf("Entity error: Type %s, %s\n",
435 				       entity_list[i].name,
436 				       err_msg[-entity_hdr->hdr_flags]);
437 				if (entity_hdr->sys_err)
438 					printf("System error  %d\n",
439 					       entity_hdr->sys_err);
440 
441 				if (poutbuf)
442 					*poutbuf_size = 0;
443 
444 				continue;
445 			}
446 			memset(&cudbg_poutbuf, 0, sizeof(cudbg_poutbuf));
447 			if (entity_hdr->size > 0) {
448 				if (poutbuf) {
449 					cudbg_poutbuf.data = poutbuf;
450 					/* poutbuf_size value should not be
451  					 * more than 32 bit value
452  					 */
453 					assert(!((*poutbuf_size) >> 32));
454 					cudbg_poutbuf.size = (u32)*poutbuf_size;
455 					cudbg_poutbuf.offset = 0;
456 				}
457 
458 				if (info)
459 					printf("%-20s compressed size %u\n",
460 					       entity_list[i].name,
461 					       entity_hdr->size);
462 				else {
463 					if (entity_hdr->entity_type !=
464 					    CUDBG_EXT_ENTITY)
465 						printf("%s() dbg entity : %s\n",
466 						       __func__,
467 						       entity_list[i].name);
468 
469 					rc = view_entity[i - 1]
470 						((char *)pinbuf,
471 						 entity_hdr,
472 						 &cudbg_poutbuf,
473 						 tmp_hdr->chip_ver);
474 
475 					count++;
476 				}
477 			} else if (!all && i !=
478 				   CUDBG_EXT_ENTITY) {
479 				printf("%s() dbg entity : %s\n",
480 				       __func__, entity_list[i].name);
481 				printf("\t%s not available\n",
482 				       entity_list[i].name);
483 			}
484 			if (rc < 0)
485 				goto out;
486 		}
487 		offset += sizeof(struct cudbg_entity_hdr);
488 	}
489 
490 	/* if max_entities in dump is less than current CUDBG_MAX_ENTITY
491 	 * it means entities after tmp_hdr->max_entities does not exist
492 	 * in that dump
493 	 */
494 	if (tmp_hdr->max_entities < CUDBG_MAX_ENTITY) {
495 		for (i = tmp_hdr->max_entities; i < CUDBG_MAX_ENTITY; i++) {
496 			index = i / 8;
497 			bit = i % 8;
498 
499 			if (all || (dbg_bitmap[index] & (1 << bit))) {
500 				printf("%s() dbg entity : %s\n",
501 				       __func__, entity_list[i].name);
502 				printf("\t%s does not Exist\n",
503 				       entity_list[i].name);
504 			}
505 		}
506 	}
507 	if (poutbuf) {
508 		if (!count)
509 			*poutbuf_size = 0;
510 		else
511 			*poutbuf_size = cudbg_poutbuf.size;
512 	}
513 
514 	return validate_next_rec_offset(pinbuf, inbuf_size, next_rec_offset);
515 
516 out:
517 	if (poutbuf)
518 		*poutbuf_size = cudbg_poutbuf.size;
519 	return rc;
520 }
521 
522 int
view_cim_q(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)523 view_cim_q(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
524 	   struct cudbg_buffer *cudbg_poutbuf,
525 	   enum chip_type chip)
526 {
527 	struct cudbg_buffer c_buff, dc_buff;
528 	u32 i, *pdata = NULL;
529 	int rc;
530 
531 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
532 	if (rc)
533 		return rc;
534 
535 	pdata = (u32 *)dc_buff.data;
536 	for (i = 0; i < dc_buff.offset / 4; i += 4)
537 		printf("%#06x: %08x %08x %08x "\
538 			     "%08x\n", i * 4,
539 			     pdata[i + 0], pdata[i + 1],
540 			     pdata[i + 2], pdata[i + 3]);
541 
542 	return rc;
543 }
544 
545 static int
view_cim_la_t6(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)546 view_cim_la_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
547 	       struct cudbg_buffer *cudbg_poutbuf)
548 {
549 	struct cudbg_buffer c_buff, dc_buff;
550 	u32 i, *p, cfg, dc_size;
551 	int rc;
552 
553 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
554 	if (rc)
555 		return rc;
556 
557 	dc_size = dc_buff.offset;
558 	p = (u32 *)((char *)dc_buff.data + sizeof(cfg));
559 	cfg = *((u32 *)dc_buff.data);
560 	dc_size -= sizeof(cfg);
561 
562 	if (cfg & F_UPDBGLACAPTPCONLY) {
563 		printf("Status   Inst    Data      "\
564 			     "PC\r\n");
565 
566 		for (i = 0; i < dc_size; i += 40, p += 10) {
567 			printf("  %02x   %08x %08x %08x\n",
568 				p[3] & 0xff, p[2], p[1], p[0]);
569 
570 			printf("  %02x   %02x%06x %02x%06x %02x%06x\n",
571 				(p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
572 				     p[5] & 0xff, p[4] >> 8, p[4] & 0xff,
573 				     p[3] >> 8);
574 
575 			printf("  %02x   %04x%04x %04x%04x %04x%04x\n",
576 				(p[9] >> 16) & 0xff, p[9] & 0xffff,
577 				p[8] >> 16, p[8] & 0xffff, p[7] >> 16,
578 				p[7] & 0xffff, p[6] >> 16);
579 		}
580 		goto err1;
581 	}
582 
583 	printf("Status   Inst    Data      PC     "\
584 		     "LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data\n");
585 
586 	for (i = 0; i < dc_size; i += 40, p += 10) {
587 		printf("  %02x   %04x%04x %04x%04x "\
588 			     "%04x%04x %08x %08x %08x %08x %08x %08x\n",
589 			     (p[9] >> 16) & 0xff,       /* Status */
590 			     p[9] & 0xffff, p[8] >> 16, /* Inst */
591 			     p[8] & 0xffff, p[7] >> 16, /* Data */
592 			     p[7] & 0xffff, p[6] >> 16, /* PC */
593 			     p[2], p[1], p[0],          /* LS0 Stat, Addr
594 							   and Data */
595 			     p[5], p[4], p[3]);         /* LS1 Stat, Addr
596 							   and Data */
597 	}
598 
599 err1:
600 	return rc;
601 }
602 
603 static int
view_cim_la_t5(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)604 view_cim_la_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
605 	       struct cudbg_buffer *cudbg_poutbuf)
606 {
607 	struct cudbg_buffer c_buff, dc_buff;
608 	u32 i, *p, cfg, dc_size;
609 	int rc;
610 
611 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
612 	if (rc)
613 		return rc;
614 
615 	dc_size = dc_buff.offset;
616 	p = (u32 *)((char *)dc_buff.data + sizeof(cfg));
617 	cfg = *((u32 *)dc_buff.data);
618 	dc_size -= sizeof(cfg);
619 
620 	if (cfg & F_UPDBGLACAPTPCONLY) {
621 		/* as per cim_la_show_3in1() (in
622 		 * sw\dev\linux\drv\cxgb4_main.c)*/
623 		printf("Status   Data      PC\r\n");
624 
625 		for (i = 0; i < dc_size; i += 32, p += 8) {
626 			printf("  %02X   %08X %08X\r\n",
627 				(p[5] & 0xFF), p[6], p[7]);
628 
629 			printf(
630 				     "  %02X   %02X%06X %02X%06X\n",
631 				     ((p[3] >> 8) & 0xFF), (p[3] & 0xFF),
632 				     (p[4] >> 8), (p[4] & 0xFF), (p[5] >> 8));
633 
634 			printf(
635 				     "  %02X   %X%07X %X%07X\r\n",
636 				     ((p[0] >> 4) & 0xFF), (p[0] & 0xF),
637 				     (p[1] >> 4), (p[1] & 0xF), (p[2] >> 4));
638 		}
639 		goto err1;
640 	}
641 
642 	printf("Status   Data      PC     LS0Stat  "\
643 		     "LS0Addr             LS0Data\n");
644 
645 	for (i = 0; i < dc_size; i += 32, p += 8) {
646 		printf("%02x   %x%07x %x%07x %08x "\
647 			     "%08x %08x%08x%08x%08x\n",
648 			     ((p[0] >> 4) & 0xFF), (p[0] & 0xF), (p[1] >> 4),
649 			     (p[1] & 0xF), (p[2] >> 4), (p[2] & 0xF), p[3],
650 			     p[4], p[5], p[6], p[7]);
651 	}
652 err1:
653 	return rc;
654 }
655 
656 int
view_cim_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)657 view_cim_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
658 	    struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
659 {
660 	int rc = -1;
661 
662 	if (is_t5(chip))
663 		rc = view_cim_la_t5(pbuf, entity_hdr, cudbg_poutbuf);
664 	else if (is_t6(chip))
665 		rc = view_cim_la_t6(pbuf, entity_hdr, cudbg_poutbuf);
666 
667 	return rc;
668 }
669 
670 int
view_cim_ma_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)671 view_cim_ma_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
672 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
673 {
674 	struct cudbg_buffer c_buff, dc_buff;
675 	int rc, i, j;
676 	u32 *p;
677 
678 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
679 	if (rc)
680 		return rc;
681 
682 	p = (u32 *)dc_buff.data;
683 	for (i = 0; i <= CIM_MALA_SIZE; i++, p += 4) {
684 		if (i < CIM_MALA_SIZE) {
685 			printf(
686 				     "%02x%08x%08x%08x%08x\n",
687 				     p[4], p[3], p[2], p[1], p[0]);
688 		} else {
689 			printf("\nCnt ID Tag UE   "\
690 				     "   Data       RDY VLD\n");
691 			for (j = 0; j < CIM_MALA_SIZE ; j++, p += 3) {
692 				printf(
693 					     "%3u %2u  %x  %u %08x%08x  %u   "\
694 					     "%u\n",
695 					     (p[2] >> 10) & 0xff,
696 					     (p[2] >> 7) & 7, (p[2] >> 3) & 0xf,
697 					     (p[2] >> 2) & 1,
698 					     (p[1] >> 2) | ((p[2] & 3) << 30),
699 					     (p[0] >> 2) | ((p[1] & 3) << 30),
700 					     (p[0] >> 1) & 1, p[0] & 1);
701 			}
702 		}
703 	}
704 
705 	return rc;
706 }
707 
708 int
view_cim_qcfg(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)709 view_cim_qcfg(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
710 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
711 {
712 	static const char * const pQname[] = {
713 		"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
714 		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI"
715 	};
716 	struct cudbg_buffer c_buff, dc_buff;
717 	struct struct_cim_qcfg *q_cfg_data;
718 	u32 *p, *wr;
719 	int rc, i;
720 
721 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
722 	if (rc)
723 		return rc;
724 
725 	q_cfg_data = (struct struct_cim_qcfg *) (dc_buff.data);
726 	p = q_cfg_data->stat;
727 	wr = q_cfg_data->obq_wr;
728 
729 	printf("  Queue Base Size Thres  RdPtr "\
730 		     "WrPtr  SOP  EOP Avail\n");
731 	for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) {
732 		printf("%5s %5x %5u %4u %6x  %4x "\
733 			     "%4u %4u %5u\n",
734 			     pQname[i],
735 			     q_cfg_data->base[i], q_cfg_data->size[i],
736 			     q_cfg_data->thres[i], G_IBQRDADDR(p[0]),
737 			     G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]),
738 			     G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16);
739 	}
740 
741 	for (; i < CIM_NUM_IBQ + CIM_NUM_OBQ; i++, p += 4, wr += 2) {
742 		printf("%5s %5x %5u %11x  %4x %4u "\
743 			     "%4u %5u\n",
744 			     pQname[i],
745 			     q_cfg_data->base[i], q_cfg_data->size[i],
746 			     G_QUERDADDR(p[0]) & 0x3fff,
747 			     wr[0] - q_cfg_data->base[i], G_QUESOPCNT(p[3]),
748 			     G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16);
749 	}
750 
751 	return rc;
752 }
753 
754 int
decompress_buffer_wrapper(struct cudbg_buffer * pc_buff,struct cudbg_buffer * pdc_buff)755 decompress_buffer_wrapper(struct cudbg_buffer *pc_buff,
756 			  struct cudbg_buffer *pdc_buff)
757 {
758 	int rc = 0;
759 	pdc_buff->data =  malloc(2 * CUDBG_CHUNK_SIZE);
760 	if (pdc_buff->data == NULL) {
761 		rc = CUDBG_STATUS_NOSPACE;
762 		goto err;
763 	}
764 	pdc_buff->size = 2 * CUDBG_CHUNK_SIZE;
765 
766 	rc = decompress_buffer(pc_buff, pdc_buff);
767 	if (rc == CUDBG_STATUS_SMALL_BUFF) {
768 		free(pdc_buff->data);
769 		pdc_buff->data =  malloc(pdc_buff->size);
770 
771 		if (pdc_buff->data == NULL) {
772 			printf("malloc failed for size %u\n", pdc_buff->size);
773 			rc = CUDBG_STATUS_NOSPACE;
774 			goto err;
775 		}
776 		rc = decompress_buffer(pc_buff, pdc_buff);
777 	}
778 err:
779 	return rc;
780 }
781 
782 int
copy_bin_data(char * pbuf,struct cudbg_entity_hdr * entity_hdr,const char * fname,struct cudbg_buffer * cudbg_poutbuf)783 copy_bin_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
784 	      const char *fname, struct cudbg_buffer *cudbg_poutbuf)
785 {
786 	struct cudbg_buffer c_buff, dc_buff;
787 	int rc = 0;
788 
789 	if (cudbg_poutbuf->data == NULL)
790 		return 0;
791 
792 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
793 	if (rc)
794 		return rc;
795 
796 	if (dc_buff.size > cudbg_poutbuf->size) {
797 		rc = CUDBG_STATUS_OUTBUFF_OVERFLOW;
798 		cudbg_poutbuf->size = dc_buff.size;
799 		goto err1;
800 	}
801 
802 	memcpy(cudbg_poutbuf->data, dc_buff.data, dc_buff.size);
803 	cudbg_poutbuf->size = dc_buff.size;
804 
805 err1:
806 	return rc;
807 }
808 
809 int
view_edc0_data(char * pbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)810 view_edc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
811 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
812 {
813 	return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc0.bin", cudbg_poutbuf);
814 }
815 
816 int
view_edc1_data(char * pbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)817 view_edc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
818 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
819 {
820 	return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc1.bin", cudbg_poutbuf);
821 }
822 
823 int
view_mc0_data(char * pbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)824 view_mc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
825 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
826 {
827 	return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc0.bin", cudbg_poutbuf);
828 }
829 
830 int
view_mc1_data(char * pbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)831 view_mc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
832 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
833 {
834 	return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc1.bin", cudbg_poutbuf);
835 }
836 
837 int
view_hma_data(char * pbuf,struct cudbg_entity_hdr * ent_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)838 view_hma_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
839 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
840 {
841 	return copy_bin_data(pbuf, ent_hdr, "_cudbg_hma.bin", cudbg_poutbuf);
842 }
843 
844 int
view_sw_state(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)845 view_sw_state(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
846 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
847 {
848 	struct cudbg_buffer c_buff, dc_buff;
849 	u8 os_type, *caller_string;
850 	struct sw_state *swstate;
851 	char *os, *fwstate;
852 	u32 fw_state;
853 	int rc = 0;
854 
855 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
856 	if (rc)
857 		return rc;
858 
859 	swstate = (struct sw_state *) dc_buff.data;
860 	fw_state = swstate->fw_state;
861 	caller_string = swstate->caller_string;
862 	os_type = swstate->os_type;
863 
864 	printf("\n");
865 	if (fw_state & F_PCIE_FW_ERR && G_PCIE_FW_EVAL(fw_state) ==
866 	    PCIE_FW_EVAL_CRASH)
867 		fwstate = "Crashed";
868 	else
869 		fwstate = "Alive";
870 
871 	switch (os_type) {
872 	case CUDBG_OS_TYPE_WINDOWS:
873 		os = "Windows";
874 		break;
875 	case CUDBG_OS_TYPE_LINUX:
876 		os = "Linux";
877 		break;
878 	case CUDBG_OS_TYPE_ESX:
879 		os = "ESX";
880 		break;
881 	case CUDBG_OS_TYPE_UNKNOWN:
882 	default:
883 		os = "Unknown";
884 	}
885 
886 	printf("\tFW STATE  : %s\n", fwstate);
887 	printf("\tOS        : %s\n", os);
888 	printf("\tCALLER    : %s\n", caller_string);
889 	printf("\n");
890 
891 	return rc;
892 }
893 
894 int
view_cpl_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)895 view_cpl_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
896 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
897 {
898 	struct struct_tp_cpl_stats *tp_cpl_stats_buff;
899 	struct cudbg_buffer c_buff, dc_buff;
900 	struct tp_cpl_stats stats;
901 	int rc = 0;
902 
903 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
904 	if (rc)
905 		return rc;
906 
907 	tp_cpl_stats_buff = (struct struct_tp_cpl_stats *) dc_buff.data;
908 	stats = tp_cpl_stats_buff->stats;
909 	if (tp_cpl_stats_buff->nchan == NCHAN) {
910 		printf("                 channel 0"\
911 			     "  channel 1  channel 2  channel 3\n");
912 		printf("CPL requests:   %10u %10u "\
913 			     "%10u %10u\n",
914 			     stats.req[0], stats.req[1], stats.req[2],
915 			     stats.req[3]);
916 		printf("CPL responses:  %10u %10u "\
917 			     "%10u %10u\n",
918 			     stats.rsp[0], stats.rsp[1], stats.rsp[2],
919 			     stats.rsp[3]);
920 	} else {
921 		printf("                 channel 0"\
922 			     "  channel 1\n");
923 		printf("CPL requests:   %10u %10u\n",
924 			     stats.req[0], stats.req[1]);
925 		printf("CPL responses:  %10u %10u\n",
926 			     stats.rsp[0], stats.rsp[1]);
927 	}
928 
929 	return rc;
930 }
931 
932 int
view_ddp_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)933 view_ddp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
934 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
935 {
936 	struct tp_usm_stats *tp_usm_stats_buff;
937 	struct cudbg_buffer c_buff, dc_buff;
938 	int rc = 0;
939 
940 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
941 	if (rc)
942 		return rc;
943 
944 	tp_usm_stats_buff = (struct tp_usm_stats *) dc_buff.data;
945 	printf("Frames: %u\n",
946 		     tp_usm_stats_buff->frames);
947 	printf("Octets: %llu\n",
948 		     (unsigned long long)tp_usm_stats_buff->octets);
949 	printf("Drops:  %u\n",
950 		     tp_usm_stats_buff->drops);
951 
952 	return rc;
953 }
954 
955 int
view_macstats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)956 view_macstats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
957 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
958 {
959 	struct struct_mac_stats_rev1 *macstats_buff1;
960 	struct struct_mac_stats *mac_stats_buff;
961 	struct cudbg_buffer c_buff, dc_buff;
962 	struct port_stats *stats;
963 	u32 port_count, i;
964 	int rc = 0, rev;
965 
966 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
967 	if (rc)
968 		return rc;
969 
970 	rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
971 	if (rev) {
972 		macstats_buff1 = (struct struct_mac_stats_rev1 *)(dc_buff.data);
973 		port_count = macstats_buff1->port_count;
974 		stats = macstats_buff1->stats;
975 
976 	} else {
977 		mac_stats_buff = (struct struct_mac_stats *)(dc_buff.data);
978 		port_count = mac_stats_buff->port_count;
979 		stats = mac_stats_buff->stats;
980 	}
981 
982 	for (i = 0; i < port_count; i++) {
983 		printf("\nMac %d Stats:\n", i);
984 		printf("tx_octets              "\
985 			     "%64llu\n", stats[i].tx_octets);
986 		printf("tx_frames              "\
987 			     "%64llu\n", stats[i].tx_frames);
988 		printf("tx_bcast_frames        "\
989 			     "%64llu\n", stats[i].tx_bcast_frames);
990 		printf("tx_mcast_frames        "\
991 			     "%64llu\n", stats[i].tx_mcast_frames);
992 		printf("tx_ucast_frames        "\
993 			     "%64llu\n", stats[i].tx_ucast_frames);
994 		printf("tx_error_frames        "\
995 			     "%64llu\n", stats[i].tx_error_frames);
996 		printf("tx_frames_64           "\
997 			     "%64llu\n", stats[i].tx_frames_64);
998 		printf("tx_frames_65_127       "\
999 			     "%64llu\n", stats[i].tx_frames_65_127);
1000 		printf("tx_frames_128_255      "\
1001 			     "%64llu\n", stats[i].tx_frames_128_255);
1002 		printf("tx_frames_256_511      "\
1003 			     "%64llu\n", stats[i].tx_frames_256_511);
1004 		printf("tx_frames_512_1023     "\
1005 			     "%64llu\n", stats[i].tx_frames_512_1023);
1006 		printf("tx_frames_1024_1518    "\
1007 			     "%64llu\n", stats[i].tx_frames_1024_1518);
1008 		printf("tx_frames_1519_max     "\
1009 			     "%64llu\n", stats[i].tx_frames_1519_max);
1010 		printf("tx_drop                "\
1011 			     "%64llu\n", stats[i].tx_drop);
1012 		printf("tx_pause               "\
1013 			     "%64llu\n", stats[i].tx_pause);
1014 		printf("tx_ppp0                "\
1015 			     "%64llu\n", stats[i].tx_ppp0);
1016 		printf("tx_ppp1                "\
1017 			     "%64llu\n", stats[i].tx_ppp1);
1018 		printf("tx_ppp2                "\
1019 			     "%64llu\n", stats[i].tx_ppp2);
1020 		printf("tx_ppp3                "\
1021 			     "%64llu\n", stats[i].tx_ppp3);
1022 		printf("tx_ppp4                "\
1023 			     "%64llu\n", stats[i].tx_ppp4);
1024 		printf("tx_ppp5                "\
1025 			     "%64llu\n", stats[i].tx_ppp5);
1026 		printf("tx_ppp6                "\
1027 			     "%64llu\n", stats[i].tx_ppp6);
1028 		printf("tx_ppp7                "\
1029 			     "%64llu\n", stats[i].tx_ppp7);
1030 		printf("rx_octets              "\
1031 			     "%64llu\n", stats[i].rx_octets);
1032 		printf("rx_frames              "\
1033 			     "%64llu\n", stats[i].rx_frames);
1034 		printf("rx_bcast_frames        "\
1035 			     "%64llu\n", stats[i].rx_bcast_frames);
1036 		printf("rx_mcast_frames        "\
1037 			     "%64llu\n", stats[i].rx_mcast_frames);
1038 		printf("rx_ucast_frames        "\
1039 			     "%64llu\n", stats[i].rx_ucast_frames);
1040 		printf("rx_too_long            "\
1041 			     "%64llu\n", stats[i].rx_too_long);
1042 		printf("rx_jabber              "\
1043 			     "%64llu\n", stats[i].rx_jabber);
1044 		printf("rx_fcs_err             "\
1045 			     "%64llu\n", stats[i].rx_fcs_err);
1046 		printf("rx_len_err             "\
1047 			     "%64llu\n", stats[i].rx_len_err);
1048 		printf("rx_symbol_err          "\
1049 			     "%64llu\n", stats[i].rx_symbol_err);
1050 		printf("rx_runt                "\
1051 			     "%64llu\n", stats[i].rx_runt);
1052 		printf("rx_frames_64           "\
1053 			     "%64llu\n", stats[i].rx_frames_64);
1054 		printf("rx_frames_65_127       "\
1055 			     "%64llu\n", stats[i].rx_frames_65_127);
1056 		printf("rx_frames_128_255      "\
1057 			     "%64llu\n", stats[i].rx_frames_128_255);
1058 		printf("rx_frames_256_511      "\
1059 			     "%64llu\n", stats[i].rx_frames_256_511);
1060 		printf("rx_frames_512_1023     "\
1061 			     "%64llu\n", stats[i].rx_frames_512_1023);
1062 		printf("rx_frames_1024_1518    "\
1063 			     "%64llu\n", stats[i].rx_frames_1024_1518);
1064 		printf("rx_frames_1519_max     "\
1065 			     "%64llu\n", stats[i].rx_frames_1519_max);
1066 		printf("rx_pause               "\
1067 			     "%64llu\n", stats[i].rx_pause);
1068 		printf("rx_ppp0                "\
1069 			     "%64llu\n", stats[i].rx_ppp0);
1070 		printf("rx_ppp1                "\
1071 			     "%64llu\n", stats[i].rx_ppp1);
1072 		printf("rx_ppp2                "\
1073 			     "%64llu\n", stats[i].rx_ppp2);
1074 		printf("rx_ppp3                "\
1075 			     "%64llu\n", stats[i].rx_ppp3);
1076 		printf("rx_ppp4                "\
1077 			     "%64llu\n", stats[i].rx_ppp4);
1078 		printf("rx_ppp5                "\
1079 			     "%64llu\n", stats[i].rx_ppp5);
1080 		printf("rx_ppp6                "\
1081 			     "%64llu\n", stats[i].rx_ppp6);
1082 		printf("rx_ppp7                "\
1083 			     "%64llu\n", stats[i].rx_ppp7);
1084 		printf("rx_ovflow0             "\
1085 			     "%64llu\n", stats[i].rx_ovflow0);
1086 		printf("rx_ovflow1             "\
1087 			     "%64llu\n", stats[i].rx_ovflow1);
1088 		printf("rx_ovflow2             "\
1089 			     "%64llu\n", stats[i].rx_ovflow2);
1090 		printf("rx_ovflow3             "\
1091 			     "%64llu\n", stats[i].rx_ovflow3);
1092 		printf("rx_trunc0              "\
1093 			     "%64llu\n", stats[i].rx_trunc0);
1094 		printf("rx_trunc1              "\
1095 			     "%64llu\n", stats[i].rx_trunc1);
1096 		printf("rx_trunc2              "\
1097 			     "%64llu\n", stats[i].rx_trunc2);
1098 		printf("rx_trunc3              "\
1099 			     "%64llu\n", stats[i].rx_trunc3);
1100 	}
1101 
1102 	return rc;
1103 }
1104 
1105 int
view_ulptx_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1106 view_ulptx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1107 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1108 {
1109 	struct struct_ulptx_la *ulptx_la_buff;
1110 	struct cudbg_buffer c_buff, dc_buff;
1111 	void *data;
1112 	int i, rc = 0, rev;
1113 
1114 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1115 	if (rc)
1116 		return rc;
1117 
1118 	data = dc_buff.data + sizeof(struct cudbg_ver_hdr);
1119 	rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
1120 	switch (rev) {
1121 		case 0:
1122 			/* for rev 0 there is no version hdr so
1123  			 * passing dc_buff.data */
1124 			rc = view_ulptx_la_rev0(dc_buff.data, cudbg_poutbuf);
1125 			goto err1;
1126 		case CUDBG_ULPTX_LA_REV:
1127 			/* for rev 1, print first rev 0 and then remaining of rev 1 */
1128 			rc = view_ulptx_la_rev0(data, cudbg_poutbuf);
1129 			if (rc < 0)
1130 				goto err1;
1131 			ulptx_la_buff = (struct struct_ulptx_la *)data;
1132 			break;
1133 		default:
1134 			printf("Unsupported revision %u. Only supports <= %u\n",
1135 			       rev, CUDBG_ULPTX_LA_REV);
1136 			goto err1;
1137 	}
1138 
1139 	printf("\n=======================DUMPING ULP_TX_ASIC_DEBUG=======================\n\n");
1140 
1141 	for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
1142 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1143 			     A_ULP_TX_ASIC_DEBUG_CTRL, i,
1144 			     "A_ULP_TX_ASIC_DEBUG_CTRL",
1145 			     ulptx_la_buff->rdptr_asic[i],
1146 			     ulptx_la_buff->rdptr_asic[i]);
1147 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1148 			     A_ULP_TX_ASIC_DEBUG_0,
1149 			     i, "A_ULP_TX_ASIC_DEBUG_0",
1150 			     ulptx_la_buff->rddata_asic[i][0],
1151 			     ulptx_la_buff->rddata_asic[i][0]);
1152 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1153 			     A_ULP_TX_ASIC_DEBUG_1,
1154 			     i, "A_ULP_TX_ASIC_DEBUG_1",
1155 			     ulptx_la_buff->rddata_asic[i][1],
1156 			     ulptx_la_buff->rddata_asic[i][1]);
1157 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1158 			     A_ULP_TX_ASIC_DEBUG_2,
1159 			     i, "A_ULP_TX_ASIC_DEBUG_2",
1160 			     ulptx_la_buff->rddata_asic[i][2],
1161 			     ulptx_la_buff->rddata_asic[i][2]);
1162 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1163 			     A_ULP_TX_ASIC_DEBUG_3,
1164 			     i, "A_ULP_TX_ASIC_DEBUG_3",
1165 			     ulptx_la_buff->rddata_asic[i][3],
1166 			     ulptx_la_buff->rddata_asic[i][3]);
1167 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1168 			     A_ULP_TX_ASIC_DEBUG_4,
1169 			     i, "A_ULP_TX_ASIC_DEBUG_4",
1170 			     ulptx_la_buff->rddata_asic[i][4],
1171 			     ulptx_la_buff->rddata_asic[i][4]);
1172 		printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
1173 			     PM_RX_BASE_ADDR,
1174 			     i, "PM_RX_BASE_ADDR",
1175 			     ulptx_la_buff->rddata_asic[i][5],
1176 			     ulptx_la_buff->rddata_asic[i][5]);
1177 		printf("\n");
1178 	}
1179 
1180 err1:
1181 	return rc;
1182 
1183 }
1184 
1185 int
view_ulprx_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1186 view_ulprx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1187 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1188 {
1189 	struct struct_ulprx_la *ulprx_la_buff;
1190 	struct cudbg_buffer c_buff, dc_buff;
1191 	int rc = 0;
1192 	u32 i, *p;
1193 
1194 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1195 	if (rc)
1196 		return rc;
1197 
1198 	ulprx_la_buff = (struct struct_ulprx_la *) dc_buff.data;
1199 	p = ulprx_la_buff->data;
1200 
1201 	printf(
1202 		     "      Pcmd        Type   Message                Data\n");
1203 	for (i = 0; i <  ulprx_la_buff->size; i++, p += 8)
1204 		printf(
1205 			     "%08x%08x  %4x  %08x  %08x%08x%08x%08x\n",
1206 			     p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
1207 
1208 	return rc;
1209 }
1210 
1211 int
view_wc_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1212 view_wc_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1213 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1214 {
1215 	struct struct_wc_stats *wc_stats_buff;
1216 	struct cudbg_buffer c_buff, dc_buff;
1217 	int rc = 0;
1218 
1219 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1220 	if (rc)
1221 		return rc;
1222 
1223 	wc_stats_buff = (struct struct_wc_stats *) dc_buff.data;
1224 
1225 	printf("WriteCoalSuccess: %u\n",
1226 		     wc_stats_buff->wr_cl_success);
1227 	printf("WriteCoalFail:    %u\n",
1228 		     wc_stats_buff->wr_cl_fail);
1229 
1230 	return rc;
1231 }
1232 
1233 static int
field_desc_show(u64 v,const struct field_desc * p,struct cudbg_buffer * cudbg_poutbuf)1234 field_desc_show(u64 v, const struct field_desc *p,
1235 		struct cudbg_buffer *cudbg_poutbuf)
1236 {
1237 	int line_size = 0;
1238 	char buf[32];
1239 	int rc = 0;
1240 
1241 	while (p->name) {
1242 		u64 mask = (1ULL << p->width) - 1;
1243 		int len = snprintf(buf, sizeof(buf), "%s: %llu", p->name,
1244 				   ((unsigned long long)v >> p->start) & mask);
1245 
1246 		if (line_size + len >= 79) {
1247 			line_size = 8;
1248 			printf("\n        ");
1249 		}
1250 		printf("%s ", buf);
1251 		line_size += len + 1;
1252 		p++;
1253 	}
1254 	printf("\n");
1255 
1256 	return rc;
1257 }
1258 
1259 static int
tp_la_show(void * v,int idx,struct cudbg_buffer * cudbg_poutbuf)1260 tp_la_show(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
1261 {
1262 	const u64 *p = v;
1263 	int rc;
1264 
1265 	rc = field_desc_show(*p, tp_la0, cudbg_poutbuf);
1266 	return rc;
1267 }
1268 
1269 static int
tp_la_show2(void * v,int idx,struct cudbg_buffer * cudbg_poutbuf)1270 tp_la_show2(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
1271 {
1272 	const u64 *p = v;
1273 	int rc;
1274 
1275 	if (idx)
1276 		printf("'\n");
1277 	rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf);
1278 	if (rc < 0)
1279 		goto err1;
1280 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
1281 		rc = field_desc_show(p[1], tp_la0, cudbg_poutbuf);
1282 
1283 err1:
1284 	return rc;
1285 }
1286 
1287 static int
tp_la_show3(void * v,int idx,struct cudbg_buffer * cudbg_poutbuf)1288 tp_la_show3(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
1289 {
1290 	const u64 *p = v;
1291 	int rc;
1292 
1293 	if (idx)
1294 		printf("\n");
1295 	rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf);
1296 	if (rc < 0)
1297 		goto err1;
1298 	if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
1299 		rc = field_desc_show(p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1,
1300 				     cudbg_poutbuf);
1301 
1302 err1:
1303 	return rc;
1304 }
1305 
1306 int
view_tp_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1307 view_tp_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1308 	   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1309 {
1310 	static int (*la_show) (void *v, int idx,
1311 			       struct cudbg_buffer *cudbg_poutbuf);
1312 	struct cudbg_buffer c_buff, dc_buff;
1313 	struct struct_tp_la *tp_la_buff;
1314 	int i, rc = 0;
1315 
1316 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1317 	if (rc)
1318 		return rc;
1319 
1320 	tp_la_buff = (struct struct_tp_la *) dc_buff.data;
1321 	switch (tp_la_buff->mode) {
1322 	case 2:
1323 		la_show = tp_la_show2;
1324 		break;
1325 	case 3:
1326 		la_show = tp_la_show3;
1327 		break;
1328 	default:
1329 		la_show = tp_la_show;
1330 	}
1331 
1332 	for (i = 0; i < TPLA_SIZE/2; i++) {
1333 		rc = la_show((u64 *)tp_la_buff->data + i*2, i, cudbg_poutbuf);
1334 		if (rc < 0)
1335 			goto err1;
1336 	}
1337 
1338 err1:
1339 	return rc;
1340 }
1341 
1342 static unsigned long
do_div(unsigned long * number,u32 divisor)1343 do_div(unsigned long *number, u32 divisor)
1344 {
1345 	unsigned long remainder = *number % divisor;
1346 
1347 	(*number) /= divisor;
1348 	return remainder;
1349 }
1350 
1351 static int
string_get_size(unsigned long size,const enum string_size_units units,char * buf,int len)1352 string_get_size(unsigned long size,
1353 		const enum string_size_units units, char *buf,
1354 		int len)
1355 {
1356 	const char *units_10[] = {
1357 		"B", "kB", "MB", "GB", "TB", "PB",
1358 		"EB", "ZB", "YB", NULL
1359 	};
1360 	const char *units_2[] = {
1361 		"B", "KiB", "MiB", "GiB", "TiB", "PiB",
1362 		"EiB", "ZiB", "YiB", NULL
1363 	};
1364 	const char **units_str[2];/* = {units_10, units_2};*/
1365 	const u32 divisor[] = {1000, 1024};
1366 	unsigned long remainder = 0;
1367 	unsigned long sf_cap = 0;
1368 	char tmp[8] = {0};
1369 	int i, j;
1370 
1371 	tmp[0] = '\0';
1372 	i = 0;
1373 
1374 	units_str[STRING_UNITS_10] = units_10;
1375 	units_str[STRING_UNITS_2] = units_2;
1376 
1377 	if (size >= divisor[units]) {
1378 		while (size >= divisor[units] && units_str[units][i]) {
1379 			remainder = do_div(&size, divisor[units]);
1380 			i++;
1381 		}
1382 
1383 		sf_cap = size;
1384 
1385 		for (j = 0; sf_cap*10 < 1000; j++)
1386 			sf_cap *= 10;
1387 
1388 		if (j) {
1389 			remainder *= 1000;
1390 			do_div(&remainder, divisor[units]);
1391 
1392 			(void)snprintf(tmp, sizeof(tmp), ".%03lu",
1393 						   (unsigned long)remainder);
1394 			tmp[j + 1] = '\0';
1395 		}
1396 	}
1397 
1398 	(void)snprintf(buf, len, "%lu%s %s", (unsigned long)size, tmp,
1399 		 units_str[units][i]);
1400 
1401 	return 0;
1402 }
1403 
1404 static int
mem_region_show(const char * name,u32 from,u32 to,struct cudbg_buffer * cudbg_poutbuf)1405 mem_region_show(const char *name, u32 from, u32 to,
1406 		struct cudbg_buffer *cudbg_poutbuf)
1407 {
1408 	char buf[40] = {0};
1409 	int rc = 0;
1410 
1411 	string_get_size((u64)to - from + 1, STRING_UNITS_2,
1412 			buf, sizeof(buf));
1413 	printf("%-14s %#x-%#x [%s]\n", name, from,
1414 		     to, buf);
1415 
1416 	return rc;
1417 } /* mem_region_show */
1418 
1419 int
view_meminfo(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1420 view_meminfo(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1421 	     struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1422 {
1423 	struct struct_meminfo *meminfo_buff;
1424 	struct cudbg_buffer c_buff, dc_buff;
1425 	u32 i, lo, idx;
1426 	int rc = 0, rev;
1427 
1428 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1429 	if (rc)
1430 		return rc;
1431 
1432 	rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
1433 	switch (rev) {
1434 		case 0:
1435 			meminfo_buff = (struct struct_meminfo *)dc_buff.data;
1436 			break;
1437 		case CUDBG_MEMINFO_REV:
1438 			meminfo_buff = (struct struct_meminfo *)
1439 				       (dc_buff.data +
1440 				        sizeof(struct cudbg_ver_hdr));
1441 			break;
1442 		default:
1443 			printf("Unsupported revision %u. Only supports <= %u\n",
1444 				rev, CUDBG_MEMINFO_REV);
1445 			goto err1;
1446 	}
1447 
1448 	for (lo = 0; lo < meminfo_buff->avail_c; lo++) {
1449 		idx = meminfo_buff->avail[lo].idx;
1450 		rc = mem_region_show(memory[idx], meminfo_buff->avail[lo].base,
1451 				     meminfo_buff->avail[lo].limit - 1,
1452 				     cudbg_poutbuf);
1453 		if (rc < 0)
1454 			goto err1;
1455 	}
1456 
1457 	for (i = 0; i < meminfo_buff->mem_c; i++) {
1458 		if (meminfo_buff->mem[i].idx >= ARRAY_SIZE(region))
1459 			continue;                        /* skip holes */
1460 		if (!(meminfo_buff->mem[i].limit))
1461 			meminfo_buff->mem[i].limit =
1462 				i < meminfo_buff->mem_c - 1 ?
1463 				meminfo_buff->mem[i + 1].base - 1 : ~0;
1464 
1465 		idx = meminfo_buff->mem[i].idx;
1466 		rc = mem_region_show(region[idx], meminfo_buff->mem[i].base,
1467 				     meminfo_buff->mem[i].limit, cudbg_poutbuf);
1468 		if (rc < 0)
1469 			goto err1;
1470 	}
1471 
1472 	rc = mem_region_show("uP RAM:", meminfo_buff->up_ram_lo,
1473 			     meminfo_buff->up_ram_hi, cudbg_poutbuf);
1474 	if (rc < 0)
1475 		goto err1;
1476 	rc = mem_region_show("uP Extmem2:", meminfo_buff->up_extmem2_lo,
1477 			     meminfo_buff->up_extmem2_hi, cudbg_poutbuf);
1478 	if (rc < 0)
1479 		goto err1;
1480 
1481 	if (rev == 0) {
1482 		struct struct_meminfo_rev0 *meminfo_buff_rev0 =
1483 			(struct struct_meminfo_rev0 *)meminfo_buff;
1484 
1485 		printf("\n%u Rx pages of size %uKiB for %u channels\n",
1486 			     meminfo_buff_rev0->rx_pages_data[0],
1487 			     meminfo_buff_rev0->rx_pages_data[1],
1488 			     meminfo_buff_rev0->rx_pages_data[2]);
1489 		printf("%u Tx pages of size %u%ciB for %u channels\n\n",
1490 			     meminfo_buff_rev0->tx_pages_data[0],
1491 			     meminfo_buff_rev0->tx_pages_data[1],
1492 			     meminfo_buff_rev0->tx_pages_data[2],
1493 			     meminfo_buff_rev0->tx_pages_data[3]);
1494 	} else if (rev == CUDBG_MEMINFO_REV) {
1495 		printf("\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
1496 			     meminfo_buff->rx_pages_data[0],
1497 			     meminfo_buff->free_rx_cnt,
1498 			     meminfo_buff->rx_pages_data[1],
1499 			     meminfo_buff->rx_pages_data[2]);
1500 		printf("%u Tx pages (%u free) of size %u%ciB for %u channels\n",
1501 			     meminfo_buff->tx_pages_data[0],
1502 			     meminfo_buff->free_tx_cnt,
1503 			     meminfo_buff->tx_pages_data[1],
1504 			     meminfo_buff->tx_pages_data[2],
1505 			     meminfo_buff->tx_pages_data[3]);
1506 		printf("%u p-structs (%u free)\n\n",
1507 			     meminfo_buff->p_structs,
1508 			     meminfo_buff->pstructs_free_cnt);
1509 	}
1510 
1511 	for (i = 0; i < 4; i++) {
1512 		printf("Port %d using %u pages out "\
1513 			     "of %u allocated\n",
1514 			     i, meminfo_buff->port_used[i],
1515 			     meminfo_buff->port_alloc[i]);
1516 	}
1517 
1518 	for (i = 0; i < NCHAN; i++) {
1519 		printf("Loopback %d using %u pages "\
1520 			     "out of %u allocated\n",
1521 			     i, meminfo_buff->loopback_used[i],
1522 			     meminfo_buff->loopback_alloc[i]);
1523 	}
1524 
1525 err1:
1526 	return rc;
1527 }
1528 
1529 int
view_lb_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1530 view_lb_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1531 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1532 {
1533 	struct struct_lb_stats *lb_stats_buff;
1534 	struct cudbg_buffer c_buff, dc_buff;
1535 	struct lb_port_stats *tmp_stats;
1536 	int i, j, rc = 0;
1537 	u64 *p0, *p1;
1538 
1539 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1540 	if (rc)
1541 		return rc;
1542 
1543 	lb_stats_buff = (struct struct_lb_stats *) dc_buff.data;
1544 	tmp_stats  = lb_stats_buff->s;
1545 	for (i = 0; i < lb_stats_buff->nchan; i += 2, tmp_stats += 2) {
1546 		p0 = &(tmp_stats[0].octets);
1547 		p1 = &(tmp_stats[1].octets);
1548 		printf("%s                       "\
1549 			     "Loopback %u           Loopback %u\n",
1550 			     i == 0 ? "" : "\n", i, i + 1);
1551 
1552 		for (j = 0; j < ARRAY_SIZE(lb_stat_name); j++)
1553 			printf("%-17s %20llu "\
1554 				     "%20llu\n", lb_stat_name[j],
1555 				     (unsigned long long)*p0++,
1556 				     (unsigned long long)*p1++);
1557 	}
1558 
1559 	return rc;
1560 }
1561 
1562 int
view_rdma_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1563 view_rdma_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1564 		struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1565 {
1566 	struct tp_rdma_stats *rdma_stats_buff;
1567 	struct cudbg_buffer c_buff, dc_buff;
1568 	int rc = 0;
1569 
1570 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1571 	if (rc)
1572 		return rc;
1573 
1574 	rdma_stats_buff = (struct tp_rdma_stats *) dc_buff.data;
1575 	printf("NoRQEModDefferals: %u\n",
1576 		     rdma_stats_buff->rqe_dfr_mod);
1577 	printf("NoRQEPktDefferals: %u\n",
1578 		     rdma_stats_buff->rqe_dfr_pkt);
1579 
1580 	return rc;
1581 }
1582 
1583 int
view_clk_info(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1584 view_clk_info(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1585 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1586 {
1587 	struct struct_clk_info *clk_info_buff;
1588 	struct cudbg_buffer c_buff, dc_buff;
1589 	char tmp[32] = { 0 };
1590 	int rc = 0;
1591 
1592 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1593 	if (rc)
1594 		return rc;
1595 
1596 	clk_info_buff = (struct struct_clk_info *) dc_buff.data;
1597 
1598 	unit_conv(tmp, 32, clk_info_buff->cclk_ps, 1000);
1599 	printf("Core clock period: %s ns\n", tmp);
1600 
1601 	unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->tre,
1602 		  1000000);
1603 	printf("TP timer tick: %s us\n", tmp);
1604 
1605 	unit_conv(tmp, 32,
1606 		  clk_info_buff->cclk_ps << G_TIMESTAMPRESOLUTION(clk_info_buff->res),
1607 		  1000000);
1608 	printf("TCP timestamp tick: %s us\n", tmp);
1609 
1610 	unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->dack_re,
1611 		  1000000);
1612 	printf("DACK tick: %s us\n", tmp);
1613 
1614 	printf("DACK timer: %u us\n",
1615 		     clk_info_buff->dack_timer);
1616 	printf("Retransmit min: %llu us\n",
1617 		     clk_info_buff->retransmit_min);
1618 	printf("Retransmit max: %llu us\n",
1619 		     clk_info_buff->retransmit_max);
1620 	printf("Persist timer min: %llu us\n",
1621 		     clk_info_buff->persist_timer_min);
1622 	printf("Persist timer max: %llu us\n",
1623 		     clk_info_buff->persist_timer_max);
1624 	printf("Keepalive idle timer: %llu us\n",
1625 		     clk_info_buff->keepalive_idle_timer);
1626 	printf("Keepalive interval: %llu us\n",
1627 		     clk_info_buff->keepalive_interval);
1628 	printf("Initial SRTT: %llu us\n",
1629 		     clk_info_buff->initial_srtt);
1630 	printf("FINWAIT2 timer: %llu us\n",
1631 		     clk_info_buff->finwait2_timer);
1632 
1633 	return rc;
1634 }
1635 
1636 int
view_cim_pif_la(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1637 view_cim_pif_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1638 		struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1639 {
1640 	struct cudbg_buffer c_buff, dc_buff;
1641 	struct cim_pif_la *cim_pif_la_buff;
1642 	int i, rc = 0;
1643 	u32 *p;
1644 
1645 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1646 	if (rc)
1647 		return rc;
1648 
1649 	cim_pif_la_buff = (struct cim_pif_la *) dc_buff.data;
1650 	p = (u32 *)cim_pif_la_buff->data;
1651 
1652 	printf("Cntl ID DataBE   Addr            "\
1653 		     "     Data\n");
1654 	for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6)
1655 		printf(" %02x  %02x  %04x  %08x "\
1656 			     "%08x%08x%08x%08x\n",
1657 			     (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f,
1658 			     p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]);
1659 
1660 	p = (u32 *) cim_pif_la_buff->data +  6 * CIM_PIFLA_SIZE;
1661 
1662 	printf("\nCntl ID               Data\n");
1663 	for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6)
1664 		printf(" %02x  %02x "\
1665 			     "%08x%08x%08x%08x\n",
1666 			     (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1],
1667 			     p[0]);
1668 
1669 	return rc;
1670 }
1671 
1672 int
view_fcoe_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1673 view_fcoe_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1674 		struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1675 {
1676 	struct struct_tp_fcoe_stats *tp_fcoe_stats_buff;
1677 	struct cudbg_buffer c_buff, dc_buff;
1678 	struct tp_fcoe_stats stats[4];
1679 	int rc = 0;
1680 
1681 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1682 	if (rc)
1683 		return rc;
1684 
1685 	tp_fcoe_stats_buff = (struct struct_tp_fcoe_stats *) dc_buff.data;
1686 	memcpy(stats, tp_fcoe_stats_buff->stats, sizeof(stats));
1687 
1688 	if (tp_fcoe_stats_buff->nchan == NCHAN) {
1689 		printf("                   channel "\
1690 			     "0        channel 1        channel 2        "\
1691 			     "channel 3\n");
1692 		printf("octetsDDP:  %16llu %16llu "\
1693 			     "%16llu %16llu\n",
1694 			     stats[0].octets_ddp, stats[1].octets_ddp,
1695 			     stats[2].octets_ddp, stats[3].octets_ddp);
1696 		printf("framesDDP:  %16u %16u %16u "\
1697 			     "%16u\n",
1698 			     stats[0].frames_ddp, stats[1].frames_ddp,
1699 			     stats[2].frames_ddp, stats[3].frames_ddp);
1700 		printf("framesDrop: %16u %16u %16u "\
1701 			     "%16u\n",
1702 			     stats[0].frames_drop, stats[1].frames_drop,
1703 			     stats[2].frames_drop, stats[3].frames_drop);
1704 	} else {
1705 		printf("                   channel "\
1706 			     "0        channel 1\n");
1707 		printf("octetsDDP:  %16llu "\
1708 			     "%16llu\n",
1709 			     stats[0].octets_ddp, stats[1].octets_ddp);
1710 		printf("framesDDP:  %16u %16u\n",
1711 			     stats[0].frames_ddp, stats[1].frames_ddp);
1712 		printf("framesDrop: %16u %16u\n",
1713 			     stats[0].frames_drop, stats[1].frames_drop);
1714 	}
1715 
1716 	return rc;
1717 }
1718 
1719 int
view_tp_err_stats_show(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1720 view_tp_err_stats_show(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1721 		       struct cudbg_buffer *cudbg_poutbuf,
1722 		       enum chip_type chip)
1723 {
1724 	struct struct_tp_err_stats *tp_err_stats_buff;
1725 	struct cudbg_buffer c_buff, dc_buff;
1726 	struct tp_err_stats stats;
1727 	int rc = 0;
1728 
1729 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1730 	if (rc)
1731 		return rc;
1732 
1733 	tp_err_stats_buff = (struct struct_tp_err_stats *) dc_buff.data;
1734 	stats = tp_err_stats_buff->stats;
1735 	if (tp_err_stats_buff->nchan == NCHAN) {
1736 		printf("                 channel 0"\
1737 			     "  channel 1  channel 2  channel 3\n");
1738 		printf("macInErrs:      %10u %10u "\
1739 			     "%10u %10u\n",
1740 			     stats.mac_in_errs[0], stats.mac_in_errs[1],
1741 			     stats.mac_in_errs[2], stats.mac_in_errs[3]);
1742 		printf("hdrInErrs:      %10u %10u "\
1743 			     "%10u %10u\n",
1744 			     stats.hdr_in_errs[0], stats.hdr_in_errs[1],
1745 			     stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
1746 		printf("tcpInErrs:      %10u %10u "\
1747 			     "%10u %10u\n",
1748 			     stats.tcp_in_errs[0], stats.tcp_in_errs[1],
1749 			     stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
1750 		printf("tcp6InErrs:     %10u %10u "\
1751 			     "%10u %10u\n",
1752 			     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
1753 			     stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
1754 		printf("tnlCongDrops:   %10u %10u "\
1755 			     "%10u %10u\n",
1756 			     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
1757 			     stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
1758 		printf("tnlTxDrops:     %10u %10u "\
1759 			     "%10u %10u\n",
1760 			     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
1761 			     stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
1762 		printf("ofldVlanDrops:  %10u %10u "\
1763 			     "%10u %10u\n",
1764 			     stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
1765 			     stats.ofld_vlan_drops[2],
1766 			     stats.ofld_vlan_drops[3]);
1767 		printf("ofldChanDrops:  %10u %10u "\
1768 			     "%10u %10u\n\n",
1769 			     stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
1770 			     stats.ofld_chan_drops[2],
1771 			     stats.ofld_chan_drops[3]);
1772 	} else {
1773 		printf("                 channel 0"\
1774 			     "  channel 1\n");
1775 		printf("macInErrs:      %10u %10u\n",
1776 			     stats.mac_in_errs[0], stats.mac_in_errs[1]);
1777 		printf("hdrInErrs:      %10u %10u\n",
1778 			     stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
1779 		printf("tcpInErrs:      %10u %10u\n",
1780 			     stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
1781 		printf("tcp6InErrs:     %10u %10u\n",
1782 			     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
1783 		printf("tnlCongDrops:   %10u %10u\n",
1784 			     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
1785 		printf("tnlTxDrops:     %10u %10u\n",
1786 			     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
1787 		printf("ofldVlanDrops:  %10u %10u\n",
1788 			     stats.ofld_vlan_drops[0],
1789 			     stats.ofld_vlan_drops[1]);
1790 		printf("ofldChanDrops:  %10u %10u"\
1791 			     "\n\n", stats.ofld_chan_drops[0],
1792 			     stats.ofld_chan_drops[1]);
1793 	}
1794 
1795 	printf("ofldNoNeigh:    %u\nofldCongDefer: "\
1796 		     " %u\n", stats.ofld_no_neigh, stats.ofld_cong_defer);
1797 
1798 	return rc;
1799 }
1800 
1801 int
view_tcp_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1802 view_tcp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1803 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1804 {
1805 	struct struct_tcp_stats *tcp_stats_buff;
1806 	struct cudbg_buffer c_buff, dc_buff;
1807 	int rc = 0;
1808 
1809 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1810 	if (rc)
1811 		return rc;
1812 
1813 	tcp_stats_buff = (struct struct_tcp_stats *) dc_buff.data;
1814 	printf("                                IP"\
1815 		     "                 IPv6\n");
1816 	printf("OutRsts:      %20u %20u\n",
1817 		     tcp_stats_buff->v4.tcp_out_rsts,
1818 		     tcp_stats_buff->v6.tcp_out_rsts);
1819 	printf("InSegs:       %20llu %20llu\n",
1820 		     (unsigned long long)(tcp_stats_buff->v4.tcp_in_segs),
1821 		     (unsigned long long)(tcp_stats_buff->v6.tcp_in_segs));
1822 	printf("OutSegs:      %20llu %20llu\n",
1823 		     (unsigned long long)(tcp_stats_buff->v4.tcp_out_segs),
1824 		     (unsigned long long)(tcp_stats_buff->v6.tcp_out_segs));
1825 	printf("RetransSegs:  %20llu %20llu\n",
1826 		     (unsigned long long)(tcp_stats_buff->v4.tcp_retrans_segs),
1827 		     (unsigned long long)(tcp_stats_buff->v6.tcp_retrans_segs));
1828 
1829 	return rc;
1830 }
1831 
1832 int
view_hw_sched(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1833 view_hw_sched(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1834 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1835 {
1836 	struct struct_hw_sched *hw_sched_buff;
1837 	struct cudbg_buffer c_buff, dc_buff;
1838 	int i, rc = 0;
1839 
1840 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1841 	if (rc)
1842 		return rc;
1843 
1844 	hw_sched_buff = (struct struct_hw_sched *)dc_buff.data;
1845 
1846 	printf("Scheduler  Mode   Channel  Rate "\
1847 		     "(Kbps)   Class IPG (0.1 ns)   Flow IPG (us)\n");
1848 	for (i = 0; i < NTX_SCHED; ++i, hw_sched_buff->map >>= 2) {
1849 		printf("    %u      %-5s     %u"\
1850 			     "     ", i,
1851 			     (hw_sched_buff->mode & (1 << i)) ?
1852 			     "flow" : "class",
1853 			     hw_sched_buff->map & 3);
1854 		if (hw_sched_buff->kbps[i]) {
1855 			printf("%9u     ",
1856 				     hw_sched_buff->kbps[i]);
1857 		} else {
1858 			printf(" disabled     ");
1859 		}
1860 
1861 		if (hw_sched_buff->ipg[i]) {
1862 			printf("%13u        ",
1863 				     hw_sched_buff->ipg[i]);
1864 		} else {
1865 			printf("     disabled    "\
1866 				     "    ");
1867 		}
1868 
1869 		if (hw_sched_buff->pace_tab[i]) {
1870 			printf("%10u\n",
1871 				     hw_sched_buff->pace_tab[i]);
1872 		} else {
1873 			printf("  disabled\n");
1874 		}
1875 	}
1876 
1877 	return rc;
1878 }
1879 
1880 int
view_pm_stats(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1881 view_pm_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1882 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1883 {
1884 	static const char * const tx_pm_stats[] = {
1885 		"Read:", "Write bypass:", "Write mem:", "Bypass + mem:"
1886 	};
1887 	static const char * const rx_pm_stats[] = {
1888 		"Read:", "Write bypass:", "Write mem:", "Flush:"
1889 	};
1890 	struct struct_pm_stats *pm_stats_buff;
1891 	struct cudbg_buffer c_buff, dc_buff;
1892 	int i, rc = 0;
1893 
1894 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1895 	if (rc)
1896 		return rc;
1897 
1898 	pm_stats_buff = (struct struct_pm_stats *)dc_buff.data;
1899 
1900 	printf("%13s %10s  %20s\n", " ", "Tx pcmds",
1901 		     "Tx bytes");
1902 	for (i = 0; i < PM_NSTATS - 1; i++)
1903 		printf("%-13s %10u  %20llu\n",
1904 			     tx_pm_stats[i], pm_stats_buff->tx_cnt[i],
1905 			     pm_stats_buff->tx_cyc[i]);
1906 
1907 	printf("%13s %10s  %20s\n", " ", "Rx pcmds",
1908 		     "Rx bytes");
1909 	for (i = 0; i < PM_NSTATS - 1; i++)
1910 		printf("%-13s %10u  %20llu\n",
1911 			     rx_pm_stats[i], pm_stats_buff->rx_cnt[i],
1912 			     pm_stats_buff->rx_cyc[i]);
1913 
1914 	if (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5) {
1915 		/* In T5 the granularity of the total wait is too fine.
1916 		 * It is not useful as it reaches the max value too fast.
1917 		 * Hence display this Input FIFO wait for T6 onwards.
1918 		 */
1919 		printf("%13s %10s  %20s\n",
1920 			   " ", "Total wait", "Total Occupancy");
1921 		printf("Tx FIFO wait  "
1922 			     "%10u  %20llu\n", pm_stats_buff->tx_cnt[i],
1923 			     pm_stats_buff->tx_cyc[i]);
1924 		printf("Rx FIFO wait  %10u  "
1925 			     "%20llu\n", pm_stats_buff->rx_cnt[i],
1926 			     pm_stats_buff->rx_cyc[i]);
1927 
1928 		/* Skip index 6 as there is nothing useful here */
1929 		i += 2;
1930 
1931 		/* At index 7, a new stat for read latency (count, total wait)
1932 		 * is added.
1933 		 */
1934 		printf("%13s %10s  %20s\n",
1935 			     " ", "Reads", "Total wait");
1936 		printf("Tx latency    "
1937 			     "%10u  %20llu\n", pm_stats_buff->tx_cnt[i],
1938 			     pm_stats_buff->tx_cyc[i]);
1939 		printf("Rx latency    "
1940 			     "%10u  %20llu\n", pm_stats_buff->rx_cnt[i],
1941 			     pm_stats_buff->rx_cyc[i]);
1942 	}
1943 
1944 	return rc;
1945 }
1946 
1947 int
view_path_mtu(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1948 view_path_mtu(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1949 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1950 {
1951 	struct cudbg_buffer c_buff, dc_buff;
1952 	int rc = 0;
1953 	u16 *mtus;
1954 
1955 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1956 	if (rc)
1957 		return rc;
1958 
1959 	mtus = (u16 *)dc_buff.data;
1960 	printf("%u %u %u %u %u %u %u %u %u %u %u %u"\
1961 		     " %u %u %u %u\n",
1962 		     mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5],
1963 		     mtus[6], mtus[7], mtus[8], mtus[9], mtus[10], mtus[11],
1964 		     mtus[12], mtus[13], mtus[14], mtus[15]);
1965 
1966 	return rc;
1967 }
1968 
1969 int
view_rss_config(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)1970 view_rss_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
1971 		struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
1972 {
1973 	static const char * const keymode[] = {
1974 		"global",
1975 		"global and per-VF scramble",
1976 		"per-PF and per-VF scramble",
1977 		"per-VF and per-VF scramble",
1978 	};
1979 	struct cudbg_buffer c_buff, dc_buff;
1980 	struct rss_config *struct_rss_conf;
1981 	u32 rssconf;
1982 	int rc = 0;
1983 
1984 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
1985 	if (rc)
1986 		return rc;
1987 
1988 	struct_rss_conf = (struct rss_config *)dc_buff.data;
1989 	rssconf = struct_rss_conf->tp_rssconf;
1990 	printf("TP_RSS_CONFIG: %#x\n", rssconf);
1991 	printf("  Tnl4TupEnIpv6: %3s\n",
1992 		     yesno(rssconf & F_TNL4TUPENIPV6));
1993 	printf("  Tnl2TupEnIpv6: %3s\n",
1994 		     yesno(rssconf & F_TNL2TUPENIPV6));
1995 	printf("  Tnl4TupEnIpv4: %3s\n",
1996 		     yesno(rssconf & F_TNL4TUPENIPV4));
1997 	printf("  Tnl2TupEnIpv4: %3s\n",
1998 		     yesno(rssconf & F_TNL2TUPENIPV4));
1999 	printf("  TnlTcpSel:     %3s\n",
2000 		     yesno(rssconf & F_TNLTCPSEL));
2001 	printf("  TnlIp6Sel:     %3s\n",
2002 		     yesno(rssconf & F_TNLIP6SEL));
2003 	printf("  TnlVrtSel:     %3s\n",
2004 		     yesno(rssconf & F_TNLVRTSEL));
2005 	printf("  TnlMapEn:      %3s\n",
2006 		     yesno(rssconf & F_TNLMAPEN));
2007 	printf("  OfdHashSave:   %3s\n",
2008 		     yesno(rssconf & F_OFDHASHSAVE));
2009 	printf("  OfdVrtSel:     %3s\n",
2010 		     yesno(rssconf & F_OFDVRTSEL));
2011 	printf("  OfdMapEn:      %3s\n",
2012 		     yesno(rssconf & F_OFDMAPEN));
2013 	printf("  OfdLkpEn:      %3s\n",
2014 		     yesno(rssconf & F_OFDLKPEN));
2015 	printf("  Syn4TupEnIpv6: %3s\n",
2016 		     yesno(rssconf & F_SYN4TUPENIPV6));
2017 	printf("  Syn2TupEnIpv6: %3s\n",
2018 		     yesno(rssconf & F_SYN2TUPENIPV6));
2019 	printf("  Syn4TupEnIpv4: %3s\n",
2020 		     yesno(rssconf & F_SYN4TUPENIPV4));
2021 	printf("  Syn2TupEnIpv4: %3s\n",
2022 		     yesno(rssconf & F_SYN2TUPENIPV4));
2023 	printf("  Syn4TupEnIpv6: %3s\n",
2024 		     yesno(rssconf & F_SYN4TUPENIPV6));
2025 	printf("  SynIp6Sel:     %3s\n",
2026 		     yesno(rssconf & F_SYNIP6SEL));
2027 	printf("  SynVrt6Sel:    %3s\n",
2028 		     yesno(rssconf & F_SYNVRTSEL));
2029 	printf("  SynMapEn:      %3s\n",
2030 		     yesno(rssconf & F_SYNMAPEN));
2031 	printf("  SynLkpEn:      %3s\n",
2032 		     yesno(rssconf & F_SYNLKPEN));
2033 	printf("  ChnEn:         %3s\n",
2034 		     yesno(rssconf & F_CHANNELENABLE));
2035 	printf("  PrtEn:         %3s\n",
2036 		     yesno(rssconf & F_PORTENABLE));
2037 	printf("  TnlAllLkp:     %3s\n",
2038 		     yesno(rssconf & F_TNLALLLOOKUP));
2039 	printf("  VrtEn:         %3s\n",
2040 		     yesno(rssconf & F_VIRTENABLE));
2041 	printf("  CngEn:         %3s\n",
2042 		     yesno(rssconf & F_CONGESTIONENABLE));
2043 	printf("  HashToeplitz:  %3s\n",
2044 		     yesno(rssconf & F_HASHTOEPLITZ));
2045 	printf("  Udp4En:        %3s\n",
2046 		     yesno(rssconf & F_UDPENABLE));
2047 	printf("  Disable:       %3s\n",
2048 		     yesno(rssconf & F_DISABLE));
2049 
2050 	rssconf = struct_rss_conf->tp_rssconf_tnl;
2051 	printf("TP_RSS_CONFIG_TNL: %#x\n",
2052 		     rssconf);
2053 	printf("  MaskSize:      %3d\n",
2054 		     G_MASKSIZE(rssconf));
2055 	printf("  MaskFilter:    %3d\n",
2056 		     G_MASKFILTER(rssconf));
2057 	if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) {
2058 		printf("  HashAll:     %3s\n",
2059 			     yesno(rssconf & F_HASHALL));
2060 		printf("  HashEth:     %3s\n",
2061 			     yesno(rssconf & F_HASHETH));
2062 	}
2063 	printf("  UseWireCh:     %3s\n",
2064 		     yesno(rssconf & F_USEWIRECH));
2065 
2066 	rssconf = struct_rss_conf->tp_rssconf_ofd;
2067 	printf("TP_RSS_CONFIG_OFD: %#x\n",
2068 		     rssconf);
2069 	printf("  MaskSize:      %3d\n",
2070 		     G_MASKSIZE(rssconf));
2071 	printf("  RRCplMapEn:    %3s\n",
2072 		     yesno(rssconf & F_RRCPLMAPEN));
2073 	printf("  RRCplQueWidth: %3d\n",
2074 		     G_RRCPLQUEWIDTH(rssconf));
2075 
2076 	rssconf = struct_rss_conf->tp_rssconf_syn;
2077 	printf("TP_RSS_CONFIG_SYN: %#x\n",
2078 		     rssconf);
2079 	printf("  MaskSize:      %3d\n",
2080 		     G_MASKSIZE(rssconf));
2081 	printf("  UseWireCh:     %3s\n",
2082 		     yesno(rssconf & F_USEWIRECH));
2083 
2084 	rssconf = struct_rss_conf->tp_rssconf_vrt;
2085 	printf("TP_RSS_CONFIG_VRT: %#x\n",
2086 		     rssconf);
2087 	if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) {
2088 		printf("  KeyWrAddrX:     %3d\n",
2089 			     G_KEYWRADDRX(rssconf));
2090 		printf("  KeyExtend:      %3s\n",
2091 			     yesno(rssconf & F_KEYEXTEND));
2092 	}
2093 	printf("  VfRdRg:        %3s\n",
2094 		     yesno(rssconf & F_VFRDRG));
2095 	printf("  VfRdEn:        %3s\n",
2096 		     yesno(rssconf & F_VFRDEN));
2097 	printf("  VfPerrEn:      %3s\n",
2098 		     yesno(rssconf & F_VFPERREN));
2099 	printf("  KeyPerrEn:     %3s\n",
2100 		     yesno(rssconf & F_KEYPERREN));
2101 	printf("  DisVfVlan:     %3s\n",
2102 		     yesno(rssconf & F_DISABLEVLAN));
2103 	printf("  EnUpSwt:       %3s\n",
2104 		     yesno(rssconf & F_ENABLEUP0));
2105 	printf("  HashDelay:     %3d\n",
2106 		     G_HASHDELAY(rssconf));
2107 	if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) <= CHELSIO_T5) {
2108 		printf("  VfWrAddr:      %3d\n",
2109 			     G_VFWRADDR(rssconf));
2110 	} else {
2111 		printf("  VfWrAddr:      %3d\n",
2112 			     G_T6_VFWRADDR(rssconf));
2113 	}
2114 	printf("  KeyMode:       %s\n",
2115 		     keymode[G_KEYMODE(rssconf)]);
2116 	printf("  VfWrEn:        %3s\n",
2117 		     yesno(rssconf & F_VFWREN));
2118 	printf("  KeyWrEn:       %3s\n",
2119 		     yesno(rssconf & F_KEYWREN));
2120 	printf("  KeyWrAddr:     %3d\n",
2121 		     G_KEYWRADDR(rssconf));
2122 
2123 	rssconf = struct_rss_conf->tp_rssconf_cng;
2124 	printf("TP_RSS_CONFIG_CNG: %#x\n",
2125 		     rssconf);
2126 	printf("  ChnCount3:     %3s\n",
2127 		     yesno(rssconf & F_CHNCOUNT3));
2128 	printf("  ChnCount2:     %3s\n",
2129 		     yesno(rssconf & F_CHNCOUNT2));
2130 	printf("  ChnCount1:     %3s\n",
2131 		     yesno(rssconf & F_CHNCOUNT1));
2132 	printf("  ChnCount0:     %3s\n",
2133 		     yesno(rssconf & F_CHNCOUNT0));
2134 	printf("  ChnUndFlow3:   %3s\n",
2135 		     yesno(rssconf & F_CHNUNDFLOW3));
2136 	printf("  ChnUndFlow2:   %3s\n",
2137 		     yesno(rssconf & F_CHNUNDFLOW2));
2138 	printf("  ChnUndFlow1:   %3s\n",
2139 		     yesno(rssconf & F_CHNUNDFLOW1));
2140 	printf("  ChnUndFlow0:   %3s\n",
2141 		     yesno(rssconf & F_CHNUNDFLOW0));
2142 	printf("  RstChn3:       %3s\n",
2143 		     yesno(rssconf & F_RSTCHN3));
2144 	printf("  RstChn2:       %3s\n",
2145 		     yesno(rssconf & F_RSTCHN2));
2146 	printf("  RstChn1:       %3s\n",
2147 		     yesno(rssconf & F_RSTCHN1));
2148 	printf("  RstChn0:       %3s\n",
2149 		     yesno(rssconf & F_RSTCHN0));
2150 	printf("  UpdVld:        %3s\n",
2151 		     yesno(rssconf & F_UPDVLD));
2152 	printf("  Xoff:          %3s\n",
2153 		     yesno(rssconf & F_XOFF));
2154 	printf("  UpdChn3:       %3s\n",
2155 		     yesno(rssconf & F_UPDCHN3));
2156 	printf("  UpdChn2:       %3s\n",
2157 		     yesno(rssconf & F_UPDCHN2));
2158 	printf("  UpdChn1:       %3s\n",
2159 		     yesno(rssconf & F_UPDCHN1));
2160 	printf("  UpdChn0:       %3s\n",
2161 		     yesno(rssconf & F_UPDCHN0));
2162 	printf("  Queue:         %3d\n",
2163 		     G_QUEUE(rssconf));
2164 
2165 	return rc;
2166 }
2167 
2168 int
view_rss_key(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2169 view_rss_key(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2170 	     struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2171 {
2172 	struct cudbg_buffer c_buff, dc_buff;
2173 	int rc = 0;
2174 	u32 *key;
2175 
2176 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2177 	if (rc)
2178 		return rc;
2179 
2180 	key = (u32 *)dc_buff.data;
2181 	printf(
2182 		     "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
2183 		     key[9], key[8], key[7], key[6], key[5], key[4],
2184 		     key[3], key[2], key[1], key[0]);
2185 
2186 	return rc;
2187 }
2188 
2189 int
view_rss_vf_config(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2190 view_rss_vf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2191 		   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2192 {
2193 	struct cudbg_buffer c_buff, dc_buff;
2194 	struct rss_vf_conf *vfconf;
2195 	int i, rc = 0;
2196 
2197 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2198 	if (rc)
2199 		return rc;
2200 
2201 	vfconf = (struct rss_vf_conf *) dc_buff.data;
2202 	printf("     RSS                     Hash "\
2203 		     "Tuple Enable\n");
2204 	printf("     Enable   IVF  Dis  Enb  IPv6 "\
2205 		     "     IPv4      UDP    Def  Secret Key\n");
2206 	printf(" VF  Chn Prt  Map  VLAN  uP  Four "\
2207 		     "Two  Four Two  Four   Que  Idx       Hash\n");
2208 	for (i = 0; i < dc_buff.offset/sizeof(*vfconf); i += 1) {
2209 		printf("%3d  %3s %3s  %3d   %3s %3s"\
2210 			     "   %3s %3s   %3s %3s   %3s  %4d  %3d %#10x\n",
2211 			     i, yesno(vfconf->rss_vf_vfh & F_VFCHNEN),
2212 			     yesno(vfconf->rss_vf_vfh & F_VFPRTEN),
2213 			     G_VFLKPIDX(vfconf->rss_vf_vfh),
2214 			     yesno(vfconf->rss_vf_vfh & F_VFVLNEX),
2215 			     yesno(vfconf->rss_vf_vfh & F_VFUPEN),
2216 			     yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN),
2217 			     yesno(vfconf->rss_vf_vfh & F_VFIP6TWOTUPEN),
2218 			     yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN),
2219 			     yesno(vfconf->rss_vf_vfh & F_VFIP4TWOTUPEN),
2220 			     yesno(vfconf->rss_vf_vfh & F_ENABLEUDPHASH),
2221 			     G_DEFAULTQUEUE(vfconf->rss_vf_vfh),
2222 			     G_KEYINDEX(vfconf->rss_vf_vfh),
2223 			     vfconf->rss_vf_vfl);
2224 
2225 		vfconf++;
2226 	}
2227 
2228 	return rc;
2229 }
2230 
2231 int
view_rss_pf_config(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2232 view_rss_pf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2233 		   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2234 {
2235 	struct cudbg_buffer c_buff, dc_buff;
2236 	struct rss_pf_conf *pfconf;
2237 	int i, rc = 0;
2238 
2239 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2240 	if (rc)
2241 		return rc;
2242 
2243 	pfconf = (struct rss_pf_conf *) dc_buff.data;
2244 	printf("PF Map Index Size = %d\n\n",
2245 		     G_LKPIDXSIZE(pfconf->rss_pf_map));
2246 	printf("     RSS              PF   VF    "\
2247 		     "Hash Tuple Enable         Default\n");
2248 	printf("     Enable       IPF Mask Mask  "\
2249 		     "IPv6      IPv4      UDP   Queue\n");
2250 	printf(" PF  Map Chn Prt  Map Size Size  "\
2251 		     "Four Two  Four Two  Four  Ch1  Ch0\n");
2252 
2253 #define G_PFnLKPIDX(map, n) \
2254 	(((map) >> S_PF1LKPIDX*(n)) & M_PF0LKPIDX)
2255 #define G_PFnMSKSIZE(mask, n) \
2256 	(((mask) >> S_PF1MSKSIZE*(n)) & M_PF1MSKSIZE)
2257 
2258 	for (i = 0; i < dc_buff.offset/sizeof(*pfconf); i += 1) {
2259 		printf("%3d  %3s %3s %3s  %3d  %3d"\
2260 			     "  %3d   %3s %3s   %3s %3s   %3s  %3d  %3d\n",
2261 			     i, yesno(pfconf->rss_pf_config & F_MAPENABLE),
2262 			     yesno(pfconf->rss_pf_config & F_CHNENABLE),
2263 			     yesno(pfconf->rss_pf_config & F_PRTENABLE),
2264 			     G_PFnLKPIDX(pfconf->rss_pf_map, i),
2265 			     G_PFnMSKSIZE(pfconf->rss_pf_mask, i),
2266 			     G_IVFWIDTH(pfconf->rss_pf_config),
2267 			     yesno(pfconf->rss_pf_config & F_IP6FOURTUPEN),
2268 			     yesno(pfconf->rss_pf_config & F_IP6TWOTUPEN),
2269 			     yesno(pfconf->rss_pf_config & F_IP4FOURTUPEN),
2270 			     yesno(pfconf->rss_pf_config & F_IP4TWOTUPEN),
2271 			     yesno(pfconf->rss_pf_config & F_UDPFOURTUPEN),
2272 			     G_CH1DEFAULTQUEUE(pfconf->rss_pf_config),
2273 			     G_CH0DEFAULTQUEUE(pfconf->rss_pf_config));
2274 
2275 		pfconf++;
2276 	}
2277 #undef G_PFnLKPIDX
2278 #undef G_PFnMSKSIZE
2279 
2280 	return rc;
2281 }
2282 
2283 int
view_rss(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2284 view_rss(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2285 	 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2286 {
2287 	struct cudbg_buffer c_buff, dc_buff;
2288 	u16 *pdata = NULL;
2289 	int rc = 0;
2290 	u32 i;
2291 
2292 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2293 	if (rc)
2294 		return rc;
2295 
2296 	pdata = (u16 *) dc_buff.data;
2297 	for (i = 0; i < dc_buff.offset / 2; i += 8) {
2298 		printf("%4d:  %4u  %4u  %4u  %4u  "\
2299 			     "%4u  %4u  %4u  %4u\n",
2300 			     i, pdata[i + 0], pdata[i + 1], pdata[i + 2],
2301 			     pdata[i + 3], pdata[i + 4], pdata[i + 5],
2302 			     pdata[i + 6], pdata[i + 7]);
2303 	}
2304 
2305 	return rc;
2306 }
2307 
2308 int
view_fw_devlog(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2309 view_fw_devlog(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2310 	       struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2311 {
2312 	struct cudbg_buffer c_buff, dc_buff;
2313 	struct fw_devlog_e *e, *devlog;
2314 	unsigned long index;
2315 	u32 num_entries = 0;
2316 	u32 first_entry = 0;
2317 	int rc = 0;
2318 	u32 itr;
2319 
2320 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2321 	if (rc)
2322 		return rc;
2323 
2324 	translate_fw_devlog(dc_buff.data, dc_buff.offset,
2325 			&num_entries, &first_entry);
2326 
2327 	devlog = (struct fw_devlog_e *)(dc_buff.data);
2328 	printf("%10s  %15s  %8s  %8s  %s\n",
2329 		     "Seq#", "Tstamp", "Level", "Facility", "Message");
2330 
2331 	index = first_entry;
2332 	for (itr = 0; itr < num_entries; itr++) {
2333 		if (index >= num_entries)
2334 			index = 0;
2335 
2336 		e = &devlog[index++];
2337 		if (e->timestamp == 0)
2338 			break;
2339 		printf("%10d  %15llu  %8s  %8s  ",
2340 			     e->seqno, e->timestamp,
2341 			     (e->level < ARRAY_SIZE(devlog_level_strings)
2342 			      ? devlog_level_strings[e->level] : "UNKNOWN"),
2343 			     (e->facility < ARRAY_SIZE(devlog_facility_strings)
2344 			      ? devlog_facility_strings[e->facility]
2345 			      : "UNKNOWN"));
2346 		printf((const char *)e->fmt,
2347 			     e->params[0], e->params[1], e->params[2],
2348 			     e->params[3], e->params[4], e->params[5],
2349 			     e->params[6], e->params[7]);
2350 	}
2351 
2352 	return rc;
2353 }
2354 
2355 void
translate_fw_devlog(void * pbuf,u32 io_size,u32 * num_entries,u32 * first_entry)2356 translate_fw_devlog(void *pbuf, u32 io_size,
2357 		    u32 *num_entries, u32 *first_entry)
2358 {
2359 	struct fw_devlog_e *e = NULL;
2360 	u64 ftstamp;
2361 	u32 index;
2362 
2363 	*num_entries = (io_size / sizeof(struct fw_devlog_e));
2364 	*first_entry = 0;
2365 	e = (struct fw_devlog_e *)pbuf;
2366 	for (ftstamp = ~0ULL, index = 0; index < *num_entries; index++) {
2367 		int i;
2368 
2369 		if (e->timestamp == 0)
2370 			continue;
2371 
2372 		e->timestamp = ntohll(e->timestamp);
2373 		e->seqno = ntohl(e->seqno);
2374 		for (i = 0; i < 8; i++)
2375 			e->params[i] = ntohl(e->params[i]);
2376 
2377 		if (e->timestamp < ftstamp) {
2378 			ftstamp = e->timestamp;
2379 			*first_entry = index;
2380 		}
2381 
2382 		e++;
2383 	}
2384 }
2385 
2386 /* Regdump function */
2387 static uint32_t
xtract(uint32_t val,int shift,int len)2388 xtract(uint32_t val, int shift, int len)
2389 {
2390 	return (val >> shift) & ((1L << len) - 1);
2391 }
2392 
2393 static int
dump_block_regs(const struct reg_info * reg_array,const u32 * regs,struct cudbg_buffer * cudbg_poutbuf)2394 dump_block_regs(const struct reg_info *reg_array, const u32 *regs,
2395 		struct cudbg_buffer *cudbg_poutbuf)
2396 {
2397 	uint32_t reg_val = 0; /* silence compiler warning*/
2398 	int rc = 0;
2399 
2400 	for (; reg_array->name; ++reg_array) {
2401 		if (!reg_array->len) {
2402 			reg_val = regs[reg_array->addr / 4];
2403 			printf("[%#7x] %-47s %#-10x"\
2404 				     " %u\n", reg_array->addr, reg_array->name,
2405 				     reg_val, reg_val);
2406 		} else {
2407 			uint32_t v = xtract(reg_val, reg_array->addr,
2408 					    reg_array->len);
2409 
2410 			printf("    %*u:%u %-47s "\
2411 				     "%#-10x %u\n",
2412 				     reg_array->addr < 10 ? 3 : 2,
2413 				     reg_array->addr + reg_array->len - 1,
2414 				     reg_array->addr, reg_array->name, v, v);
2415 		}
2416 	}
2417 
2418 	return 1;
2419 
2420 	return rc;
2421 }
2422 
2423 static int
dump_regs_table(const u32 * regs,const struct mod_regs * modtab,int nmodules,const char * modnames,struct cudbg_buffer * cudbg_poutbuf)2424 dump_regs_table(const u32 *regs, const struct mod_regs *modtab,
2425 		int nmodules, const char *modnames,
2426 		struct cudbg_buffer *cudbg_poutbuf)
2427 {
2428 	int match = 0;
2429 	int rc = 0;
2430 
2431 	for (; nmodules; nmodules--, modtab++) {
2432 		rc = dump_block_regs(modtab->ri,
2433 				     regs + modtab->offset, cudbg_poutbuf);
2434 		if (rc < 0)
2435 			goto err1;
2436 		match += rc;
2437 	}
2438 
2439 err1:
2440 	return rc;
2441 }
2442 
2443 #define T6_MODREGS(name) { #name, t6_##name##_regs }
2444 static int
dump_regs_t6(const u32 * regs,struct cudbg_buffer * cudbg_poutbuf)2445 dump_regs_t6(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf)
2446 {
2447 	static struct mod_regs t6_mod[] = {
2448 		T6_MODREGS(sge),
2449 		{ "pci", t6_pcie_regs },
2450 		T6_MODREGS(dbg),
2451 		{ "mc0", t6_mc_0_regs },
2452 		T6_MODREGS(ma),
2453 		{ "edc0", t6_edc_t60_regs },
2454 		{ "edc1", t6_edc_t61_regs },
2455 		T6_MODREGS(cim),
2456 		T6_MODREGS(tp),
2457 		{ "ulprx", t6_ulp_rx_regs },
2458 		{ "ulptx", t6_ulp_tx_regs },
2459 		{ "pmrx", t6_pm_rx_regs },
2460 		{ "pmtx", t6_pm_tx_regs },
2461 		T6_MODREGS(mps),
2462 		{ "cplsw", t6_cpl_switch_regs },
2463 		T6_MODREGS(smb),
2464 		{ "i2c", t6_i2cm_regs },
2465 		T6_MODREGS(mi),
2466 		T6_MODREGS(uart),
2467 		T6_MODREGS(pmu),
2468 		T6_MODREGS(sf),
2469 		T6_MODREGS(pl),
2470 		T6_MODREGS(le),
2471 		T6_MODREGS(ncsi),
2472 		T6_MODREGS(mac),
2473 		{ "hma", t6_hma_t6_regs }
2474 	};
2475 
2476 	return dump_regs_table(regs, t6_mod,
2477 			ARRAY_SIZE(t6_mod),
2478 			"sge, pci, dbg, mc0, ma, edc0, edc1, cim, "\
2479 			"tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\
2480 			"i2c, mi, uart, pmu, sf, pl, le, ncsi, "\
2481 			"mac, hma", cudbg_poutbuf);
2482 }
2483 #undef T6_MODREGS
2484 
2485 #define T5_MODREGS(name) { #name, t5_##name##_regs }
2486 
2487 static int
dump_regs_t5(const u32 * regs,struct cudbg_buffer * cudbg_poutbuf)2488 dump_regs_t5(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf)
2489 {
2490 	static struct mod_regs t5_mod[] = {
2491 		T5_MODREGS(sge),
2492 		{ "pci", t5_pcie_regs },
2493 		T5_MODREGS(dbg),
2494 		{ "mc0", t5_mc_0_regs },
2495 		{ "mc1", t5_mc_1_regs },
2496 		T5_MODREGS(ma),
2497 		{ "edc0", t5_edc_t50_regs },
2498 		{ "edc1", t5_edc_t51_regs },
2499 		T5_MODREGS(cim),
2500 		T5_MODREGS(tp),
2501 		{ "ulprx", t5_ulp_rx_regs },
2502 		{ "ulptx", t5_ulp_tx_regs },
2503 		{ "pmrx", t5_pm_rx_regs },
2504 		{ "pmtx", t5_pm_tx_regs },
2505 		T5_MODREGS(mps),
2506 		{ "cplsw", t5_cpl_switch_regs },
2507 		T5_MODREGS(smb),
2508 		{ "i2c", t5_i2cm_regs },
2509 		T5_MODREGS(mi),
2510 		T5_MODREGS(uart),
2511 		T5_MODREGS(pmu),
2512 		T5_MODREGS(sf),
2513 		T5_MODREGS(pl),
2514 		T5_MODREGS(le),
2515 		T5_MODREGS(ncsi),
2516 		T5_MODREGS(mac),
2517 		{ "hma", t5_hma_t5_regs }
2518 	};
2519 
2520 	return dump_regs_table(regs, t5_mod,
2521 			ARRAY_SIZE(t5_mod),
2522 			"sge, pci, dbg, mc0, mc1, ma, edc0, edc1, cim, "\
2523 			"tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\
2524 			"i2c, mi, uart, pmu, sf, pl, le, ncsi, "\
2525 			"mac, hma", cudbg_poutbuf);
2526 }
2527 #undef T5_MODREGS
2528 
2529 int
view_reg_dump(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)2530 view_reg_dump(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2531 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
2532 {
2533 	struct cudbg_buffer c_buff, dc_buff;
2534 	int rc = 0;
2535 	u32 *regs;
2536 
2537 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2538 	if (rc)
2539 		return rc;
2540 
2541 	regs = (u32 *) ((unsigned int *)dc_buff.data);
2542 	if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
2543 		rc =  dump_regs_t5((u32 *)regs, cudbg_poutbuf);
2544 	else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
2545 		rc = dump_regs_t6((u32 *)regs, cudbg_poutbuf);
2546 	return rc;
2547 }
2548 
2549 static int
t6_view_wtp(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)2550 t6_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
2551 	    struct cudbg_buffer *cudbg_poutbuf)
2552 {
2553 	struct cudbg_buffer c_buff, dc_buff;
2554 	struct wtp_data *wtp = NULL;
2555 	int rc = 0;
2556 	int i = 0;
2557 	/****Rx****/
2558 	u32 pcie_core_dmaw_sop = 0;
2559 	u32 sge_pcie_sop = 0;
2560 	u32 csw_sge_sop = 0;
2561 	u32 tp_csw_sop = 0;
2562 	u32 tpcside_csw_sop = 0;
2563 	u32 ulprx_tpcside_sop = 0;
2564 	u32 pmrx_ulprx_sop = 0;
2565 	u32 mps_tpeside_sop = 0;
2566 	u32 mps_tp_sop = 0;
2567 	u32 xgm_mps_sop = 0;
2568 	u32 rx_xgm_xgm_sop = 0;
2569 	u32 wire_xgm_sop = 0;
2570 	u32 rx_wire_macok_sop = 0;
2571 
2572 	u32 pcie_core_dmaw_eop = 0;
2573 	u32 sge_pcie_eop = 0;
2574 	u32 csw_sge_eop = 0;
2575 	u32 tp_csw_eop = 0;
2576 	u32 tpcside_csw_eop = 0;
2577 	u32 ulprx_tpcside_eop = 0;
2578 	u32 pmrx_ulprx_eop = 0;
2579 	u32 mps_tpeside_eop = 0;
2580 	u32 mps_tp_eop = 0;
2581 	u32 xgm_mps_eop = 0;
2582 	u32 rx_xgm_xgm_eop = 0;
2583 	u32 wire_xgm_eop = 0;
2584 	u32 rx_wire_macok_eop = 0;
2585 
2586 	/****Tx****/
2587 	u32 core_pcie_dma_rsp_sop = 0;
2588 	u32 pcie_sge_dma_rsp_sop = 0;
2589 	u32 sge_debug_index6_sop = 0;
2590 	u32 sge_utx_sop = 0;
2591 	u32 utx_tp_sop = 0;
2592 	u32 sge_work_req_sop = 0;
2593 	u32 utx_tpcside_sop = 0;
2594 	u32 tpcside_rxarb_sop = 0;
2595 	u32 tpeside_mps_sop = 0;
2596 	u32 tp_mps_sop = 0;
2597 	u32 mps_xgm_sop = 0;
2598 	u32 tx_xgm_xgm_sop = 0;
2599 	u32 xgm_wire_sop = 0;
2600 	u32 tx_macok_wire_sop = 0;
2601 
2602 	u32 core_pcie_dma_rsp_eop = 0;
2603 	u32 pcie_sge_dma_rsp_eop = 0;
2604 	u32 sge_debug_index6_eop = 0;
2605 	u32 sge_utx_eop = 0;
2606 	u32 utx_tp_eop = 0;
2607 	u32 utx_tpcside_eop = 0;
2608 	u32 tpcside_rxarb_eop = 0;
2609 	u32 tpeside_mps_eop = 0;
2610 	u32 tp_mps_eop = 0;
2611 	u32 mps_xgm_eop = 0;
2612 	u32 tx_xgm_xgm_eop = 0;
2613 	u32 xgm_wire_eop = 0;
2614 	u32 tx_macok_wire_eop = 0;
2615 
2616 	u32 pcie_core_cmd_req_sop = 0;
2617 	u32 sge_pcie_cmd_req_sop = 0;
2618 	u32 core_pcie_cmd_rsp_sop = 0;
2619 	u32 pcie_sge_cmd_rsp_sop = 0;
2620 	u32 sge_cim_sop = 0;
2621 	u32 pcie_core_dma_req_sop = 0;
2622 	u32 sge_pcie_dma_req_sop = 0;
2623 	u32 utx_sge_dma_req_sop = 0;
2624 
2625 	u32 sge_pcie_cmd_req_eop = 0;
2626 	u32 pcie_core_cmd_req_eop = 0;
2627 	u32 core_pcie_cmd_rsp_eop = 0;
2628 	u32 pcie_sge_cmd_rsp_eop = 0;
2629 	u32 sge_cim_eop = 0;
2630 	u32 pcie_core_dma_req_eop = 0;
2631 	u32 sge_pcie_dma_req_eop = 0;
2632 	u32 utx_sge_dma_req_eop = 0;
2633 
2634 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
2635 	if (rc)
2636 		return rc;
2637 
2638 	wtp = (struct wtp_data *) dc_buff.data;
2639 	/*Add up the sop/eop of all channels.*/
2640 	for (i = 0; i < 8; i++) {
2641 		if (i < 2) {
2642 			/*Rx Path*/
2643 			csw_sge_sop           +=
2644 				(wtp->sge_debug_data_high_indx1.sop[i]);
2645 			tp_csw_sop            +=
2646 				(wtp->sge_debug_data_high_indx9.sop[i]);
2647 
2648 			csw_sge_eop           += (wtp->csw_sge.eop[i]);
2649 			tp_csw_eop            += (wtp->tp_csw.eop[i]);
2650 			rx_wire_macok_sop     +=
2651 				wtp->mac_porrx_etherstatspkts.sop[i];
2652 			rx_wire_macok_eop     +=
2653 				wtp->mac_porrx_etherstatspkts.eop[i];
2654 
2655 			/*Tx Path*/
2656 			sge_pcie_cmd_req_sop  += wtp->sge_pcie_cmd_req.sop[i];
2657 			pcie_sge_cmd_rsp_sop  += wtp->pcie_sge_cmd_rsp.sop[i];
2658 			sge_cim_sop           += wtp->sge_cim.sop[i];
2659 			tpcside_csw_sop       += (wtp->utx_tpcside_tx.sop[i]);
2660 			sge_work_req_sop      += wtp->sge_work_req_pkt.sop[i];
2661 			tx_macok_wire_sop     +=
2662 				wtp->mac_portx_etherstatspkts.sop[i];
2663 			tx_macok_wire_eop     +=
2664 				wtp->mac_portx_etherstatspkts.eop[i];
2665 
2666 			sge_pcie_cmd_req_eop  += wtp->sge_pcie_cmd_req.eop[i];
2667 			pcie_sge_cmd_rsp_eop  += wtp->pcie_sge_cmd_rsp.eop[i];
2668 			sge_cim_eop           += wtp->sge_cim.eop[i];
2669 
2670 		}
2671 
2672 		if (i < 3) {
2673 			pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i];
2674 			core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i];
2675 
2676 			core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i];
2677 			pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i];
2678 		}
2679 
2680 		if (i < 4) {
2681 			/*Rx Path*/
2682 			pcie_core_dmaw_sop    +=
2683 				(wtp->pcie_dma1_stat2.sop[i]);
2684 			sge_pcie_sop          +=
2685 				(wtp->sge_debug_data_high_indx7.sop[i]);
2686 			ulprx_tpcside_sop     += (wtp->ulprx_tpcside.sop[i]);
2687 			pmrx_ulprx_sop        += (wtp->pmrx_ulprx.sop[i]);
2688 			mps_tpeside_sop       +=
2689 				(wtp->tp_dbg_eside_pktx.sop[i]);
2690 			rx_xgm_xgm_sop        +=
2691 				(wtp->mac_porrx_pkt_count.sop[i]);
2692 			wire_xgm_sop          +=
2693 				(wtp->mac_porrx_aframestra_ok.sop[i]);
2694 
2695 			pcie_core_dmaw_eop    +=
2696 				(wtp->pcie_dma1_stat2.eop[i]);
2697 			sge_pcie_eop          += (wtp->sge_pcie.eop[i]);
2698 			tpcside_csw_eop       += (wtp->tpcside_csw.eop[i]);
2699 			ulprx_tpcside_eop     += (wtp->ulprx_tpcside.eop[i]);
2700 			pmrx_ulprx_eop        += (wtp->pmrx_ulprx.eop[i]);
2701 			mps_tpeside_eop       += (wtp->mps_tpeside.eop[i]);
2702 			rx_xgm_xgm_eop        +=
2703 				(wtp->mac_porrx_pkt_count.eop[i]);
2704 			wire_xgm_eop          +=
2705 				(wtp->mac_porrx_aframestra_ok.eop[i]);
2706 
2707 			/*special case type 3:*/
2708 			mps_tp_sop            += (wtp->mps_tp.sop[i]);
2709 			mps_tp_eop            += (wtp->mps_tp.eop[i]);
2710 
2711 			/*Tx Path*/
2712 			core_pcie_dma_rsp_sop +=
2713 				wtp->pcie_t5_dma_stat3.sop[i];
2714 			pcie_sge_dma_rsp_sop  += wtp->pcie_sge_dma_rsp.sop[i];
2715 			sge_debug_index6_sop  +=
2716 				wtp->sge_debug_data_high_index_6.sop[i];
2717 			sge_utx_sop           += wtp->ulp_se_cnt_chx.sop[i];
2718 			utx_tp_sop            += wtp->utx_tp.sop[i];
2719 			utx_tpcside_sop       += wtp->utx_tpcside.sop[i];
2720 			tpcside_rxarb_sop     += wtp->tpcside_rxarb.sop[i];
2721 			tpeside_mps_sop       += wtp->tpeside_mps.sop[i];
2722 			tx_xgm_xgm_sop        +=
2723 				wtp->mac_portx_pkt_count.sop[i];
2724 			xgm_wire_sop          +=
2725 				wtp->mac_portx_aframestra_ok.sop[i];
2726 
2727 			core_pcie_dma_rsp_eop +=
2728 				wtp->pcie_t5_dma_stat3.eop[i];
2729 			pcie_sge_dma_rsp_eop  += wtp->pcie_sge_dma_rsp.eop[i];
2730 			sge_debug_index6_eop  +=
2731 				wtp->sge_debug_data_high_index_6.eop[i];
2732 			sge_utx_eop           += wtp->sge_utx.eop[i];
2733 			utx_tp_eop            += wtp->utx_tp.eop[i];
2734 			utx_tpcside_eop       += wtp->utx_tpcside.eop[i];
2735 			tpcside_rxarb_eop     += wtp->tpcside_rxarb.eop[i];
2736 			tpeside_mps_eop       += wtp->tpeside_mps.eop[i];
2737 			tx_xgm_xgm_eop        +=
2738 				wtp->mac_portx_pkt_count.eop[i];
2739 			xgm_wire_eop          +=
2740 				wtp->mac_portx_aframestra_ok.eop[i];
2741 
2742 			/*special case type 3:*/
2743 			tp_mps_sop            += wtp->tp_mps.sop[i];
2744 			mps_xgm_sop           += wtp->mps_xgm.sop[i];
2745 
2746 			tp_mps_eop            += wtp->tp_mps.eop[i];
2747 			mps_xgm_eop           += wtp->mps_xgm.eop[i];
2748 
2749 			pcie_core_dma_req_sop +=
2750 				wtp->pcie_dma1_stat2_core.sop[i];
2751 			sge_pcie_dma_req_sop  +=
2752 				wtp->sge_debug_data_high_indx5.sop[i];
2753 			utx_sge_dma_req_sop   += wtp->utx_sge_dma_req.sop[i];
2754 
2755 			pcie_core_dma_req_eop +=
2756 				wtp->pcie_dma1_stat2_core.eop[i];
2757 			sge_pcie_dma_req_eop  +=
2758 				wtp->sge_debug_data_high_indx5.eop[i];
2759 			utx_sge_dma_req_eop   += wtp->utx_sge_dma_req.eop[i];
2760 		}
2761 
2762 		if (i < 5) {
2763 			xgm_mps_sop               += (wtp->xgm_mps.sop[i]);
2764 			xgm_mps_eop               += (wtp->xgm_mps.eop[i]);
2765 		}
2766 	}
2767 	printf("ifaces = nic0 nic1\n");
2768 	printf("*************************EGGRESS (TX) PATH **********************************\n");
2769 	printf("MOD :  core---->PCIE---->SGE<-|    #Ring Doorbell\n");
2770 	printf("SOP        ?      ???         |\n");
2771 	printf("EOP        ?      ???         |\n");
2772 	printf("MOD |<-core<----PCIE<----SGE<-|    #Request Work Request\n");
2773 	printf("SOP_CH0  %02X       %02x\n",
2774 		     wtp->pcie_cmd_stat2.sop[0], wtp->sge_pcie_cmd_req.sop[0]);
2775 	printf("SOP |    %02X       %02X\n",
2776 		     pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop);
2777 	printf("EOP |    %2X       %2X\n",
2778 		     pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop);
2779 	printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n");
2780 	printf("SOP_CH0  %02X       %02X      %02X"\
2781 		     "               |      %2X\n",
2782 		     wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[1],
2783 		     wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]);
2784 
2785 	printf("SOP_CH1                   %02X"\
2786 		     "               |\n", wtp->pcie_sge_cmd_rsp.sop[1]);
2787 	printf("SOP      %02X       %02X      %2X"\
2788 		     "               |      %2X\n", core_pcie_cmd_rsp_sop,
2789 		     pcie_sge_cmd_rsp_sop, sge_cim_sop, sge_work_req_sop);
2790 	printf("EOP      %2X       %2X      %2X"\
2791 		     "               |\n", core_pcie_cmd_rsp_eop,
2792 		     pcie_sge_cmd_rsp_eop, sge_cim_eop);
2793 	printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n");
2794 	printf("SOP_CH0  %02X\n",
2795 		     wtp->pcie_dma1_stat2_core.sop[0]);
2796 	printf("SOP_CH1  %02X\n",
2797 		     wtp->pcie_dma1_stat2_core.sop[1]);
2798 	printf("SOP |    %2X\n",
2799 		     pcie_core_dma_req_sop);
2800 	printf("EOP |    %2X\n",
2801 		     pcie_core_dma_req_eop);
2802 
2803 	printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->MACOK->wire\n");
2804 	printf("SOP_CH0        %02X         %2X   "\
2805 		     "   %2X       %2X    %2X   %02X  %02X  %02X      %02X   "\
2806 		     " %02X\n",
2807 		     wtp->pcie_t5_dma_stat3.sop[0], wtp->ulp_se_cnt_chx.sop[0],
2808 		     wtp->utx_tpcside.sop[0], wtp->tpcside_rxarb.sop[0],
2809 		     wtp->tpeside_mps.sop[0], wtp->tp_mps.sop[0],
2810 		     wtp->mps_xgm.sop[0], wtp->mac_portx_pkt_count.sop[0],
2811 		     wtp->mac_portx_aframestra_ok.sop[0],
2812 		     wtp->mac_portx_etherstatspkts.sop[0]);
2813 
2814 	printf("EOP_CH0        %02X         %2X  "\
2815 		     "    %2X       %2X    %2X   %02X  %02X  %02X      %02X"\
2816 		     "    %02X\n",
2817 		     wtp->pcie_t5_dma_stat3.eop[0], wtp->ulp_se_cnt_chx.eop[0],
2818 		     wtp->utx_tpcside.eop[0], wtp->tpcside_rxarb.eop[0],
2819 		     wtp->tpeside_mps.eop[0], wtp->tp_mps.eop[0],
2820 		     wtp->mps_xgm.eop[0], wtp->mac_portx_pkt_count.eop[0],
2821 		     wtp->mac_portx_aframestra_ok.eop[0],
2822 		     wtp->mac_portx_etherstatspkts.eop[0]);
2823 	printf("SOP_CH1        %02X         %2X   "\
2824 		     "   %2X       %2X    %2X   %02X  %02X  %02X      %02X  "\
2825 		     "%02X\n",
2826 		     wtp->pcie_t5_dma_stat3.sop[1], wtp->ulp_se_cnt_chx.sop[1],
2827 		     wtp->utx_tpcside.sop[1], wtp->tpcside_rxarb.sop[1],
2828 		     wtp->tpeside_mps.sop[1], wtp->tp_mps.sop[1],
2829 		     wtp->mps_xgm.sop[1], wtp->mac_portx_pkt_count.sop[1],
2830 		     wtp->mac_portx_aframestra_ok.sop[1],
2831 		     wtp->mac_portx_etherstatspkts.sop[1]);
2832 
2833 	printf("EOP_CH1        %02X         %2X   "\
2834 		     "   %2X       %2X    %2X   %02X  %02X  %02X      %02X"\
2835 		     "    %02X\n",
2836 		     wtp->pcie_t5_dma_stat3.eop[1], wtp->ulp_se_cnt_chx.eop[1],
2837 		     wtp->utx_tpcside.eop[1], wtp->tpcside_rxarb.eop[1],
2838 		     wtp->tpeside_mps.eop[1], wtp->tp_mps.eop[1],
2839 		     wtp->mps_xgm.eop[1], wtp->mac_portx_pkt_count.eop[1],
2840 		     wtp->mac_portx_aframestra_ok.eop[1],
2841 		     wtp->mac_portx_etherstatspkts.eop[1]);
2842 	printf("SOP_CH2        %02X         %2X   "\
2843 		     "   %2X       %2X    %2X   %02X  %02X\n",
2844 		     wtp->pcie_t5_dma_stat3.sop[2], wtp->ulp_se_cnt_chx.sop[2],
2845 		     wtp->utx_tpcside.sop[2], wtp->tpcside_rxarb.sop[2],
2846 		     wtp->tpeside_mps.sop[2], wtp->tp_mps.sop[2],
2847 		     wtp->mps_xgm.sop[2]);
2848 
2849 	printf("EOP_CH2        %02X         %2X   "\
2850 		     "   %2X       %2X    %2X   %02X  %02X\n",
2851 		     wtp->pcie_t5_dma_stat3.eop[2], wtp->ulp_se_cnt_chx.eop[2],
2852 		     wtp->utx_tpcside.eop[2], wtp->tpcside_rxarb.eop[2],
2853 		     wtp->tpeside_mps.eop[2], wtp->tp_mps.eop[2],
2854 		     wtp->mps_xgm.eop[2]);
2855 	printf("SOP_CH3        %02X         %2X  "\
2856 		     "    %2X       %2X    %2X   %02X  %02X\n",
2857 		     wtp->pcie_t5_dma_stat3.sop[3], wtp->ulp_se_cnt_chx.sop[3],
2858 		     wtp->utx_tpcside.sop[3], wtp->tpcside_rxarb.sop[3],
2859 		     wtp->tpeside_mps.sop[3], wtp->tp_mps.sop[3],
2860 		     wtp->mps_xgm.sop[3]);
2861 
2862 	printf("EOP_CH3        %02X         %2X   "\
2863 		     "   %2X       %2X    %2X   %02X  %02X\n",
2864 		     wtp->pcie_t5_dma_stat3.eop[3], wtp->ulp_se_cnt_chx.eop[3],
2865 		     wtp->utx_tpcside.eop[3], wtp->tpcside_rxarb.eop[3],
2866 		     wtp->tpeside_mps.eop[3], wtp->tp_mps.eop[3],
2867 		     wtp->mps_xgm.eop[3]);
2868 	printf("SOP            %2X         %2X    "\
2869 		     "  %2X       %2X    %2X   %2X  %2X  %2X      %2X    %2X\n",
2870 		     core_pcie_dma_rsp_sop, sge_utx_sop, utx_tp_sop,
2871 		     tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop,
2872 		     mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop,
2873 		     tx_macok_wire_sop);
2874 	printf("EOP            %2X         %2X   "\
2875 			"   %2X       %2X    %2X   %2X  %2X  %2X      %2X  "\
2876 			"  %2X\n",
2877 			core_pcie_dma_rsp_eop, sge_utx_eop, utx_tp_eop,
2878 			tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop,
2879 			mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop,
2880 			tx_macok_wire_eop);
2881 	printf("*************************INGRESS (RX) PATH **********************************\n");
2882 
2883 	printf("MOD   core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<-MACOK<--wire\n");
2884 
2885 	printf("SOP_CH0      %2X  %2X    %2X    %2X"\
2886 		     "   %2X  %2X  %2X %2X  %2X    %2X   %02X  %02X     "\
2887 		     " %02X    %02X\n",
2888 		     wtp->pcie_dma1_stat2.sop[0],
2889 		     wtp->sge_debug_data_high_indx7.sop[0],
2890 		     wtp->sge_debug_data_high_indx1.sop[0],
2891 		     wtp->sge_debug_data_high_indx9.sop[0],
2892 		     wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0],
2893 		     wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop,
2894 		     wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0],
2895 		     wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0],
2896 		     wtp->mac_porrx_aframestra_ok.sop[0],
2897 		     wtp->mac_porrx_etherstatspkts.sop[0]);
2898 
2899 	printf("EOP_CH0      %2X  %2X    %2X    "\
2900 		     "%2X   %2X  %2X  %2X %2X  %2X    %2X   %02X  %02X   "\
2901 		     "   %02X    %02X\n",
2902 		     wtp->pcie_dma1_stat2.eop[0],
2903 		     wtp->sge_debug_data_high_indx7.eop[0],
2904 		     wtp->sge_debug_data_high_indx1.eop[0],
2905 		     wtp->sge_debug_data_high_indx9.eop[0],
2906 		     wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0],
2907 		     wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop,
2908 		     wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0],
2909 		     wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0],
2910 		     wtp->mac_porrx_aframestra_ok.eop[0],
2911 		     wtp->mac_porrx_etherstatspkts.eop[0]);
2912 	printf("SOP_CH1      %2X  %2X    %2X   "\
2913 		     " %2X   %2X  %2X  %2X     %2X    %2X   %02X  %02X  "\
2914 		     "    %02X    %02X\n",
2915 		     wtp->pcie_dma1_stat2.sop[1],
2916 		     wtp->sge_debug_data_high_indx7.sop[1],
2917 		     wtp->sge_debug_data_high_indx1.sop[1],
2918 		     wtp->sge_debug_data_high_indx9.sop[1],
2919 		     wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1],
2920 		     wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1],
2921 		     wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1],
2922 		     wtp->mac_porrx_pkt_count.sop[1],
2923 		     wtp->mac_porrx_aframestra_ok.sop[1],
2924 		     wtp->mac_porrx_etherstatspkts.sop[1]);
2925 
2926 	printf("EOP_CH1      %2X  %2X    %2X    %2X"\
2927 		     "   %2X  %2X  %2X     %2X    %2X   %02X  %02X      "\
2928 		     "%02X    %02X\n",
2929 		     wtp->pcie_dma1_stat2.eop[1],
2930 		     wtp->sge_debug_data_high_indx7.eop[1],
2931 		     wtp->sge_debug_data_high_indx1.eop[1],
2932 		     wtp->sge_debug_data_high_indx9.eop[1],
2933 		     wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1],
2934 		     wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1],
2935 		     wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1],
2936 		     wtp->mac_porrx_pkt_count.eop[1],
2937 		     wtp->mac_porrx_aframestra_ok.eop[1],
2938 		     wtp->mac_porrx_etherstatspkts.eop[1]);
2939 	printf("SOP_CH2                           "\
2940 		     "               %2X         %02X\n",
2941 		     wtp->tp_dbg_eside_pktx.sop[2], wtp->xgm_mps.sop[2]);
2942 
2943 	printf("EOP_CH2                           "\
2944 		     "               %2X         %02X\n",
2945 		     wtp->tp_dbg_eside_pktx.eop[2], wtp->xgm_mps.eop[2]);
2946 	printf("SOP_CH3                           "\
2947 		     "               %2X         %02X\n",
2948 		     wtp->tp_dbg_eside_pktx.sop[3],
2949 		     wtp->xgm_mps.sop[3]);
2950 
2951 	printf("EOP_CH3                           "\
2952 		     "               %2X         %02X\n",
2953 		     wtp->tp_dbg_eside_pktx.eop[3], wtp->xgm_mps.eop[3]);
2954 	printf("SOP_CH4                           "\
2955 		     "                          %02X\n",
2956 		     wtp->xgm_mps.sop[4]);
2957 	printf("EOP_CH4                           "\
2958 		     "                          %02X\n",
2959 		     wtp->xgm_mps.eop[4]);
2960 	printf("SOP_CH5                           "\
2961 		     "                          %02X\n",
2962 		     wtp->xgm_mps.sop[5]);
2963 	printf("EOP_CH5                           "\
2964 		     "                          %02X\n",
2965 		     wtp->xgm_mps.eop[5]);
2966 	printf("SOP_CH6\n");
2967 	printf("EOP_CH6\n");
2968 	printf("SOP_CH7\n");
2969 	printf("EOP_CH7\n");
2970 
2971 	printf("SOP          %2X  %2X    %2X    %2X"\
2972 		     "   %2X  %2X   %2X    %2X    %2X   %2X  %2X      %2X "\
2973 		     "  %2X\n",
2974 		     pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop,
2975 		     tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop,
2976 		     pmrx_ulprx_sop, mps_tpeside_sop,
2977 		     mps_tp_sop, xgm_mps_sop, rx_xgm_xgm_sop,
2978 		     wire_xgm_sop, rx_wire_macok_sop);
2979 	printf("EOP          %2X  %2X    %2X    "\
2980 		     "%2X   %2X  %2X   %2X    %2X    %2X   %2X  %2X     "\
2981 		     " %2X   %2X\n",
2982 		     pcie_core_dmaw_eop, sge_pcie_eop, csw_sge_eop,
2983 		     tp_csw_eop, tpcside_csw_eop, ulprx_tpcside_eop,
2984 		     pmrx_ulprx_eop, mps_tpeside_eop, mps_tp_eop,
2985 		     xgm_mps_eop, rx_xgm_xgm_eop, wire_xgm_eop,
2986 		     rx_wire_macok_eop);
2987 	printf("DROP: ???      ???      ???       "\
2988 		     "%2X(mib)  %2X(err) %2X(oflow) %X(cls)\n",
2989 		     (wtp->mps_tp.drops & 0xFF), (wtp->xgm_mps.err & 0xFF),
2990 		     (wtp->xgm_mps.drop & 0xFF),
2991 		     (wtp->xgm_mps.cls_drop & 0xFF));
2992 	printf("INTS:  ");
2993 	for (i = 0; i < 2; i++) {
2994 		printf("%2X<- %2X    ",
2995 			     (wtp->pcie_core_dmai.sop[i] & 0xF),
2996 			     (wtp->sge_pcie_ints.sop[i] & 0xF));
2997 	}
2998 	printf("(PCIE<-SGE, channels 0 to 1)\n");
2999 
3000 	return rc;
3001 }
3002 
3003 static int
t5_view_wtp(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)3004 t5_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3005 	    struct cudbg_buffer *cudbg_poutbuf)
3006 {
3007 	struct cudbg_buffer c_buff, dc_buff;
3008 	struct wtp_data *wtp = NULL;
3009 	int rc = 0;
3010 	int i = 0;
3011 	/****Rx****/
3012 	u32 pcie_core_dmaw_sop = 0;
3013 	u32 sge_pcie_sop = 0;
3014 	u32 csw_sge_sop = 0;
3015 	u32 tp_csw_sop = 0;
3016 	u32 tpcside_csw_sop = 0;
3017 	u32 ulprx_tpcside_sop = 0;
3018 	u32 pmrx_ulprx_sop = 0;
3019 	u32 mps_tpeside_sop = 0;
3020 	u32 mps_tp_sop = 0;
3021 	u32 xgm_mps_sop = 0;
3022 	u32 rx_xgm_xgm_sop = 0;
3023 	u32 wire_xgm_sop = 0;
3024 
3025 	u32 pcie_core_dmaw_eop = 0;
3026 	u32 sge_pcie_eop = 0;
3027 	u32 csw_sge_eop = 0;
3028 	u32 tp_csw_eop = 0;
3029 	u32 tpcside_csw_eop = 0;
3030 	u32 ulprx_tpcside_eop = 0;
3031 	u32 pmrx_ulprx_eop = 0;
3032 	u32 mps_tpeside_eop = 0;
3033 	u32 mps_tp_eop = 0;
3034 	u32 xgm_mps_eop = 0;
3035 	u32 rx_xgm_xgm_eop = 0;
3036 	u32 wire_xgm_eop = 0;
3037 
3038 	/****Tx****/
3039 	u32 core_pcie_dma_rsp_sop = 0;
3040 	u32 pcie_sge_dma_rsp_sop = 0;
3041 	u32 sge_debug_index6_sop = 0;
3042 	u32 sge_utx_sop = 0;
3043 	u32 utx_tp_sop = 0;
3044 	u32 sge_work_req_sop = 0;
3045 	u32 utx_tpcside_sop = 0;
3046 	u32 tpcside_rxarb_sop = 0;
3047 	u32 tpeside_mps_sop = 0;
3048 	u32 tp_mps_sop = 0;
3049 	u32 mps_xgm_sop = 0;
3050 	u32 tx_xgm_xgm_sop = 0;
3051 	u32 xgm_wire_sop = 0;
3052 
3053 	u32 core_pcie_dma_rsp_eop = 0;
3054 	u32 pcie_sge_dma_rsp_eop = 0;
3055 	u32 sge_debug_index6_eop = 0;
3056 	u32 sge_utx_eop = 0;
3057 	u32 utx_tp_eop = 0;
3058 	u32 utx_tpcside_eop = 0;
3059 	u32 tpcside_rxarb_eop = 0;
3060 	u32 tpeside_mps_eop = 0;
3061 	u32 tp_mps_eop = 0;
3062 	u32 mps_xgm_eop = 0;
3063 	u32 tx_xgm_xgm_eop = 0;
3064 	u32 xgm_wire_eop = 0;
3065 
3066 	u32 pcie_core_cmd_req_sop = 0;
3067 	u32 sge_pcie_cmd_req_sop = 0;
3068 	u32 core_pcie_cmd_rsp_sop = 0;
3069 	u32 pcie_sge_cmd_rsp_sop = 0;
3070 	u32 sge_cim_sop = 0;
3071 	u32 pcie_core_dma_req_sop = 0;
3072 	u32 sge_pcie_dma_req_sop = 0;
3073 	u32 utx_sge_dma_req_sop = 0;
3074 
3075 	u32 sge_pcie_cmd_req_eop = 0;
3076 	u32 pcie_core_cmd_req_eop = 0;
3077 	u32 core_pcie_cmd_rsp_eop = 0;
3078 	u32 pcie_sge_cmd_rsp_eop = 0;
3079 	u32 sge_cim_eop = 0;
3080 	u32 pcie_core_dma_req_eop = 0;
3081 	u32 sge_pcie_dma_req_eop = 0;
3082 	u32 utx_sge_dma_req_eop = 0;
3083 
3084 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3085 	if (rc)
3086 		return rc;
3087 
3088 	wtp = (struct wtp_data *) dc_buff.data;
3089 	/*Add up the sop/eop of all channels.*/
3090 	for (i = 0; i < 8; i++) {
3091 		if (i < 2) {
3092 			/*Rx Path*/
3093 			csw_sge_sop           +=
3094 				(wtp->sge_debug_data_high_indx1.sop[i]);
3095 			tp_csw_sop            +=
3096 				(wtp->sge_debug_data_high_indx9.sop[i]);
3097 
3098 			csw_sge_eop           += (wtp->csw_sge.eop[i]);
3099 			tp_csw_eop            += (wtp->tp_csw.eop[i]);
3100 
3101 			/*Tx Path*/
3102 			sge_pcie_cmd_req_sop  += wtp->sge_pcie_cmd_req.sop[i];
3103 			pcie_sge_cmd_rsp_sop  += wtp->pcie_sge_cmd_rsp.sop[i];
3104 			sge_cim_sop           += wtp->sge_cim.sop[i];
3105 			tpcside_csw_sop       += (wtp->utx_tpcside_tx.sop[i]);
3106 			sge_work_req_sop      += wtp->sge_work_req_pkt.sop[i];
3107 
3108 			sge_pcie_cmd_req_eop  += wtp->sge_pcie_cmd_req.eop[i];
3109 			pcie_sge_cmd_rsp_eop  += wtp->pcie_sge_cmd_rsp.eop[i];
3110 			sge_cim_eop           += wtp->sge_cim.eop[i];
3111 
3112 		}
3113 
3114 		if (i < 3) {
3115 			pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i];
3116 			core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i];
3117 
3118 			core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i];
3119 			pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i];
3120 		}
3121 
3122 		if (i < 4) {
3123 			/*Rx Path*/
3124 			pcie_core_dmaw_sop    +=
3125 				(wtp->pcie_dma1_stat2.sop[i]);
3126 			sge_pcie_sop          +=
3127 				(wtp->sge_debug_data_high_indx7.sop[i]);
3128 			ulprx_tpcside_sop     += (wtp->ulprx_tpcside.sop[i]);
3129 			pmrx_ulprx_sop        += (wtp->pmrx_ulprx.sop[i]);
3130 			mps_tpeside_sop       +=
3131 				(wtp->tp_dbg_eside_pktx.sop[i]);
3132 			rx_xgm_xgm_sop        +=
3133 				(wtp->mac_porrx_pkt_count.sop[i]);
3134 			wire_xgm_sop          +=
3135 				(wtp->mac_porrx_aframestra_ok.sop[i]);
3136 
3137 			pcie_core_dmaw_eop    +=
3138 				(wtp->pcie_dma1_stat2.eop[i]);
3139 			sge_pcie_eop          += (wtp->sge_pcie.eop[i]);
3140 			tpcside_csw_eop       += (wtp->tpcside_csw.eop[i]);
3141 			ulprx_tpcside_eop     += (wtp->ulprx_tpcside.eop[i]);
3142 			pmrx_ulprx_eop        += (wtp->pmrx_ulprx.eop[i]);
3143 			mps_tpeside_eop       += (wtp->mps_tpeside.eop[i]);
3144 			rx_xgm_xgm_eop        +=
3145 				(wtp->mac_porrx_pkt_count.eop[i]);
3146 			wire_xgm_eop          += (wtp->xgm_mps.eop[i]);
3147 
3148 			/*special case type 3:*/
3149 			mps_tp_sop            += (wtp->mps_tp.sop[i]);
3150 			mps_tp_eop            += (wtp->mps_tp.eop[i]);
3151 
3152 			/*Tx Path*/
3153 			core_pcie_dma_rsp_sop +=
3154 				wtp->pcie_t5_dma_stat3.sop[i];
3155 			pcie_sge_dma_rsp_sop  += wtp->pcie_sge_dma_rsp.sop[i];
3156 			sge_debug_index6_sop  +=
3157 				wtp->sge_debug_data_high_index_6.sop[i];
3158 			sge_utx_sop           += wtp->ulp_se_cnt_chx.sop[i];
3159 			utx_tp_sop            += wtp->utx_tp.sop[i];
3160 			utx_tpcside_sop       += wtp->utx_tpcside.sop[i];
3161 			tpcside_rxarb_sop     += wtp->tpcside_rxarb.sop[i];
3162 			tpeside_mps_sop       += wtp->tpeside_mps.sop[i];
3163 			tx_xgm_xgm_sop        +=
3164 				wtp->mac_portx_pkt_count.sop[i];
3165 			xgm_wire_sop          +=
3166 				wtp->mac_portx_aframestra_ok.sop[i];
3167 
3168 			core_pcie_dma_rsp_eop +=
3169 				wtp->pcie_t5_dma_stat3.eop[i];
3170 			pcie_sge_dma_rsp_eop  += wtp->pcie_sge_dma_rsp.eop[i];
3171 			sge_debug_index6_eop  +=
3172 				wtp->sge_debug_data_high_index_6.eop[i];
3173 			sge_utx_eop           += wtp->sge_utx.eop[i];
3174 			utx_tp_eop            += wtp->utx_tp.eop[i];
3175 			utx_tpcside_eop       += wtp->utx_tpcside.eop[i];
3176 			tpcside_rxarb_eop     += wtp->tpcside_rxarb.eop[i];
3177 			tpeside_mps_eop       += wtp->tpeside_mps.eop[i];
3178 			tx_xgm_xgm_eop        +=
3179 				wtp->mac_portx_pkt_count.eop[i];
3180 			xgm_wire_eop          +=
3181 				wtp->mac_portx_aframestra_ok.eop[i];
3182 
3183 			/*special case type 3:*/
3184 			tp_mps_sop            += wtp->tp_mps.sop[i];
3185 			mps_xgm_sop           += wtp->mps_xgm.sop[i];
3186 
3187 			tp_mps_eop            += wtp->tp_mps.eop[i];
3188 			mps_xgm_eop           += wtp->mps_xgm.eop[i];
3189 
3190 			pcie_core_dma_req_sop +=
3191 				wtp->pcie_dma1_stat2_core.sop[i];
3192 			sge_pcie_dma_req_sop  +=
3193 				wtp->sge_debug_data_high_indx5.sop[i];
3194 			utx_sge_dma_req_sop   += wtp->utx_sge_dma_req.sop[i];
3195 
3196 			pcie_core_dma_req_eop +=
3197 				wtp->pcie_dma1_stat2_core.eop[i];
3198 			sge_pcie_dma_req_eop  +=
3199 				wtp->sge_debug_data_high_indx5.eop[i];
3200 			utx_sge_dma_req_eop   += wtp->utx_sge_dma_req.eop[i];
3201 		}
3202 
3203 		xgm_mps_sop               += (wtp->xgm_mps.sop[i]);
3204 		xgm_mps_eop               += (wtp->xgm_mps.eop[i]);
3205 	}
3206 	printf("ifaces = nic0 nic1\n");
3207 	printf("*************************EGGRESS (TX) PATH **********************************\n");
3208 	printf("MOD :  core---->PCIE---->SGE<-|    #Ring Doorbell\n");
3209 	printf("SOP        ?      ???         |\n");
3210 	printf("EOP        ?      ???         |\n");
3211 	printf("MOD |<-core<----PCIE<----SGE<-|    #Request Work Request\n");
3212 	printf("SOP_CH0  %02X       %02x\n",
3213 			     wtp->pcie_cmd_stat2.sop[0],
3214 			     wtp->sge_pcie_cmd_req.sop[0]);
3215 	printf("SOP_CH1  %02X       %02X\n",
3216 		     wtp->pcie_cmd_stat2.sop[1], wtp->sge_pcie_cmd_req.sop[1]);
3217 	printf("SOP_CH2  %02X\n",
3218 		     wtp->pcie_cmd_stat2.sop[2]);
3219 	printf("SOP |    %02X       %02X\n",
3220 		     pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop);
3221 	printf("EOP |   %2X       %2X\n",
3222 		     pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop);
3223 	printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n");
3224 	printf("SOP_CH0  %02X       %02X      %02X"\
3225 		     "               |      %2X\n",
3226 		     wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[0],
3227 		     wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]);
3228 	printf("SOP_CH1  %02X       %02X      %02X"\
3229 		     "               |      %2X\n",
3230 		     wtp->pcie_cmd_stat3.sop[1], wtp->pcie_sge_cmd_rsp.sop[1],
3231 		     wtp->sge_cim.sop[1], wtp->sge_work_req_pkt.sop[1]);
3232 	printf("SOP_CH2  %02X                     "\
3233 		     "           |\n", wtp->pcie_cmd_stat3.sop[2]);
3234 	printf("SOP      %02X       %02X      %2X "\
3235 		     "              |      %2X\n",
3236 		     core_pcie_cmd_rsp_sop, pcie_sge_cmd_rsp_sop,
3237 		     sge_cim_sop, sge_work_req_sop);
3238 	printf("EOP      %2X       %2X      %2X   "\
3239 		     "            |\n",
3240 		     core_pcie_cmd_rsp_eop,
3241 		     pcie_sge_cmd_rsp_eop, sge_cim_eop);
3242 	printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n");
3243 	printf("SOP_CH0  %02X       %02X      "\
3244 		     "%02X\n", wtp->pcie_dma1_stat2_core.sop[0],
3245 		     wtp->sge_debug_data_high_indx5.sop[0],
3246 		     wtp->utx_sge_dma_req.sop[0]);
3247 	printf("SOP_CH1  %02X       %02X      "\
3248 		     "%02X\n", wtp->pcie_dma1_stat2_core.sop[1],
3249 		     wtp->sge_debug_data_high_indx5.sop[1],
3250 		     wtp->utx_sge_dma_req.sop[1]);
3251 	printf("SOP_CH2  %02X       %02X      "\
3252 		     "%02X\n", wtp->pcie_dma1_stat2_core.sop[2],
3253 		     wtp->sge_debug_data_high_indx5.sop[2],
3254 		     wtp->utx_sge_dma_req.sop[2]);
3255 	printf("SOP_CH3  %02X       %02X      "\
3256 		     "%02X\n", wtp->pcie_dma1_stat2_core.sop[3],
3257 		     wtp->sge_debug_data_high_indx5.sop[3],
3258 		     wtp->utx_sge_dma_req.sop[3]);
3259 	printf("SOP |    %2X       %2X      %2X\n",
3260 		     pcie_core_dma_req_sop/*eop in perl??*/,
3261 		     sge_pcie_dma_req_sop, utx_sge_dma_req_sop);
3262 	printf("EOP |    %2X       %2X      %2X\n",
3263 		     pcie_core_dma_req_eop,
3264 		     sge_pcie_dma_req_eop, utx_sge_dma_req_eop);
3265 	printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->wire\n");
3266 	printf("SOP_CH0        %02X %2X   %2X  %2X"\
3267 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3268 		     wtp->pcie_t5_dma_stat3.sop[0],
3269 		     wtp->sge_debug_data_high_index_6.sop[0],
3270 		     wtp->sge_debug_data_high_index_3.sop[0],
3271 		     wtp->ulp_se_cnt_chx.sop[0], wtp->utx_tpcside.sop[0],
3272 		     wtp->tpcside_rxarb.sop[0], wtp->tpeside_mps.sop[0],
3273 		     wtp->tp_mps.sop[0], wtp->mps_xgm.sop[0],
3274 		     wtp->mac_portx_pkt_count.sop[0],
3275 		     wtp->mac_portx_aframestra_ok.sop[0]);
3276 
3277 	printf("EOP_CH0        %02X %2X   %2X  %2X"\
3278 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3279 		     wtp->pcie_t5_dma_stat3.eop[0],
3280 		     wtp->sge_debug_data_high_index_6.eop[0],
3281 		     wtp->sge_debug_data_high_index_3.eop[0],
3282 		     wtp->ulp_se_cnt_chx.eop[0], wtp->utx_tpcside.eop[0],
3283 		     wtp->tpcside_rxarb.eop[0], wtp->tpeside_mps.eop[0],
3284 		     wtp->tp_mps.eop[0], wtp->mps_xgm.eop[0],
3285 		     wtp->mac_portx_pkt_count.eop[0],
3286 		     wtp->mac_portx_aframestra_ok.eop[0]);
3287 	printf("SOP_CH1        %02X %2X   %2X  %2X"\
3288 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3289 		     wtp->pcie_t5_dma_stat3.sop[1],
3290 		     wtp->sge_debug_data_high_index_6.sop[1],
3291 		     wtp->sge_debug_data_high_index_3.sop[1],
3292 		     wtp->ulp_se_cnt_chx.sop[1], wtp->utx_tpcside.sop[1],
3293 		     wtp->tpcside_rxarb.sop[1], wtp->tpeside_mps.sop[1],
3294 		     wtp->tp_mps.sop[1], wtp->mps_xgm.sop[1],
3295 		     wtp->mac_portx_pkt_count.sop[1],
3296 		     wtp->mac_portx_aframestra_ok.sop[1]);
3297 
3298 	printf("EOP_CH1        %02X %2X   %2X  %2X"\
3299 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3300 		     wtp->pcie_t5_dma_stat3.eop[1],
3301 		     wtp->sge_debug_data_high_index_6.eop[1],
3302 		     wtp->sge_debug_data_high_index_3.eop[1],
3303 		     wtp->ulp_se_cnt_chx.eop[1], wtp->utx_tpcside.eop[1],
3304 		     wtp->tpcside_rxarb.eop[1], wtp->tpeside_mps.eop[1],
3305 		     wtp->tp_mps.eop[1], wtp->mps_xgm.eop[1],
3306 		     wtp->mac_portx_pkt_count.eop[1],
3307 		     wtp->mac_portx_aframestra_ok.eop[1]);
3308 	printf("SOP_CH2        %02X %2X   %2X  %2X"\
3309 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3310 		     wtp->pcie_t5_dma_stat3.sop[2],
3311 		     wtp->sge_debug_data_high_index_6.sop[2],
3312 		     wtp->sge_debug_data_high_index_3.sop[2],
3313 		     wtp->ulp_se_cnt_chx.sop[2], wtp->utx_tpcside.sop[2],
3314 		     wtp->tpcside_rxarb.sop[2], wtp->tpeside_mps.sop[2],
3315 		     wtp->tp_mps.sop[2], wtp->mps_xgm.sop[2],
3316 		     wtp->mac_portx_pkt_count.sop[2],
3317 		     wtp->mac_portx_aframestra_ok.sop[2]);
3318 
3319 	printf("EOP_CH2        %02X %2X   %2X  %2X"\
3320 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3321 		     wtp->pcie_t5_dma_stat3.eop[2],
3322 		     wtp->sge_debug_data_high_index_6.eop[2],
3323 		     wtp->sge_debug_data_high_index_3.eop[2],
3324 		     wtp->ulp_se_cnt_chx.eop[2], wtp->utx_tpcside.eop[2],
3325 		     wtp->tpcside_rxarb.eop[2], wtp->tpeside_mps.eop[2],
3326 		     wtp->tp_mps.eop[2], wtp->mps_xgm.eop[2],
3327 		     wtp->mac_portx_pkt_count.eop[2],
3328 		     wtp->mac_portx_aframestra_ok.eop[2]);
3329 	printf("SOP_CH3        %02X %2X   %2X  %2X"\
3330 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3331 		     wtp->pcie_t5_dma_stat3.sop[3],
3332 		     wtp->sge_debug_data_high_index_6.sop[3],
3333 		     wtp->sge_debug_data_high_index_3.sop[3],
3334 		     wtp->ulp_se_cnt_chx.sop[3], wtp->utx_tpcside.sop[3],
3335 		     wtp->tpcside_rxarb.sop[3], wtp->tpeside_mps.sop[3],
3336 		     wtp->tp_mps.sop[3], wtp->mps_xgm.sop[3],
3337 		     wtp->mac_portx_pkt_count.sop[3],
3338 		     wtp->mac_portx_aframestra_ok.sop[3]);
3339 
3340 	printf("EOP_CH3        %02X %2X   %2X  %2X"\
3341 		     "    %2X       %2X    %2X   %02X  %02X   %02X      %02X\n",
3342 		     wtp->pcie_t5_dma_stat3.eop[3],
3343 		     wtp->sge_debug_data_high_index_6.eop[3],
3344 		     wtp->sge_debug_data_high_index_3.eop[3],
3345 		     wtp->ulp_se_cnt_chx.eop[3], wtp->utx_tpcside.eop[3],
3346 		     wtp->tpcside_rxarb.eop[3], wtp->tpeside_mps.eop[3],
3347 		     wtp->tp_mps.eop[3], wtp->mps_xgm.eop[3],
3348 		     wtp->mac_portx_pkt_count.eop[3],
3349 		     wtp->mac_portx_aframestra_ok.eop[3]);
3350 	printf("SOP            %2X %2X   %2X  %2X "\
3351 		     "   %2X       %2X    %2X   %2X  %2X   %2X      %2X\n",
3352 		     core_pcie_dma_rsp_sop, sge_debug_index6_sop,
3353 		     pcie_sge_dma_rsp_sop, sge_utx_sop, utx_tp_sop,
3354 		     tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop,
3355 		     mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop);
3356 	printf("EOP            %2X %2X   %2X  %2X "\
3357 		     "   %2X       %2X    %2X   %2X  %2X   %2X      %2X\n",
3358 		     core_pcie_dma_rsp_eop, sge_debug_index6_eop,
3359 		     pcie_sge_dma_rsp_eop, sge_utx_eop, utx_tp_eop,
3360 		     tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop,
3361 		     mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop);
3362 	printf("*************************INGRESS (RX) PATH **********************************\n");
3363 
3364 	printf("MOD   core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<---wire\n");
3365 
3366 	printf("SOP_CH0      %2X  %2X    %2X    %2X"\
3367 		     "   %2X  %2X  %2X %2X  %2X    %2X   %02X  %02X      "\
3368 		     "%02X\n",
3369 		     wtp->pcie_dma1_stat2.sop[0],
3370 		     wtp->sge_debug_data_high_indx7.sop[0],
3371 		     wtp->sge_debug_data_high_indx1.sop[0],
3372 		     wtp->sge_debug_data_high_indx9.sop[0],
3373 		     wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0],
3374 		     wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop,
3375 		     wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0],
3376 		     wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0],
3377 		     wtp->mac_porrx_aframestra_ok.sop[0]);
3378 
3379 	printf("EOP_CH0      %2X  %2X    %2X    "\
3380 		     "%2X   %2X  %2X  %2X %2X  %2X    %2X   %02X  %02X  "\
3381 		     "    %02X\n",
3382 		     wtp->pcie_dma1_stat2.eop[0],
3383 		     wtp->sge_debug_data_high_indx7.eop[0],
3384 		     wtp->sge_debug_data_high_indx1.eop[0],
3385 		     wtp->sge_debug_data_high_indx9.eop[0],
3386 		     wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0],
3387 		     wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop,
3388 		     wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0],
3389 		     wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0],
3390 		     wtp->mac_porrx_aframestra_ok.eop[0]);
3391 	printf("SOP_CH1      %2X  %2X    %2X    "\
3392 		     "%2X   %2X  %2X  %2X     %2X    %2X   %02X  %02X   "\
3393 		     "   %02X\n",
3394 		     wtp->pcie_dma1_stat2.sop[1],
3395 		     wtp->sge_debug_data_high_indx7.sop[1],
3396 		     wtp->sge_debug_data_high_indx1.sop[1],
3397 		     wtp->sge_debug_data_high_indx9.sop[1],
3398 		     wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1],
3399 		     wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1],
3400 		     wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1],
3401 		     wtp->mac_porrx_pkt_count.sop[1],
3402 		     wtp->mac_porrx_aframestra_ok.sop[1]);
3403 
3404 	printf("EOP_CH1      %2X  %2X    %2X    "\
3405 		     "%2X   %2X  %2X  %2X     %2X    %2X   %02X  %02X   "\
3406 		     "   %02X\n",
3407 		     wtp->pcie_dma1_stat2.eop[1],
3408 		     wtp->sge_debug_data_high_indx7.eop[1],
3409 		     wtp->sge_debug_data_high_indx1.eop[1],
3410 		     wtp->sge_debug_data_high_indx9.eop[1],
3411 		     wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1],
3412 		     wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1],
3413 		     wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1],
3414 		     wtp->mac_porrx_pkt_count.eop[1],
3415 		     wtp->mac_porrx_aframestra_ok.eop[1]);
3416 	printf("SOP_CH2      %2X  %2X             "\
3417 		     "                 %2X    %2X   %02X  %02X      %02X\n",
3418 		     wtp->pcie_dma1_stat2.sop[2],
3419 		     wtp->sge_debug_data_high_indx7.sop[2],
3420 		     wtp->tp_dbg_eside_pktx.sop[2], wtp->mps_tp.sop[2],
3421 		     wtp->xgm_mps.sop[2], wtp->mac_porrx_pkt_count.sop[2],
3422 		     wtp->mac_porrx_aframestra_ok.sop[2]);
3423 
3424 	printf("EOP_CH2      %2X  %2X             "\
3425 		     "                 %2X    %2X   %02X  %02X      %02X\n",
3426 		     wtp->pcie_dma1_stat2.eop[2],
3427 		     wtp->sge_debug_data_high_indx7.eop[2],
3428 		     wtp->tp_dbg_eside_pktx.eop[2], wtp->mps_tp.eop[2],
3429 		     wtp->xgm_mps.eop[2], wtp->mac_porrx_pkt_count.eop[2],
3430 		     wtp->mac_porrx_aframestra_ok.eop[2]);
3431 	printf("SOP_CH3      %2X  %2X             "\
3432 		     "                 %2X    %2X   %02X  %02X      %02X\n",
3433 		     wtp->pcie_dma1_stat2.sop[3],
3434 		     wtp->sge_debug_data_high_indx7.sop[3],
3435 		     wtp->tp_dbg_eside_pktx.sop[3], wtp->mps_tp.sop[3],
3436 		     wtp->xgm_mps.sop[3], wtp->mac_porrx_pkt_count.sop[3],
3437 		     wtp->mac_porrx_aframestra_ok.sop[3]);
3438 
3439 	printf("EOP_CH3      %2X  %2X             "\
3440 		     "                 %2X    %2X   %02X  %02X      %02X\n",
3441 		     wtp->pcie_dma1_stat2.eop[3],
3442 		     wtp->sge_debug_data_high_indx7.eop[3],
3443 		     wtp->tp_dbg_eside_pktx.eop[3], wtp->mps_tp.eop[3],
3444 		     wtp->xgm_mps.eop[3], wtp->mac_porrx_pkt_count.eop[3],
3445 		     wtp->mac_porrx_aframestra_ok.eop[3]);
3446 	printf("SOP_CH4                           "\
3447 		     "                          %02X\n",
3448 		     wtp->xgm_mps.sop[4]);
3449 	printf("EOP_CH4                           "\
3450 		     "                          %02X\n",
3451 		     wtp->xgm_mps.eop[4]);
3452 	printf("SOP_CH5                           "\
3453 		     "                          %02X\n",
3454 		     wtp->xgm_mps.sop[5]);
3455 	printf("EOP_CH5                           "\
3456 		     "                          %02X\n",
3457 		     wtp->xgm_mps.eop[5]);
3458 	printf("SOP_CH6                           "\
3459 		     "                          %02X\n",
3460 		     wtp->xgm_mps.sop[6]);
3461 	printf("EOP_CH6                           "\
3462 		     "                          %02X\n",
3463 		     wtp->xgm_mps.eop[6]);
3464 	printf("SOP_CH7                           "\
3465 		     "                          %02X\n",
3466 		     wtp->xgm_mps.sop[7]);
3467 	printf("EOP_CH7                           "\
3468 		     "                          %02X\n",
3469 		     wtp->xgm_mps.eop[7]);
3470 
3471 	printf("SOP          %2X  %2X    %2X    "\
3472 		     "%2X   %2X  %2X   %2X    %2X    %2X   %2X  %2X     %2X\n",
3473 		     pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop,
3474 		     tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop,
3475 		     pmrx_ulprx_sop, mps_tpeside_sop, mps_tp_sop,
3476 		     xgm_mps_sop, rx_xgm_xgm_sop, wire_xgm_sop);
3477 	printf("EOP          %2X  %2X    %2X    "\
3478 		     "%2X   %2X  %2X   %2X    %2X    %2X   %2X  %2X     %2X\n",
3479 		     pcie_core_dmaw_eop, sge_pcie_eop,
3480 		     csw_sge_eop, tp_csw_eop,
3481 		     tpcside_csw_eop, ulprx_tpcside_eop,
3482 		     pmrx_ulprx_eop, mps_tpeside_eop,
3483 		     mps_tp_eop, xgm_mps_eop, rx_xgm_xgm_eop,
3484 		     wire_xgm_eop);
3485 	printf("DROP: ???      ???      ???       "\
3486 		     "%2X(mib)  %2X(err) %2X(oflow) %X(cls)\n",
3487 		     (wtp->mps_tp.drops & 0xFF),
3488 		     (wtp->xgm_mps.err & 0xFF),
3489 		     (wtp->xgm_mps.drop & 0xFF),
3490 		     (wtp->xgm_mps.cls_drop & 0xFF));
3491 	printf("INTS:  ");
3492 	for (i = 0; i < 4; i++) {
3493 		printf("%2X<- %2X    ",
3494 			     (wtp->pcie_core_dmai.sop[i] & 0xF),
3495 			     (wtp->sge_pcie_ints.sop[i] & 0xF));
3496 	}
3497 	printf("(PCIE<-SGE, channels 0 to 3)\n");
3498 
3499 	return rc;
3500 }
3501 
3502 int
view_wtp(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3503 view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3504 	 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3505 {
3506 	int rc = -1;
3507 
3508 	if (is_t5(chip))
3509 		rc = t5_view_wtp(pbuf, entity_hdr, cudbg_poutbuf);
3510 	else if (is_t6(chip))
3511 		rc = t6_view_wtp(pbuf, entity_hdr, cudbg_poutbuf);
3512 
3513 	return rc;
3514 }
3515 
3516 /*
3517  *  * Small utility function to return the strings "yes" or "no" if the
3518  *  supplied
3519  *   * argument is non-zero.
3520  *    */
3521 static const char *
yesno(int x)3522 yesno(int x)
3523 {
3524 	static const char *yes = "yes";
3525 	static const char *no = "no";
3526 
3527 	return x ? yes : no;
3528 }
3529 
3530 static int
dump_indirect_regs(const struct cudbg_reg_info * reg_array,u32 indirect_addr,const u32 * regs,struct cudbg_buffer * cudbg_poutbuf)3531 dump_indirect_regs(const struct cudbg_reg_info *reg_array,
3532 		   u32 indirect_addr, const u32 *regs,
3533 		   struct cudbg_buffer *cudbg_poutbuf)
3534 {
3535 	uint32_t reg_val = 0; /* silence compiler warning*/
3536 	int i, rc;
3537 
3538 	for (i = 0 ; reg_array->name; ++reg_array) {
3539 		if (!reg_array->len) {
3540 			reg_val = regs[i];
3541 			i++;
3542 			printf("[0x%05x:0x%05x] "\
3543 				     "%-47s %#-14x %u\n",
3544 				     indirect_addr, reg_array->addr,
3545 				     reg_array->name, reg_val, reg_val);
3546 		} else {
3547 			uint32_t v = xtract(reg_val, reg_array->addr,
3548 					reg_array->len);
3549 			printf("    %*u:%u %-55s "\
3550 				     "%#-14x %u\n",
3551 				     reg_array->addr < 10 ? 3 : 2,
3552 				     reg_array->addr + reg_array->len - 1,
3553 				     reg_array->addr, reg_array->name, v, v);
3554 		}
3555 	}
3556 
3557 	return 1;
3558 
3559 	return rc;
3560 }
3561 
3562 int
view_cctrl(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3563 view_cctrl(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3564 	   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3565 {
3566 	struct cudbg_buffer c_buff, dc_buff;
3567 	u16 (*incr)[NCCTRL_WIN];
3568 	int rc = 0;
3569 	u32 i = 0;
3570 
3571 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3572 	if (rc)
3573 		return rc;
3574 
3575 	incr = (void *)dc_buff.data;
3576 	for (i = 0; i < NCCTRL_WIN; i++) {
3577 		printf("%2d: %4u %4u %4u %4u %4u "\
3578 			     "%4u %4u %4u\n", i,
3579 			     incr[0][i], incr[1][i], incr[2][i], incr[3][i],
3580 			     incr[4][i], incr[5][i], incr[6][i], incr[7][i]);
3581 		printf("%8u %4u %4u %4u %4u %4u %4u"\
3582 			     " %4u\n", incr[8][i], incr[9][i], incr[10][i],
3583 			     incr[11][i], incr[12][i], incr[13][i],
3584 			     incr[14][i], incr[15][i]);
3585 	}
3586 
3587 	return rc;
3588 }
3589 
3590 int
view_up_cim_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3591 view_up_cim_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3592 		     struct cudbg_buffer *cudbg_poutbuf,
3593 		     enum chip_type chip)
3594 {
3595 	struct cudbg_buffer c_buff, dc_buff;
3596 	struct ireg_buf *up_cim_indr;
3597 	u32 indirect_addr;
3598 	int rc = 0;
3599 	int i = 0;
3600 	int n = 0;
3601 
3602 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3603 	if (rc)
3604 		return rc;
3605 
3606 	indirect_addr = A_CIM_HOST_ACC_CTRL;
3607 	up_cim_indr = (struct ireg_buf *)dc_buff.data;
3608 	if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5)
3609 		n = sizeof(t5_up_cim_reg_array) / (5 * sizeof(u32));
3610 	else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
3611 		n = sizeof(t6_up_cim_reg_array) / (5 * sizeof(u32));
3612 
3613 	for (i = 0; i < n; i++) {
3614 		u32 *buff = up_cim_indr->outbuf;
3615 
3616 		if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5)
3617 			rc = dump_indirect_regs(t5_up_cim_reg_ptr[i],
3618 						indirect_addr,
3619 						(const u32 *)buff,
3620 						cudbg_poutbuf);
3621 		else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
3622 			rc = dump_indirect_regs(t6_up_cim_reg_ptr[i],
3623 						indirect_addr,
3624 						(const u32 *)buff,
3625 						cudbg_poutbuf);
3626 
3627 		if (rc < 0)
3628 			goto err1;
3629 		up_cim_indr++;
3630 
3631 		/* Prohibit accessing data beyond entity size. This helps
3632 		 * new app and old dump compatibily scenario
3633 		 */
3634 		if ((char *)up_cim_indr >= (dc_buff.data + dc_buff.size))
3635 			break;
3636 	}
3637 
3638 err1:
3639 	return rc;
3640 }
3641 
3642 static int
print_pbt_addr_entry(struct cudbg_buffer * cudbg_poutbuf,u32 val)3643 print_pbt_addr_entry(struct cudbg_buffer *cudbg_poutbuf, u32 val)
3644 {
3645 	char *fmts = "\n    [%2u:%2u]  %-10s  ";
3646 	u32 vld, alloc, pending, address;
3647 	int rc = 0;
3648 
3649 	vld = (val >> 28) & 1;
3650 	printf(fmts, 28, 28, "vld");
3651 	printf("%d", vld);
3652 
3653 	alloc = (val >> 27) & 1;
3654 	printf(fmts, 27, 27, "alloc");
3655 	printf("%d", alloc);
3656 
3657 	pending = (val >> 26) & 1;
3658 	printf(fmts, 26, 26, "pending");
3659 	printf("%d", pending);
3660 
3661 	address = val & 0x1FFFFFF;
3662 	printf(fmts, 25, 0, "address<<6");
3663 	printf("0x%08x", address<<6);
3664 	printf("\n");
3665 
3666 
3667 	return rc;
3668 }
3669 
3670 int
view_mbox_log(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3671 view_mbox_log(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3672 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3673 {
3674 	struct cudbg_mbox_log *mboxlog = NULL;
3675 	struct cudbg_buffer c_buff, dc_buff;
3676 	u16 mbox_cmds;
3677 	int rc, i, k;
3678 
3679 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3680 	if (rc)
3681 		return rc;
3682 
3683 	mbox_cmds = (u16)dc_buff.size / sizeof(struct cudbg_mbox_log);
3684 	mboxlog = (struct cudbg_mbox_log *)dc_buff.data;
3685 	printf(
3686 		     "%10s  %15s  %5s  %5s  %s\n", "Seq", "Tstamp", "Atime",
3687 		     "Etime", "Command/Reply");
3688 
3689 	for (i = 0; i < mbox_cmds && mboxlog->entry.timestamp; i++) {
3690 		printf("%10u  %15llu  %5d  %5d",
3691 			     mboxlog->entry.seqno, mboxlog->entry.timestamp,
3692 			     mboxlog->entry.access, mboxlog->entry.execute);
3693 
3694 		for (k = 0; k < MBOX_LEN / 8; k++)
3695 			printf("  %08x %08x",
3696 				     mboxlog->hi[k], mboxlog->lo[k]);
3697 
3698 		printf("\n");
3699 		mboxlog++;
3700 	}
3701 
3702 	return rc;
3703 }
3704 
3705 int
view_pbt_tables(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3706 view_pbt_tables(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3707 		struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3708 {
3709 	struct cudbg_buffer c_buff, dc_buff;
3710 	struct cudbg_pbt_tables *pbt;
3711 	int rc = 0;
3712 	int i = 0;
3713 	u32 addr;
3714 
3715 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3716 	if (rc)
3717 		return rc;
3718 
3719 	pbt = (struct cudbg_pbt_tables *)dc_buff.data;
3720 	/* PBT dynamic entries */
3721 	addr = CUDBG_CHAC_PBT_ADDR;
3722 	for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
3723 		printf("Dynamic ");
3724 		printf("Addr Table [0x%03x]: 0x%08x",
3725 			     (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR),
3726 			     pbt->pbt_dynamic[i]);
3727 		rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_dynamic[i]);
3728 		if (rc < 0)
3729 			goto err1;
3730 	}
3731 
3732 	/* PBT static entries */
3733 	addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
3734 	for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
3735 		printf("Static ");
3736 		printf("Addr Table [0x%03x]: 0x%08x",
3737 			     (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR),
3738 			     pbt->pbt_static[i]);
3739 		rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_static[i]);
3740 		if (rc < 0)
3741 			goto err1;
3742 	}
3743 
3744 	/* PBT lrf entries */
3745 	addr = CUDBG_CHAC_PBT_LRF;
3746 	for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
3747 		printf(
3748 			     "LRF Table [0x%03x]: 0x%08x\n",
3749 			     (addr + (i * 4) - CUDBG_CHAC_PBT_LRF),
3750 			     pbt->lrf_table[i]);
3751 	}
3752 
3753 	/* PBT data entries */
3754 	addr = CUDBG_CHAC_PBT_DATA;
3755 	for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
3756 		printf(
3757 			     "DATA Table [0x%03x]: 0x%08x\n",
3758 			     (addr + (i * 4) - CUDBG_CHAC_PBT_DATA),
3759 			     pbt->pbt_data[i]);
3760 	}
3761 
3762 err1:
3763 	return rc;
3764 }
3765 
3766 int
view_ma_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3767 view_ma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3768 		 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3769 {
3770 	struct cudbg_buffer c_buff, dc_buff;
3771 	struct ireg_buf *ma_indr;
3772 	u32 indirect_addr;
3773 	int rc = 0;
3774 	int i = 0;
3775 	int n;
3776 
3777 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3778 	if (rc)
3779 		return rc;
3780 
3781 	indirect_addr = A_MA_LOCAL_DEBUG_CFG;
3782 	ma_indr = (struct ireg_buf *)dc_buff.data;
3783 	n = sizeof(t6_ma_ireg_array) / (4 * sizeof(u32));
3784 	n += sizeof(t6_ma_ireg_array2) / (4 * sizeof(u32));
3785 	for (i = 0; i < n; i++) {
3786 		u32 *buff = ma_indr->outbuf;
3787 
3788 		rc = dump_indirect_regs(t6_ma_ptr[i], indirect_addr,
3789 					(const u32 *) buff, cudbg_poutbuf);
3790 		if (rc < 0)
3791 			goto err1;
3792 		ma_indr++;
3793 	}
3794 
3795 err1:
3796 	return rc;
3797 }
3798 
3799 int
view_hma_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3800 view_hma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3801 		  struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3802 {
3803 	struct cudbg_buffer c_buff, dc_buff;
3804 	struct ireg_buf *hma_indr;
3805 	u32 indirect_addr;
3806 	int rc = 0;
3807 	int i = 0;
3808 	int n;
3809 
3810 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3811 	if (rc)
3812 		return rc;
3813 
3814 	indirect_addr = A_HMA_LOCAL_DEBUG_CFG;
3815 	hma_indr = (struct ireg_buf *)dc_buff.data;
3816 	n = sizeof(t6_hma_ireg_array) / (4 * sizeof(u32));
3817 	for (i = 0; i < n; i++) {
3818 		u32 *buff = hma_indr->outbuf;
3819 
3820 		rc = dump_indirect_regs(t6_hma_ptr[i], indirect_addr,
3821 					(const u32 *) buff, cudbg_poutbuf);
3822 		if (rc < 0)
3823 			goto err1;
3824 		hma_indr++;
3825 	}
3826 
3827 err1:
3828 	return rc;
3829 }
3830 
3831 int
view_pm_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3832 view_pm_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3833 		 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3834 {
3835 	struct cudbg_buffer c_buff, dc_buff;
3836 	struct ireg_buf *ch_pm;
3837 	u32 indirect_addr;
3838 	int rc = 0;
3839 	int i = 0;
3840 	int n;
3841 
3842 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3843 	if (rc)
3844 		return rc;
3845 
3846 	ch_pm = (struct ireg_buf *)dc_buff.data;
3847 
3848 	if (!cudbg_poutbuf->data)
3849 		printf("\n\nPM_RX\n\n");
3850 
3851 	indirect_addr = PM_RX_INDIRECT;
3852 	n = sizeof(t5_pm_rx_array)/(4 * sizeof(u32));
3853 	for (i = 0; i < n; i++) {
3854 		u32 *buff = ch_pm->outbuf;
3855 
3856 		rc = dump_indirect_regs(t5_pm_rx_ptr[i], indirect_addr,
3857 					(const u32 *) buff, cudbg_poutbuf);
3858 		if (rc < 0)
3859 			goto err1;
3860 
3861 		ch_pm++;
3862 	}
3863 
3864 	if (!cudbg_poutbuf->data)
3865 		printf("\n\nPM_TX\n\n");
3866 
3867 	indirect_addr = PM_TX_INDIRECT;
3868 	n = sizeof(t5_pm_tx_array)/(4 * sizeof(u32));
3869 	for (i = 0; i < n; i++) {
3870 		u32 *buff = ch_pm->outbuf;
3871 
3872 		rc = dump_indirect_regs(t5_pm_tx_ptr[i], indirect_addr,
3873 					(const u32 *) buff, cudbg_poutbuf);
3874 		if (rc < 0)
3875 			goto err1;
3876 		ch_pm++;
3877 	}
3878 
3879 err1:
3880 	return rc;
3881 }
3882 
3883 int
view_tx_rate(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3884 view_tx_rate(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3885 	     struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3886 {
3887 	struct cudbg_buffer c_buff, dc_buff;
3888 	struct tx_rate *tx_rate;
3889 	int rc = 0;
3890 
3891 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3892 	if (rc)
3893 		return rc;
3894 
3895 	tx_rate = (struct tx_rate *)dc_buff.data;
3896 	printf("\n\n\t\tTX_RATE\n\n");
3897 	if (tx_rate->nchan == NCHAN) {
3898 		printf("              channel 0   channel 1   channel 2   channel 3\n");
3899 		printf("NIC B/s:     %10llu  %10llu"\
3900 			     "  %10llu  %10llu\n",
3901 			     (unsigned long long)tx_rate->nrate[0],
3902 			     (unsigned long long)tx_rate->nrate[1],
3903 			     (unsigned long long)tx_rate->nrate[2],
3904 			     (unsigned long long)tx_rate->nrate[3]);
3905 		printf("Offload B/s: %10llu  %10llu"\
3906 			     "  %10llu  %10llu\n",
3907 			     (unsigned long long)tx_rate->orate[0],
3908 			     (unsigned long long)tx_rate->orate[1],
3909 			     (unsigned long long)tx_rate->orate[2],
3910 			     (unsigned long long)tx_rate->orate[3]);
3911 	} else {
3912 		printf("              channel 0   "\
3913 			     "channel 1\n");
3914 		printf("NIC B/s:     %10llu  "\
3915 			     "%10llu\n",
3916 			     (unsigned long long)tx_rate->nrate[0],
3917 			     (unsigned long long)tx_rate->nrate[1]);
3918 		printf("Offload B/s: %10llu  "\
3919 			     "%10llu\n",
3920 			     (unsigned long long)tx_rate->orate[0],
3921 			     (unsigned long long)tx_rate->orate[1]);
3922 	}
3923 
3924 	return rc;
3925 }
3926 
3927 int
view_tid(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)3928 view_tid(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
3929 	 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
3930 {
3931 	struct cudbg_buffer c_buff, dc_buff;
3932 	struct tid_info_region_rev1 *tid1;
3933 	struct tid_info_region *tid;
3934 	u32 tid_start = 0;
3935 	int rc = 0, rev;
3936 
3937 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
3938 	if (rc)
3939 		return rc;
3940 
3941 	rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
3942 	if (rev) {
3943 		tid1 = (struct tid_info_region_rev1 *)(dc_buff.data);
3944 		tid_start = tid1->tid_start;
3945 		tid = &(tid1->tid);
3946 	} else
3947 		tid = (struct tid_info_region *)dc_buff.data;
3948 
3949 	printf("\n\n\tTID INFO\n\n");
3950 	if (tid->le_db_conf & F_HASHEN) {
3951 		if (tid->sb) {
3952 			printf("TID range: "\
3953 				     "%u..%u/%u..%u\n", tid_start, tid->sb - 1,
3954 				     tid->hash_base, tid->ntids - 1);
3955 		} else if (tid->flags & FW_OFLD_CONN) {
3956 			printf("TID range: "\
3957 				     "%u..%u/%u..%u\n", tid->aftid_base,
3958 				     tid->aftid_end, tid->hash_base,
3959 				     tid->ntids - 1);
3960 
3961 		} else {
3962 			printf("TID range: "\
3963 				     "%u..%u\n", tid->hash_base,
3964 				     tid->ntids - 1);
3965 		}
3966 	} else if (tid->ntids) {
3967 		printf("TID range: %u..%u\n",
3968 			     tid_start, tid->ntids - 1);
3969 	}
3970 
3971 	if (tid->nstids)
3972 		printf("STID range: %u..%u\n",
3973 			     tid->stid_base, tid->stid_base + tid->nstids - 1);
3974 
3975 #if 0    /*For T4 cards*/
3976 	if (tid->nsftids)
3977 		printf("SFTID range: %u..%u\n",
3978 			     tid->sftid_base,
3979 			     tid->sftid_base + tid->nsftids - 2);
3980 #endif
3981 
3982 	if (tid->nuotids)
3983 		printf("UOTID range: %u..%u\n",
3984 			     tid->uotid_base,
3985 			     tid->uotid_base + tid->nuotids - 1);
3986 
3987 	if (tid->nhpftids && is_t6(chip))
3988 		printf("HPFTID range: %u..%u\n",
3989 			     tid->hpftid_base,
3990 			     tid->hpftid_base + tid->nhpftids - 1);
3991 	if (tid->ntids)
3992 		printf("HW TID usage: %u IP users, "\
3993 			     "%u IPv6 users\n",
3994 			     tid->IP_users, tid->IPv6_users);
3995 
3996 	return rc;
3997 }
3998 
3999 static int
show_cntxt(struct cudbg_ch_cntxt * context,struct cudbg_cntxt_field * field,struct cudbg_buffer * cudbg_poutbuf)4000 show_cntxt(struct cudbg_ch_cntxt *context,
4001 	   struct cudbg_cntxt_field *field,
4002 	   struct cudbg_buffer *cudbg_poutbuf)
4003 {
4004 	char str[8];
4005 	int rc = 0;
4006 
4007 	if (context->cntxt_type == CTXT_EGRESS)
4008 		strcpy(str, "egress");
4009 	if (context->cntxt_type == CTXT_INGRESS)
4010 		strcpy(str, "ingress");
4011 	if (context->cntxt_type == CTXT_FLM)
4012 		strcpy(str, "fl");
4013 	if (context->cntxt_type == CTXT_CNM)
4014 		strcpy(str, "cong");
4015 	printf("\n\nContext type: %-47s\nQueue ID: "\
4016 			"%-10d\n", str, context->cntxt_id);
4017 
4018 	while (field->name) {
4019 		unsigned long long data;
4020 
4021 		u32 index = field->start_bit / 32;
4022 		u32 bits = field->start_bit % 32;
4023 		u32 width = field->end_bit - field->start_bit + 1;
4024 		u32 mask = (1ULL << width) - 1;
4025 
4026 		data = (unsigned long long)((context->data[index] >> bits) |
4027 		       ((u64)context->data[index + 1] << (32 - bits)));
4028 		if (bits)
4029 			data |= ((u64)context->data[index + 2] << (64 - bits));
4030 		data &= mask;
4031 
4032 		if (field->islog2)
4033 			data = (unsigned long long)1 << data;
4034 
4035 		printf("%-47s %#-10llx\n",
4036 			     field->name, data << field->shift);
4037 		field++;
4038 	}
4039 
4040 	return rc;
4041 }
4042 
4043 int
view_mps_tcam(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4044 view_mps_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4045 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4046 {
4047 	struct cudbg_buffer c_buff, dc_buff;
4048 	struct cudbg_mps_tcam *tcam;
4049 	int rc = 0;
4050 	int n, i;
4051 
4052 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4053 	if (rc)
4054 		return rc;
4055 
4056 	n = dc_buff.size / sizeof(struct cudbg_mps_tcam);
4057 	tcam = (struct cudbg_mps_tcam *)dc_buff.data;
4058 	if (is_t6(chip)) {
4059 		printf("Idx  Ethernet address     "\
4060 			     "Mask       VNI   Mask   IVLAN Vld DIP_Hit   "\
4061 			     "Lookup  Port Vld Ports PF  VF                  "\
4062 			     "         Replication                           "\
4063 			     "         P0 P1 P2 P3  ML\n");
4064 	} else if (is_t5(chip)) {
4065 		if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) {
4066 			printf("Idx  Ethernet "\
4067 				     "address     Mask     Vld Ports PF  VF  "\
4068 				     "                         Replication   "\
4069 				     "                                 P0 P1 "\
4070 				     "P2 P3  ML\n");
4071 		} else {
4072 			printf("Idx  Ethernet "\
4073 				     "address     Mask     Vld Ports PF  VF  "\
4074 				     "            Replication               P0"\
4075 				     " P1 P2 P3  ML\n");
4076 		}
4077 	}
4078 
4079 	for (i = 0; i < n; i++, tcam++) {
4080 		/* Print only valid MPS TCAM entries */
4081 		if (i && !tcam->idx)
4082 			continue;
4083 
4084 		if (is_t6(chip)) {
4085 			/* Inner header lookup */
4086 			if (tcam->lookup_type && (tcam->lookup_type !=
4087 						  M_DATALKPTYPE)) {
4088 				printf("%3u "\
4089 					     "%02x:%02x:%02x:%02x:%02x:%02x "\
4090 					     "%012llx %06x %06x    -    -   "\
4091 					     "%3c      %3c  %4x   %3c   "\
4092 					     "%#x%4u%4d",
4093 					     tcam->idx, tcam->addr[0],
4094 					     tcam->addr[1], tcam->addr[2],
4095 					     tcam->addr[3], tcam->addr[4],
4096 					     tcam->addr[5],
4097 					     (unsigned long long)tcam->mask,
4098 					     tcam->vniy, (tcam->vnix | tcam->vniy),
4099 					     tcam->dip_hit ? 'Y' : 'N',
4100 					     tcam->lookup_type ? 'I' : 'O',
4101 					     tcam->port_num,
4102 					     (tcam->cls_lo & F_T6_SRAM_VLD)
4103 					     ? 'Y' : 'N',
4104 					     G_PORTMAP(tcam->cls_hi),
4105 					     G_T6_PF(tcam->cls_lo),
4106 					     (tcam->cls_lo & F_T6_VF_VALID)
4107 					     ?
4108 					     G_T6_VF(tcam->cls_lo) : -1);
4109 			} else {
4110 				printf("%3u "\
4111 					     "%02x:%02x:%02x:%02x:%02x:%02x"\
4112 					     " %012llx    -       -   ",
4113 					     tcam->idx, tcam->addr[0],
4114 					     tcam->addr[1], tcam->addr[2],
4115 					     tcam->addr[3], tcam->addr[4],
4116 					     tcam->addr[5],
4117 					     (unsigned long long)tcam->mask);
4118 
4119 				if (tcam->vlan_vld) {
4120 					printf(
4121 						     "%4u  Y     ",
4122 						     tcam->ivlan);
4123 				} else {
4124 					printf(
4125 						     "  -    N     ");
4126 				}
4127 
4128 				printf(
4129 					     "-      %3c  %4x   %3c   "\
4130 					     "%#x%4u%4d",
4131 					     tcam->lookup_type ? 'I' : 'O',
4132 					     tcam->port_num,
4133 					     (tcam->cls_lo & F_T6_SRAM_VLD)
4134 					     ? 'Y' : 'N',
4135 					     G_PORTMAP(tcam->cls_hi),
4136 					     G_T6_PF(tcam->cls_lo),
4137 					     (tcam->cls_lo & F_T6_VF_VALID)
4138 					     ?
4139 					     G_T6_VF(tcam->cls_lo) : -1);
4140 			}
4141 		} else if (is_t5(chip)) {
4142 			printf("%3u "\
4143 				     "%02x:%02x:%02x:%02x:%02x:%02x %012llx%3c"\
4144 				     "   %#x%4u%4d",
4145 				     tcam->idx, tcam->addr[0], tcam->addr[1],
4146 				     tcam->addr[2], tcam->addr[3],
4147 				     tcam->addr[4], tcam->addr[5],
4148 				     (unsigned long long)tcam->mask,
4149 				     (tcam->cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
4150 				     G_PORTMAP(tcam->cls_hi),
4151 				     G_PF(tcam->cls_lo),
4152 				     (tcam->cls_lo & F_VF_VALID) ?
4153 				     G_VF(tcam->cls_lo) : -1);
4154 		}
4155 
4156 		if (tcam->repli) {
4157 			if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) {
4158 				printf(" %08x %08x "\
4159 					     "%08x %08x %08x %08x %08x %08x",
4160 					     tcam->rplc[7], tcam->rplc[6],
4161 					     tcam->rplc[5], tcam->rplc[4],
4162 					     tcam->rplc[3], tcam->rplc[2],
4163 					     tcam->rplc[1], tcam->rplc[0]);
4164 			} else {
4165 				printf(" %08x %08x "\
4166 					     "%08x %08x", tcam->rplc[3],
4167 					     tcam->rplc[2], tcam->rplc[1],
4168 					     tcam->rplc[0]);
4169 			}
4170 		} else {
4171 			if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE)
4172 				printf("%72c", ' ');
4173 			else
4174 				printf("%36c", ' ');
4175 		}
4176 		if (is_t6(chip)) {
4177 			printf( "%4u%3u%3u%3u %#x\n",
4178 				     G_T6_SRAM_PRIO0(tcam->cls_lo),
4179 				     G_T6_SRAM_PRIO1(tcam->cls_lo),
4180 				     G_T6_SRAM_PRIO2(tcam->cls_lo),
4181 				     G_T6_SRAM_PRIO3(tcam->cls_lo),
4182 				     (tcam->cls_lo >> S_T6_MULTILISTEN0) & 0xf);
4183 		} else if (is_t5(chip)) {
4184 			printf("%4u%3u%3u%3u %#x\n",
4185 				     G_SRAM_PRIO0(tcam->cls_lo),
4186 				     G_SRAM_PRIO1(tcam->cls_lo),
4187 				     G_SRAM_PRIO2(tcam->cls_lo),
4188 				     G_SRAM_PRIO3(tcam->cls_lo),
4189 				     (tcam->cls_lo >> S_MULTILISTEN0) & 0xf);
4190 		}
4191 	}
4192 
4193 	return rc;
4194 }
4195 
4196 int
view_dump_context(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4197 view_dump_context(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4198 		  struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4199 {
4200 	struct cudbg_buffer c_buff, dc_buff;
4201 	struct cudbg_ch_cntxt *context;
4202 	int rc = 0;
4203 	int n, i;
4204 
4205 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4206 	if (rc)
4207 		return rc;
4208 
4209 	n = dc_buff.size / sizeof(struct cudbg_ch_cntxt);
4210 	context = (struct cudbg_ch_cntxt *)dc_buff.data;
4211 	for (i = 0; i < n; i++, context++) {
4212 		/* Only print valid contexts */
4213 		if (context->cntxt_type != CTXT_CNM) {
4214 			rc = cudbg_sge_ctxt_check_valid(context->data,
4215 							context->cntxt_type);
4216 			if (!rc)
4217 				continue;
4218 		}
4219 
4220 		if (context->cntxt_type == CTXT_EGRESS) {
4221 			if (is_t5(chip))
4222 				rc = show_cntxt(context, t5_egress_cntxt,
4223 						cudbg_poutbuf);
4224 			else if (is_t6(chip))
4225 				rc = show_cntxt(context, t6_egress_cntxt,
4226 						cudbg_poutbuf);
4227 		} else if (context->cntxt_type == CTXT_INGRESS) {
4228 			if (is_t5(chip))
4229 				rc = show_cntxt(context, t5_ingress_cntxt,
4230 						cudbg_poutbuf);
4231 			else if (is_t6(chip))
4232 				rc = show_cntxt(context, t6_ingress_cntxt,
4233 						cudbg_poutbuf);
4234 		} else if (context->cntxt_type == CTXT_CNM)
4235 			rc = show_cntxt(context, t5_cnm_cntxt, cudbg_poutbuf);
4236 		else if (context->cntxt_type == CTXT_FLM) {
4237 			if (is_t5(chip))
4238 				rc = show_cntxt(context, t5_flm_cntxt,
4239 						cudbg_poutbuf);
4240 			else if (is_t6(chip))
4241 				rc = show_cntxt(context, t6_flm_cntxt,
4242 						cudbg_poutbuf);
4243 		}
4244 
4245 		if (rc < 0)
4246 			goto err1;
4247 	}
4248 
4249 err1:
4250 	return rc;
4251 }
4252 
4253 int
view_le_tcam(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4254 view_le_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4255 	     struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4256 {
4257 	char *le_region[] = {
4258 		"active", "server", "filter", "clip", "routing"
4259 	};
4260 	struct cudbg_tid_data *tid_data = NULL;
4261 	struct cudbg_tcam *tcam_region = NULL;
4262 	struct cudbg_buffer c_buff, dc_buff;
4263 	int rc = 0, j;
4264 	u32 i;
4265 
4266 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4267 	if (rc)
4268 		return rc;
4269 
4270 	tcam_region = (struct cudbg_tcam *)dc_buff.data;
4271 	tid_data = (struct cudbg_tid_data *)(tcam_region + 1);
4272 	printf("\n\nRouting table index: 0x%X\n",
4273 		     tcam_region->routing_start);
4274 	printf("Lip comp table index: 0x%X\n",
4275 		     tcam_region->clip_start);
4276 	printf("Filter table index: 0x%X\n",
4277 		     tcam_region->filter_start);
4278 	printf("Server index: 0x%X\n\n",
4279 		     tcam_region->server_start);
4280 
4281 	printf("tid start: %d\n\n", 0);
4282 	printf("tid end: %d\n\n",
4283 		     tcam_region->max_tid);
4284 
4285 	for (i = 0; i < tcam_region->max_tid; i++) {
4286 		printf(
4287 			     "======================================================================================\n");
4288 		printf("This is a LE_DB_DATA_READ "\
4289 			     "command: on TID %d at index %d\n", i, i * 4);
4290 		if (i < tcam_region->server_start / 4) {
4291 			printf("Region: %s\n\n",
4292 				     le_region[0]);
4293 		} else if ((i >= tcam_region->server_start / 4) &&
4294 			   (i < tcam_region->filter_start / 4)) {
4295 			printf("Region: %s\n\n",
4296 				     le_region[1]);
4297 		} else if ((i >= tcam_region->filter_start / 4) &&
4298 			   (i < tcam_region->clip_start / 4)) {
4299 			printf("Region: %s\n\n",
4300 				     le_region[2]);
4301 		} else if ((i >= tcam_region->clip_start / 4) &&
4302 			   (i < tcam_region->routing_start / 4)) {
4303 			printf("Region: %s\n\n",
4304 				     le_region[3]);
4305 		} else if (i >= tcam_region->routing_start / 4) {
4306 			printf("Region: %s\n\n",
4307 				     le_region[4]);
4308 		}
4309 
4310 		printf("READ:\n");
4311 		printf("DBGICMDMODE: %s\n",
4312 			     (tid_data->dbig_conf & 1) ? "LE" : "TCAM");
4313 		printf("READING TID: 0x%X\n",
4314 			     tid_data->tid);
4315 		printf("Write: "\
4316 			     "LE_DB_DBGI_REQ_TCAM_CMD: 0x%X\n",
4317 			     tid_data->dbig_cmd);
4318 		printf("Write: LE_DB_DBGI_CONFIG "\
4319 			     "0x%X\n", tid_data->dbig_conf);
4320 		printf("Polling: LE_DB_DBGI_CONFIG:"\
4321 			     " busy bit\n");
4322 		printf("Read: "\
4323 			     "LE_DB_DBGI_RSP_STATUS: 0x%X [%d]\n",
4324 			     tid_data->dbig_rsp_stat & 1,
4325 			     tid_data->dbig_rsp_stat & 1);
4326 		printf("Read: "\
4327 			     "LE_DB_DBGI_RSP_DATA:\n");
4328 		printf("Response data for TID "\
4329 			     "0x%X:\n", i);
4330 
4331 		for (j = 0; j < CUDBG_NUM_REQ_REGS; j++) {
4332 			printf("\t0x%X: 0x%08X\n",
4333 				     A_LE_DB_DBGI_RSP_DATA + (j << 2),
4334 				     tid_data->data[j]);
4335 		}
4336 
4337 		printf("DATA READ: ");
4338 		for (j = CUDBG_NUM_REQ_REGS - 1; j >= 0; j--) {
4339 			printf("%08X",
4340 				     tid_data->data[j]);
4341 		}
4342 		printf("\n\n");
4343 
4344 		tid_data++;
4345 	}
4346 
4347 	return rc;
4348 }
4349 
4350 int
view_pcie_config(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4351 view_pcie_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4352 		 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4353 {
4354 	struct cudbg_buffer c_buff, dc_buff;
4355 	u32 *pcie_config;
4356 	int rc = 0;
4357 
4358 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4359 	if (rc)
4360 		return rc;
4361 
4362 	if (!cudbg_poutbuf->data)
4363 		printf("\n\t\t\tPCIE CONFIG\n\n");
4364 
4365 	pcie_config = (u32 *)dc_buff.data;
4366 	rc = dump_indirect_regs(t5_pcie_config_ptr[0], 0,
4367 				(const u32 *)pcie_config, cudbg_poutbuf);
4368 
4369 	return rc;
4370 }
4371 
4372 int
view_pcie_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4373 view_pcie_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4374 		   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4375 {
4376 	struct cudbg_buffer c_buff, dc_buff;
4377 	struct ireg_buf *ch_pcie;
4378 	u32 indirect_addr;
4379 	int rc = 0;
4380 	int i = 0;
4381 	int n;
4382 
4383 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4384 	if (rc)
4385 		return rc;
4386 
4387 	if (!cudbg_poutbuf->data)
4388 		printf("\n\nPCIE_PDBG\n\n");
4389 
4390 	indirect_addr = PCIE_PDEBUG_INDIRECT;
4391 	ch_pcie = (struct ireg_buf *)dc_buff.data;
4392 	n = sizeof(t5_pcie_pdbg_array)/(4 * sizeof(u32));
4393 	for (i = 0; i < n; i++) {
4394 		u32 *buff = ch_pcie->outbuf;
4395 
4396 		rc = dump_indirect_regs(t5_pcie_pdbg_ptr[i], indirect_addr,
4397 					(const u32 *) buff, cudbg_poutbuf);
4398 		if (rc < 0)
4399 			goto err1;
4400 		ch_pcie++;
4401 	}
4402 
4403 	if (!cudbg_poutbuf->data)
4404 		printf("\n\nPCIE_CDBG\n\n");
4405 
4406 	indirect_addr = PCIE_CDEBUG_INDIRECT;
4407 	n = sizeof(t5_pcie_cdbg_array)/(4 * sizeof(u32));
4408 	for (i = 0; i < n; i++) {
4409 		u32 *buff = ch_pcie->outbuf;
4410 
4411 		rc = dump_indirect_regs(t5_pcie_cdbg_ptr[i], indirect_addr,
4412 					(const u32 *) buff, cudbg_poutbuf);
4413 		if (rc < 0)
4414 			goto err1;
4415 		ch_pcie++;
4416 	}
4417 
4418 err1:
4419 	return rc;
4420 }
4421 
4422 int
view_tp_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4423 view_tp_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4424 		 struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4425 {
4426 	struct cudbg_buffer c_buff, dc_buff;
4427 	int j = 0, k, l, len, n = 0;
4428 	struct ireg_buf *ch_tp_pio;
4429 	u32 indirect_addr;
4430 	u32 *pkey = NULL;
4431 	int rc = 0;
4432 	int i = 0;
4433 
4434 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4435 	if (rc)
4436 		return rc;
4437 
4438 	ch_tp_pio = (struct ireg_buf *)dc_buff.data;
4439 	l = 0;
4440 
4441 	indirect_addr = TP_PIO;
4442 	if (!cudbg_poutbuf->data)
4443 		printf("\n\nTP_PIO\n\n");
4444 
4445 	if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4446 		n = sizeof(t5_tp_pio_array)/(4 * sizeof(u32));
4447 	else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4448 		n = sizeof(t6_tp_pio_array)/(4 * sizeof(u32));
4449 
4450 	for (i = 0; i < n; i++) {
4451 		u32 *buff = ch_tp_pio->outbuf;
4452 
4453 		if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4454 			rc = dump_indirect_regs(t5_tp_pio_ptr[i], indirect_addr,
4455 						(const u32 *) buff,
4456 						cudbg_poutbuf);
4457 		else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4458 			rc = dump_indirect_regs(t6_tp_pio_ptr[i], indirect_addr,
4459 						(const u32 *) buff,
4460 						cudbg_poutbuf);
4461 
4462 		if (rc < 0)
4463 			goto err1;
4464 
4465 		ch_tp_pio++;
4466 	}
4467 
4468 	indirect_addr = TP_TM_PIO_ADDR;
4469 	if (!cudbg_poutbuf->data)
4470 		printf("\n\nTP_TM_PIO\n\n");
4471 
4472 	l = 0;
4473 	if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4474 		n = sizeof(t5_tp_tm_pio_array)/(4 * sizeof(u32));
4475 	else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4476 		n = sizeof(t6_tp_tm_pio_array)/(4 * sizeof(u32));
4477 
4478 	for (i = 0; i < n; i++) {
4479 		u32 *buff = ch_tp_pio->outbuf;
4480 
4481 		if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4482 			rc = dump_indirect_regs(t5_tp_tm_regs, indirect_addr,
4483 						(const u32 *)buff,
4484 						cudbg_poutbuf);
4485 		else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4486 			rc = dump_indirect_regs(t6_tp_tm_regs, indirect_addr,
4487 						(const u32 *)buff,
4488 						cudbg_poutbuf);
4489 
4490 		if (rc < 0)
4491 			goto err1;
4492 
4493 		ch_tp_pio++;
4494 	}
4495 	indirect_addr = TP_MIB_INDEX;
4496 	if (!cudbg_poutbuf->data)
4497 		printf("\n\nTP_MIB_INDEX\n\n");
4498 
4499 	l = 0;
4500 	if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4501 		n = sizeof(t5_tp_mib_index_array)/(4 * sizeof(u32));
4502 	else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4503 		n = sizeof(t6_tp_mib_index_array)/(4 * sizeof(u32));
4504 	for (i = 0; i < n ; i++) {
4505 		u32 *buff = ch_tp_pio->outbuf;
4506 
4507 		pkey = (u32 *) buff;
4508 		if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
4509 			j = l + t5_tp_mib_index_array[i][3];
4510 		else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
4511 			j = l + t6_tp_mib_index_array[i][3];
4512 
4513 		len = 0;
4514 		for (k = l; k < j; k++) {
4515 			if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) {
4516 				printf("[0x%x:%2s]"\
4517 					     " %-47s %#-10x %u\n",
4518 					     indirect_addr,
4519 					     t5_tp_mib_index_reg_array[k].addr,
4520 					     t5_tp_mib_index_reg_array[k].name,
4521 					     pkey[len], pkey[len]);
4522 			} else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) {
4523 				printf("[0x%x:%2s]"\
4524 					     " %-47s %#-10x %u\n",
4525 					     indirect_addr,
4526 					     t6_tp_mib_index_reg_array[k].addr,
4527 					     t6_tp_mib_index_reg_array[k].name,
4528 					     pkey[len], pkey[len]);
4529 			}
4530 			len++;
4531 		}
4532 		l = k;
4533 		ch_tp_pio++;
4534 	}
4535 
4536 err1:
4537 	return rc;
4538 }
4539 
4540 int
find_index_in_t6_sge_regs(u32 addr)4541 find_index_in_t6_sge_regs(u32 addr)
4542 {
4543 	u32 i = 0;
4544 
4545 	while (t6_sge_regs[i].name) {
4546 		if (t6_sge_regs[i].addr == addr)
4547 			return i;
4548 		i++;
4549 	}
4550 
4551 	return -1;
4552 }
4553 
4554 void
print_t6_sge_reg_value(u32 reg_addr,u32 reg_data,u32 data_value,int idx_map,struct cudbg_buffer * cudbg_poutbuf)4555 print_t6_sge_reg_value(u32 reg_addr, u32 reg_data, u32 data_value,
4556 		       int idx_map, struct cudbg_buffer *cudbg_poutbuf)
4557 {
4558 	struct reg_info *reg_array = &t6_sge_regs[idx_map];
4559 	u32 value;
4560 
4561 	printf("[0x%x:0x%x] %-47s %#-10x %u\n",
4562 		     reg_addr, reg_data, reg_array->name, data_value,
4563 		     data_value);
4564 
4565 	reg_array++;
4566 	while (reg_array->len) {
4567 		value = xtract(data_value, reg_array->addr, reg_array->len);
4568 
4569 		printf("        %-3u:%3u %-47s "\
4570 			     "%#-10x %u\n",
4571 			     reg_array->addr + reg_array->len - 1,
4572 			     reg_array->addr, reg_array->name, value, value);
4573 
4574 		reg_array++;
4575 	}
4576 
4577 
4578 	return;
4579 }
4580 
4581 void
print_sge_qbase(struct sge_qbase_reg_field * sge_qbase,u32 pf_vf_count,int isPF,struct cudbg_buffer * cudbg_poutbuf)4582 print_sge_qbase(struct sge_qbase_reg_field *sge_qbase, u32 pf_vf_count,
4583 		int isPF, struct cudbg_buffer *cudbg_poutbuf)
4584 {
4585 	u32 *data_value;
4586 	u32 f;
4587 	int idx_map0, idx_map1, idx_map2, idx_map3;
4588 
4589 	idx_map0 = find_index_in_t6_sge_regs(sge_qbase->reg_data[0]);
4590 	idx_map1 = find_index_in_t6_sge_regs(sge_qbase->reg_data[1]);
4591 	idx_map2 = find_index_in_t6_sge_regs(sge_qbase->reg_data[2]);
4592 	idx_map3 = find_index_in_t6_sge_regs(sge_qbase->reg_data[3]);
4593 
4594 	if (idx_map0 < 0 || idx_map1 < 0 || idx_map2 < 0 || idx_map3 < 0) {
4595 		printf("Error: one of these addr is "\
4596 			     "wrong: 0x%x 0x%x 0x%x 0x%x\n", sge_qbase->reg_data[0],
4597 			     sge_qbase->reg_data[1], sge_qbase->reg_data[2],
4598 			     sge_qbase->reg_data[3]);
4599 		return;
4600 	}
4601 
4602 	for (f = 0; f < pf_vf_count; f++) {
4603 		if (isPF)
4604 			data_value = (u32 *)sge_qbase->pf_data_value[f];
4605 		else
4606 			data_value = (u32 *)sge_qbase->vf_data_value[f];
4607 		printf("\nSGE_QBASE_INDEX for %s %d\n",
4608 			     isPF ? "pf" : "vf", f);
4609 		print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[0],
4610 				       data_value[0], idx_map0, cudbg_poutbuf);
4611 
4612 		print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[1],
4613 				       data_value[1], idx_map1, cudbg_poutbuf);
4614 
4615 		print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[2],
4616 				       data_value[2], idx_map2, cudbg_poutbuf);
4617 
4618 		print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[3],
4619 				       data_value[3], idx_map3, cudbg_poutbuf);
4620 	}
4621 
4622 	return;
4623 }
4624 
4625 int
view_sge_indirect(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4626 view_sge_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4627 		  struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4628 {
4629 	struct cudbg_buffer c_buff, dc_buff;
4630 	struct sge_qbase_reg_field *sge_qbase;
4631 	u32 indirect_addr;
4632 	u32 *pkey = NULL;
4633 	int j, k, len;
4634 	int rc = 0;
4635 	int i = 0;
4636 	int l = 0;
4637 
4638 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4639 	if (rc)
4640 		return rc;
4641 
4642 	pkey = (u32 *) (dc_buff.data + sizeof(struct ireg_field));
4643 	indirect_addr = SGE_DEBUG_DATA_INDIRECT;
4644 	for (i = 0; i < 2; i++) {
4645 		printf("\n");
4646 		j = l + t5_sge_dbg_index_array[i][3];
4647 		len = 0;
4648 		for (k = l; k < j; k++) {
4649 			if (i == 0) {
4650 				printf("[0x%x:0x%x]"\
4651 					     "  %-47s %#-10x %u\n",
4652 					     indirect_addr,
4653 					     sge_debug_data_high[k].addr,
4654 					     sge_debug_data_high[k].name,
4655 					     pkey[len], pkey[len]);
4656 			} else {
4657 				printf("[0x%x:0x%x]"\
4658 					     " %-47s %#-10x %u\n",
4659 					     indirect_addr,
4660 					     sge_debug_data_low[k].addr,
4661 					     sge_debug_data_low[k].name,
4662 					     pkey[len], pkey[len]);
4663 			}
4664 			len++;
4665 		}
4666 		pkey = (u32 *)((char *)pkey + sizeof(struct ireg_buf));
4667 	}
4668 
4669 	if (is_t6(chip)) {
4670 		dc_buff.offset = 2 * sizeof(struct ireg_buf);
4671 
4672 		if (dc_buff.size <= dc_buff.offset)
4673 			goto err1;
4674 
4675 		sge_qbase = (struct sge_qbase_reg_field *)(dc_buff.data +
4676 							   dc_buff.offset);
4677 		print_sge_qbase(sge_qbase, 8, 1, cudbg_poutbuf);
4678 		print_sge_qbase(sge_qbase, sge_qbase->vfcount, 0,
4679 				cudbg_poutbuf);
4680 	}
4681 
4682 err1:
4683 	return rc;
4684 }
4685 
4686 static int
view_full_t6(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)4687 view_full_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4688 	     struct cudbg_buffer *cudbg_poutbuf)
4689 {
4690 	u32 pcie_c0rd_full, pcie_c0wr_full, pcie_c0rsp_full;
4691 	u32 pcie_c1rd_full, pcie_c1wr_full, pcie_c1rsp_full;
4692 	u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng;
4693 	u32 tx, rx, cs, es, pcie, pcie1, sge;
4694 	struct cudbg_buffer c_buff, dc_buff;
4695 	u32 sge_req_full = 0, sge_rx_full;
4696 	u32 cng0, cng1;
4697 	int rc = 0;
4698 	u32 *sp;
4699 
4700 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4701 	if (rc)
4702 		return rc;
4703 
4704 	sp = (u32 *)dc_buff.data;
4705 
4706 	/* Collect Registers:
4707 	 * TP_DBG_SCHED_TX (0x7e40 + 0x6a),
4708 	 * TP_DBG_SCHED_RX (0x7e40 + 0x6b),
4709 	 * TP_DBG_CSIDE_INT (0x7e40 + 0x23f),
4710 	 * TP_DBG_ESIDE_INT (0x7e40 + 0x148),
4711 	 * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2),
4712 	 * PCIE_CDEBUG_INDEX[AppData1] (0x5a10 + 3),
4713 	 * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8)
4714 	 **/
4715 	tx = *sp;
4716 	rx = *(sp + 1);
4717 	cs = *(sp + 2);
4718 	es = *(sp + 3);
4719 	pcie = *(sp + 4);
4720 	pcie1 = *(sp + 5);
4721 	sge = *(sp + 6);
4722 
4723 	pcie_c0wr_full = pcie & 1;
4724 	pcie_c0rd_full = (pcie >> 2) & 1;
4725 	pcie_c0rsp_full = (pcie >> 4) & 1;
4726 
4727 	pcie_c1wr_full = pcie1 & 1;
4728 	pcie_c1rd_full = (pcie1 >> 2) & 1;
4729 	pcie_c1rsp_full = (pcie1 >> 4) & 1;
4730 
4731 	/* sge debug_PD_RdRspAFull_d for each channel */
4732 	sge_rx_full = (sge >> 30) & 0x3;
4733 
4734 	rx_fifo_cng = (rx >> 20) & 0xf;
4735 	rx_pcmd_cng = (rx >> 14) & 0x3;
4736 	rx_hdr_cng = (rx >> 8) & 0xf;
4737 	cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1);
4738 	cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) |
4739 		((rx_hdr_cng & 2) >> 1);
4740 
4741 	printf("\n");
4742 	/* TP resource reservation */
4743 	printf("Tx0 ==%1u=>  T  <=%1u= Rx0\n",
4744 		     ((tx >> 28) & 1), ((rx >> 28) & 1));
4745 	printf("Tx1 ==%1u=>  P  <=%1u= Rx1\n",
4746 		     ((tx >> 29) & 1), ((rx >> 29) & 1));
4747 	printf("\n");
4748 
4749 	/* TX path */
4750 	/* pcie bits 19:16 are D_RspAFull for each channel */
4751 	/* Tx is blocked when Responses from system cannot flow toward TP. */
4752 	printf("Tx0 P =%1u=> S ? U =>%1u=>  T\n",
4753 		     pcie_c0rsp_full, ((cs >> 24) & 1));
4754 	printf("Tx1 C =%1u=> G ? T =>%1u=>  P\n",
4755 		     pcie_c1rsp_full, ((cs >> 25) & 1));
4756 
4757 	/* RX path */
4758 	/* Rx is blocked when sge and/or pcie cannot send requests to system.
4759 	 * */
4760 	printf("       Rd Wr\n");
4761 	printf("RX0 P <=%1u=%1u=%1u S <=%1u= C "\
4762 		     "<=%1u= T <=T <=%1u=  T <=%1u= M\n",
4763 		     ((pcie_c0rd_full >> 0) & 1), ((pcie_c0wr_full >> 0) & 1),
4764 		     ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1),
4765 		     cng0, ((cs >> 20) & 1), ((es >> 16) & 1));
4766 #ifndef __CHECKER__
4767 	printf("RX1 C <=%1u=%1u=%1u G <=%1u= X "\
4768 		     "<=%1u= C <=P <=%1u=  E <=%1u= P\n",
4769 		     ((pcie_c1rd_full >> 1) & 1), ((pcie_c1wr_full >> 1) & 1),
4770 		     ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1),
4771 		     cng1, ((cs >> 21) & 1), ((es >> 17) & 1));
4772 #endif
4773 	printf("\n");
4774 
4775 
4776 	return rc;
4777 }
4778 
4779 static int
view_full_t5(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf)4780 view_full_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4781 	     struct cudbg_buffer *cudbg_poutbuf)
4782 {
4783 	u32 sge_rsp_full, sge_req_full, sge_rx_full;
4784 	u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng;
4785 	struct cudbg_buffer c_buff, dc_buff;
4786 	u32 pcie_rd_full, pcie_wr_full;
4787 	u32 tx, rx, cs, es, pcie, sge;
4788 	u32 cng0, cng1;
4789 	int rc = 0;
4790 	u32 *sp;
4791 
4792 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4793 	if (rc)
4794 		return rc;
4795 
4796 	sp = (u32 *)dc_buff.data;
4797 
4798 	/* Collect Registers:
4799 	 * TP_DBG_SCHED_TX (0x7e40 + 0x6a),
4800 	 * TP_DBG_SCHED_RX (0x7e40 + 0x6b),
4801 	 * TP_DBG_CSIDE_INT (0x7e40 + 0x23f),
4802 	 * TP_DBG_ESIDE_INT (0x7e40 + 0x148),
4803 	 * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2),
4804 	 * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8)
4805 	 **/
4806 	tx = *sp;
4807 	rx = *(sp + 1);
4808 	cs = *(sp + 2);
4809 	es = *(sp + 3);
4810 	pcie = *(sp + 4);
4811 	sge = *(sp + 5);
4812 
4813 	pcie_rd_full = (pcie >> 8) & 0xf;
4814 	pcie_wr_full = pcie & 0xf;
4815 
4816 	/* OR together D_RdReqAFull and D_WrReqAFull for pcie */
4817 
4818 	/* sge debug_PD_RdRspAFull_d for each channel */
4819 	sge_rsp_full = ((sge >> 26) & 0xf);
4820 	/* OR together sge debug_PD_RdReqAFull_d and debug PD_WrReqAFull_d */
4821 	sge_req_full = ((sge >> 22) & 0xf) | ((sge >> 18) & 0xf);
4822 	sge_rx_full = (sge >> 30) & 0x3;
4823 
4824 	rx_fifo_cng = (rx >> 20) & 0xf;
4825 	rx_pcmd_cng = (rx >> 14) & 0x3;
4826 	rx_hdr_cng = (rx >> 8) & 0xf;
4827 	cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1);
4828 	cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) |
4829 		((rx_hdr_cng & 2) >> 1);
4830 
4831 	printf("\n");
4832 	/* TP resource reservation */
4833 	printf("Tx0 ==%1u=\\     /=%1u= Rx0\n",
4834 		     ((tx >> 28) & 1), ((rx >> 28) & 1));
4835 	printf("Tx1 ==%1u= | T | =%1u= Rx1\n",
4836 		     ((tx >> 29) & 1), ((rx >> 29) & 1));
4837 	printf("Tx2 ==%1u= | P | =%1u= Rx2\n",
4838 		     ((tx >> 30) & 1), ((rx >> 30) & 1));
4839 	printf("Tx3 ==%1u=/     \\=%1u= Rx3\n",
4840 		     ((tx >> 31) & 1), ((rx >> 31) & 1));
4841 	printf("\n");
4842 
4843 	/* TX path */
4844 	/* pcie bits 19:16 are D_RspAFull for each channel */
4845 	/* Tx is blocked when Responses from system cannot flow toward TP. */
4846 	printf("Tx0 P =%1u=%1u=\\ S ? U ==%1u=\\\n",
4847 		     ((pcie >> 16) & 1), (sge_rsp_full & 1), ((cs >> 24) & 1));
4848 	printf("Tx1 C =%1u=%1u= |G ? T ==%1u= | T\n",
4849 		     ((pcie >> 17) & 1), ((sge_rsp_full >> 1) & 1),
4850 		     ((cs >> 25) & 1));
4851 	printf("Tx2 I =%1u=%1u= |E ? X ==%1u= | P\n",
4852 		     ((pcie >> 18) & 1), ((sge_rsp_full >> 2) & 1),
4853 		     ((cs >> 26) & 1));
4854 	printf("Tx3 E =%1u=%1u=/   ?   ==%1u=/\n",
4855 		     ((pcie >> 19) & 1), ((sge_rsp_full >> 3) & 1),
4856 		     ((cs >> 27) & 1));
4857 	printf("\n");
4858 
4859 	/* RX path */
4860 	/* Rx is blocked when sge and/or pcie cannot send requests to system.
4861 	 * */
4862 	printf("       Rd Wr\n");
4863 	printf("RX0 P /=%1u=%1u=%1u S <=%1u= C "\
4864 		     "<=%1u= T <=T <=%1u=  T /=%1u= M\n",
4865 		     ((pcie_rd_full >> 0) & 1), ((pcie_wr_full >> 0) & 1),
4866 		     ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1),
4867 		     cng0, ((cs >> 20) & 1), ((es >> 16) & 1));
4868 	printf("RX1 C| =%1u=%1u=%1u G <=%1u= X "\
4869 		     "<=%1u= C <=P <=%1u=  E| =%1u= P\n",
4870 		     ((pcie_rd_full >> 1) & 1), ((pcie_wr_full >> 1) & 1),
4871 		     ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1),
4872 		     cng1, ((cs >> 21) & 1), ((es >> 17) & 1));
4873 	printf("RX2 I| =%1u=%1u=%1u E             "\
4874 		     "             | =%1u= S\n",
4875 		     ((pcie_rd_full >> 2) & 1), ((pcie_wr_full >> 2) & 1),
4876 		     ((sge_req_full >> 2) & 1), ((es >> 18) & 1));
4877 	printf("RX3 E \\=%1u=%1u=%1u               "\
4878 		     "              \\=%1u=\n",
4879 		     ((pcie_rd_full >> 3) & 1), ((pcie_wr_full >> 3) & 1),
4880 		     ((sge_req_full >> 3) & 1), ((es >> 19) & 1));
4881 	printf("\n");
4882 
4883 	return rc;
4884 }
4885 
4886 int
view_full(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4887 view_full(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4888 	  struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4889 {
4890 	int rc = -1;
4891 
4892 	if (is_t5(chip))
4893 		rc = view_full_t5(pbuf, entity_hdr, cudbg_poutbuf);
4894 	else if (is_t6(chip))
4895 		rc = view_full_t6(pbuf, entity_hdr, cudbg_poutbuf);
4896 
4897 	return rc;
4898 }
4899 
4900 int
view_vpd_data(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4901 view_vpd_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4902 	      struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4903 {
4904 	struct cudbg_buffer c_buff, dc_buff;
4905 	struct struct_vpd_data *vpd_data;
4906 	int rc = 0;
4907 
4908 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4909 	if (rc)
4910 		return rc;
4911 
4912 	vpd_data = (struct struct_vpd_data *) dc_buff.data;
4913 	printf("MN %s\n", vpd_data->mn);
4914 	printf("SN %s\n", vpd_data->sn);
4915 	printf("BN %s\n", vpd_data->bn);
4916 	printf("NA %s\n", vpd_data->na);
4917 	printf("SCFG Version 0x%x\n",
4918 		     vpd_data->scfg_vers);
4919 	printf("VPD Version  0x%x\n",
4920 		     vpd_data->vpd_vers);
4921 
4922 	printf("Firmware Version: %d.%d.%d.%d\n",
4923 		    vpd_data->fw_major, vpd_data->fw_minor, vpd_data->fw_micro,
4924 		    vpd_data->fw_build);
4925 
4926 	return rc;
4927 }
4928 
4929 int
view_upload(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)4930 view_upload(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
4931 	    struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
4932 {
4933 	struct cudbg_buffer c_buff, dc_buff;
4934 	int rc = 0;
4935 	u32 *value;
4936 
4937 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
4938 	if (rc)
4939 		return rc;
4940 
4941 	value = (u32 *) dc_buff.data;
4942 	if (*value == 0xffffffff) {
4943 		printf("uP load: <not available>\n");
4944 		goto err1;
4945 	}
4946 
4947 	printf("uP load: %d, %d, %d\n",
4948 		     (*value >>  0) & 0xff,
4949 		     (*value >>  8) & 0xff,
4950 		     (*value >> 16) & 0xff);
4951 
4952 err1:
4953 	return rc;
4954 }
4955 
4956 static const char *
cudbg_qdesc_qtype_to_str(enum cudbg_qdesc_qtype qtype)4957 cudbg_qdesc_qtype_to_str(enum cudbg_qdesc_qtype qtype)
4958 {
4959 	switch (qtype) {
4960 	case CUDBG_QTYPE_NIC_TXQ:
4961 		return "ETHERNET-TXQ";
4962 	case CUDBG_QTYPE_NIC_RXQ:
4963 		return "ETHERNET-RXQ";
4964 	case CUDBG_QTYPE_NIC_FLQ:
4965 		return "ETHERNET-FL";
4966 	case CUDBG_QTYPE_CTRLQ:
4967 		return "ETHERNET-CTRLQ";
4968 	case CUDBG_QTYPE_FWEVTQ:
4969 		return "FIRMWARE-EVENT-QUEUE";
4970 	case CUDBG_QTYPE_INTRQ:
4971 		return "NON-DATA-INTERRUPT-QUEUE";
4972 	case CUDBG_QTYPE_PTP_TXQ:
4973 		return "PTP-TXQ";
4974 	case CUDBG_QTYPE_OFLD_TXQ:
4975 		return "OFFLOAD-TXQ";
4976 	case CUDBG_QTYPE_RDMA_RXQ:
4977 		return "RDMA-RXQ";
4978 	case CUDBG_QTYPE_RDMA_FLQ:
4979 		return "RDMA-FL";
4980 	case CUDBG_QTYPE_RDMA_CIQ:
4981 		return "RDMA-CIQ";
4982 	case CUDBG_QTYPE_ISCSI_RXQ:
4983 		return "iSCSI-RXQ";
4984 	case CUDBG_QTYPE_ISCSI_FLQ:
4985 		return "iSCSI-FL";
4986 	case CUDBG_QTYPE_ISCSIT_RXQ:
4987 		return "iSCSIT-RXQ";
4988 	case CUDBG_QTYPE_ISCSIT_FLQ:
4989 		return "iSCSIT-FL";
4990 	case CUDBG_QTYPE_CRYPTO_TXQ:
4991 		return "CRYPTO-TXQ";
4992 	case CUDBG_QTYPE_CRYPTO_RXQ:
4993 		return "CRYPTO-RXQ";
4994 	case CUDBG_QTYPE_CRYPTO_FLQ:
4995 		return "CRYPTO-FL";
4996 	case CUDBG_QTYPE_TLS_RXQ:
4997 		return "TLS-RXQ";
4998 	case CUDBG_QTYPE_TLS_FLQ:
4999 		return "TLS-FL";
5000 	case CUDBG_QTYPE_UNKNOWN:
5001 	case CUDBG_QTYPE_MAX:
5002 		return "UNKNOWN";
5003 	}
5004 
5005 	return "UNKNOWN";
5006 }
5007 
5008 static struct cudbg_qdesc_entry *
cudbg_next_qdesc(struct cudbg_qdesc_entry * e)5009 cudbg_next_qdesc(struct cudbg_qdesc_entry *e)
5010 {
5011 	return (struct cudbg_qdesc_entry *)
5012 	       ((u8 *)e + sizeof(*e) + e->data_size);
5013 }
5014 
5015 int
view_qdesc(char * pbuf,struct cudbg_entity_hdr * entity_hdr,struct cudbg_buffer * cudbg_poutbuf,enum chip_type chip)5016 view_qdesc(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
5017 	   struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
5018 {
5019 	struct cudbg_qdesc_entry *qdesc_entry;
5020 	struct cudbg_qdesc_info *qdesc_info;
5021 	struct cudbg_buffer c_buff, dc_buff;
5022 	u8 zero_memory_128[128] = { 0 };
5023 	struct cudbg_ver_hdr *ver_hdr;
5024 	u32 i, j, k, l, max_desc;
5025 	u32 star_count = 0;
5026 	int rc = 0;
5027 	u8 *p;
5028 
5029 	rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
5030 	if (rc)
5031 		return rc;
5032 
5033 	ver_hdr = (struct cudbg_ver_hdr *)dc_buff.data;
5034 	qdesc_info = (struct cudbg_qdesc_info *)
5035 		     (dc_buff.data + sizeof(*ver_hdr));
5036 
5037 	if (!qdesc_info->num_queues) {
5038 		printf("No queues found\n");
5039 		goto err1;
5040 	}
5041 
5042 	qdesc_entry = (struct cudbg_qdesc_entry *)
5043 		      ((u8 *)qdesc_info + ver_hdr->size);
5044 
5045 	for (i = 0; i < qdesc_info->num_queues; i++) {
5046 		star_count = 0;
5047 		printf(
5048 			     "\n\nQueue - %s, context-id: %u, desc-size: %u, desc-num: %u\n",
5049 			     cudbg_qdesc_qtype_to_str(qdesc_entry->qtype),
5050 			     qdesc_entry->qid,
5051 			     qdesc_entry->desc_size,
5052 			     qdesc_entry->num_desc);
5053 		p = (u8 *)qdesc_entry + qdesc_info->qdesc_entry_size;
5054 
5055 		for (j = 0; j < qdesc_entry->num_desc; j++) {
5056 			k = 0;
5057 			/* Below logic skips printing descriptors filled with
5058 			 * all zeros and replaces it with star
5059 			 */
5060 			if (!memcmp(p, zero_memory_128, qdesc_entry->desc_size)) {
5061 				star_count++;
5062 				if (star_count >= 2 &&
5063 				    j != (qdesc_entry->num_desc - 1)) {
5064 					/* Skip all consecutive descriptors
5065 					 * filled with zeros until the last
5066 					 * descriptor.
5067 					 */
5068 					p += qdesc_entry->desc_size;
5069 
5070 					if (star_count == 2) {
5071 						/* Print * for the second
5072 						 * consecutive descriptor
5073 						 * filled with zeros.
5074 						 */
5075 						printf("\n%-8s\n", "*");
5076 					}
5077 					continue;
5078 				}
5079 			} else {
5080 				/* Descriptor doesn't contain all zeros, so
5081 				 * restart skip logic.
5082 				 */
5083 				star_count = 0;
5084 			}
5085 
5086 			printf("\n%-8d:", j);
5087 			while (k < qdesc_entry->desc_size) {
5088 				max_desc = min(qdesc_entry->desc_size - k,
5089 					       sizeof(u32));
5090 				if (k && !(k % 32))
5091 					printf("\n%-9s", " ");
5092 				if (!(k % 4))
5093 					printf(" ");
5094 				for (l = 0; l < max_desc; l++, k++, p++)
5095 					printf("%02x", *p);
5096 			}
5097 		}
5098 		qdesc_entry = cudbg_next_qdesc(qdesc_entry);
5099 	}
5100 
5101 err1:
5102 	return rc;
5103 }
5104