1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 #ifndef __FreeBSD__ 46 #include <sys/filio.h> 47 #endif 48 49 #ifndef WITHOUT_CAPSICUM 50 #include <capsicum_helpers.h> 51 #endif 52 #include <err.h> 53 #include <errno.h> 54 #include <fcntl.h> 55 #include <md5.h> 56 #include <stdio.h> 57 #include <stdlib.h> 58 #include <string.h> 59 #include <sysexits.h> 60 #include <unistd.h> 61 #include <pthread.h> 62 #include <pthread_np.h> 63 64 #include "e1000_regs.h" 65 #include "e1000_defines.h" 66 #include "mii.h" 67 68 #include "bhyverun.h" 69 #include "pci_emul.h" 70 #include "mevent.h" 71 72 /* Hardware/register definitions XXX: move some to common code. */ 73 #define E82545_VENDOR_ID_INTEL 0x8086 74 #define E82545_DEV_ID_82545EM_COPPER 0x100F 75 #define E82545_SUBDEV_ID 0x1008 76 77 #define E82545_REVISION_4 4 78 79 #define E82545_MDIC_DATA_MASK 0x0000FFFF 80 #define E82545_MDIC_OP_MASK 0x0c000000 81 #define E82545_MDIC_IE 0x20000000 82 83 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 84 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 85 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 86 87 #define E82545_BAR_REGISTER 0 88 #define E82545_BAR_REGISTER_LEN (128*1024) 89 #define E82545_BAR_FLASH 1 90 #define E82545_BAR_FLASH_LEN (64*1024) 91 #define E82545_BAR_IO 2 92 #define E82545_BAR_IO_LEN 8 93 94 #define E82545_IOADDR 0x00000000 95 #define E82545_IODATA 0x00000004 96 #define E82545_IO_REGISTER_MAX 0x0001FFFF 97 #define E82545_IO_FLASH_BASE 0x00080000 98 #define E82545_IO_FLASH_MAX 0x000FFFFF 99 100 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 101 #define E82545_RAR_MAX 15 102 #define E82545_MTA_MAX 127 103 #define E82545_VFTA_MAX 127 104 105 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 106 * followed by 6 address bits. 107 * TODO: make opcode bits and addr bits configurable? 108 * NVM Commands - Microwire */ 109 #define E82545_NVM_OPCODE_BITS 3 110 #define E82545_NVM_ADDR_BITS 6 111 #define E82545_NVM_DATA_BITS 16 112 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 113 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 114 #define E82545_NVM_OPCODE_MASK \ 115 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 116 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 117 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 118 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 119 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 120 121 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 122 123 #define E1000_ICR_SRPD 0x00010000 124 125 /* This is an arbitrary number. There is no hard limit on the chip. */ 126 #define I82545_MAX_TXSEGS 64 127 128 /* Legacy receive descriptor */ 129 struct e1000_rx_desc { 130 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 131 uint16_t length; /* Length of data DMAed into data buffer */ 132 uint16_t csum; /* Packet checksum */ 133 uint8_t status; /* Descriptor status */ 134 uint8_t errors; /* Descriptor Errors */ 135 uint16_t special; 136 }; 137 138 /* Transmit descriptor types */ 139 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 140 #define E1000_TXD_TYP_L (0) 141 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 142 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 143 144 /* Legacy transmit descriptor */ 145 struct e1000_tx_desc { 146 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 147 union { 148 uint32_t data; 149 struct { 150 uint16_t length; /* Data buffer length */ 151 uint8_t cso; /* Checksum offset */ 152 uint8_t cmd; /* Descriptor control */ 153 } flags; 154 } lower; 155 union { 156 uint32_t data; 157 struct { 158 uint8_t status; /* Descriptor status */ 159 uint8_t css; /* Checksum start */ 160 uint16_t special; 161 } fields; 162 } upper; 163 }; 164 165 /* Context descriptor */ 166 struct e1000_context_desc { 167 union { 168 uint32_t ip_config; 169 struct { 170 uint8_t ipcss; /* IP checksum start */ 171 uint8_t ipcso; /* IP checksum offset */ 172 uint16_t ipcse; /* IP checksum end */ 173 } ip_fields; 174 } lower_setup; 175 union { 176 uint32_t tcp_config; 177 struct { 178 uint8_t tucss; /* TCP checksum start */ 179 uint8_t tucso; /* TCP checksum offset */ 180 uint16_t tucse; /* TCP checksum end */ 181 } tcp_fields; 182 } upper_setup; 183 uint32_t cmd_and_length; 184 union { 185 uint32_t data; 186 struct { 187 uint8_t status; /* Descriptor status */ 188 uint8_t hdr_len; /* Header length */ 189 uint16_t mss; /* Maximum segment size */ 190 } fields; 191 } tcp_seg_setup; 192 }; 193 194 /* Data descriptor */ 195 struct e1000_data_desc { 196 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 197 union { 198 uint32_t data; 199 struct { 200 uint16_t length; /* Data buffer length */ 201 uint8_t typ_len_ext; 202 uint8_t cmd; 203 } flags; 204 } lower; 205 union { 206 uint32_t data; 207 struct { 208 uint8_t status; /* Descriptor status */ 209 uint8_t popts; /* Packet Options */ 210 uint16_t special; 211 } fields; 212 } upper; 213 }; 214 215 union e1000_tx_udesc { 216 struct e1000_tx_desc td; 217 struct e1000_context_desc cd; 218 struct e1000_data_desc dd; 219 }; 220 221 /* Tx checksum info for a packet. */ 222 struct ck_info { 223 int ck_valid; /* ck_info is valid */ 224 uint8_t ck_start; /* start byte of cksum calcuation */ 225 uint8_t ck_off; /* offset of cksum insertion */ 226 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 227 }; 228 229 /* 230 * Debug printf 231 */ 232 static int e82545_debug = 0; 233 #define DPRINTF(msg,params...) if (e82545_debug) fprintf(stderr, "e82545: " msg, params) 234 #define WPRINTF(msg,params...) fprintf(stderr, "e82545: " msg, params) 235 236 #define MIN(a,b) (((a)<(b))?(a):(b)) 237 #define MAX(a,b) (((a)>(b))?(a):(b)) 238 239 /* s/w representation of the RAL/RAH regs */ 240 struct eth_uni { 241 int eu_valid; 242 int eu_addrsel; 243 struct ether_addr eu_eth; 244 }; 245 246 247 struct e82545_softc { 248 struct pci_devinst *esc_pi; 249 struct vmctx *esc_ctx; 250 struct mevent *esc_mevp; 251 struct mevent *esc_mevpitr; 252 pthread_mutex_t esc_mtx; 253 struct ether_addr esc_mac; 254 int esc_tapfd; 255 256 /* General */ 257 uint32_t esc_CTRL; /* x0000 device ctl */ 258 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 259 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 260 uint32_t esc_FCT; /* x0030 flow ctl type */ 261 uint32_t esc_VET; /* x0038 VLAN eth type */ 262 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 263 uint32_t esc_LEDCTL; /* x0E00 LED control */ 264 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 265 266 /* Interrupt control */ 267 int esc_irq_asserted; 268 uint32_t esc_ICR; /* x00C0 cause read/clear */ 269 uint32_t esc_ITR; /* x00C4 intr throttling */ 270 uint32_t esc_ICS; /* x00C8 cause set */ 271 uint32_t esc_IMS; /* x00D0 mask set/read */ 272 uint32_t esc_IMC; /* x00D8 mask clear */ 273 274 /* Transmit */ 275 union e1000_tx_udesc *esc_txdesc; 276 struct e1000_context_desc esc_txctx; 277 pthread_t esc_tx_tid; 278 pthread_cond_t esc_tx_cond; 279 int esc_tx_enabled; 280 int esc_tx_active; 281 uint32_t esc_TXCW; /* x0178 transmit config */ 282 uint32_t esc_TCTL; /* x0400 transmit ctl */ 283 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 284 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 285 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 286 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 287 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 288 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 289 uint16_t esc_TDH; /* x3810 desc table head idx */ 290 uint16_t esc_TDHr; /* internal read version of TDH */ 291 uint16_t esc_TDT; /* x3818 desc table tail idx */ 292 uint32_t esc_TIDV; /* x3820 intr delay */ 293 uint32_t esc_TXDCTL; /* x3828 desc control */ 294 uint32_t esc_TADV; /* x382C intr absolute delay */ 295 296 /* L2 frame acceptance */ 297 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 298 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 299 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 300 301 /* Receive */ 302 struct e1000_rx_desc *esc_rxdesc; 303 pthread_cond_t esc_rx_cond; 304 int esc_rx_enabled; 305 int esc_rx_active; 306 int esc_rx_loopback; 307 uint32_t esc_RCTL; /* x0100 receive ctl */ 308 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 309 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 310 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 311 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 312 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 313 uint32_t esc_RDLEN; /* x2808 #descriptors */ 314 uint16_t esc_RDH; /* x2810 desc table head idx */ 315 uint16_t esc_RDT; /* x2818 desc table tail idx */ 316 uint32_t esc_RDTR; /* x2820 intr delay */ 317 uint32_t esc_RXDCTL; /* x2828 desc control */ 318 uint32_t esc_RADV; /* x282C intr absolute delay */ 319 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 320 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 321 322 /* IO Port register access */ 323 uint32_t io_addr; 324 325 /* Shadow copy of MDIC */ 326 uint32_t mdi_control; 327 /* Shadow copy of EECD */ 328 uint32_t eeprom_control; 329 /* Latest NVM in/out */ 330 uint16_t nvm_data; 331 uint16_t nvm_opaddr; 332 /* stats */ 333 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 334 uint32_t pkt_rx_by_size[6]; 335 uint32_t pkt_tx_by_size[6]; 336 uint32_t good_pkt_rx_count; 337 uint32_t bcast_pkt_rx_count; 338 uint32_t mcast_pkt_rx_count; 339 uint32_t good_pkt_tx_count; 340 uint32_t bcast_pkt_tx_count; 341 uint32_t mcast_pkt_tx_count; 342 uint32_t oversize_rx_count; 343 uint32_t tso_tx_count; 344 uint64_t good_octets_rx; 345 uint64_t good_octets_tx; 346 uint64_t missed_octets; /* counts missed and oversized */ 347 348 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 349 uint8_t nvm_mode:2; 350 #define E82545_NVM_MODE_OPADDR 0x0 351 #define E82545_NVM_MODE_DATAIN 0x1 352 #define E82545_NVM_MODE_DATAOUT 0x2 353 /* EEPROM data */ 354 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 355 }; 356 357 static void e82545_reset(struct e82545_softc *sc, int dev); 358 static void e82545_rx_enable(struct e82545_softc *sc); 359 static void e82545_rx_disable(struct e82545_softc *sc); 360 #ifdef __FreeBSD__ 361 static void e82545_tap_callback(int fd, enum ev_type type, void *param); 362 #endif 363 static void e82545_tx_start(struct e82545_softc *sc); 364 static void e82545_tx_enable(struct e82545_softc *sc); 365 static void e82545_tx_disable(struct e82545_softc *sc); 366 367 static inline int 368 e82545_size_stat_index(uint32_t size) 369 { 370 if (size <= 64) { 371 return 0; 372 } else if (size >= 1024) { 373 return 5; 374 } else { 375 /* should be 1-4 */ 376 return (ffs(size) - 6); 377 } 378 } 379 380 static void 381 e82545_init_eeprom(struct e82545_softc *sc) 382 { 383 uint16_t checksum, i; 384 385 /* mac addr */ 386 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 387 (((uint16_t)sc->esc_mac.octet[1]) << 8); 388 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 389 (((uint16_t)sc->esc_mac.octet[3]) << 8); 390 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 391 (((uint16_t)sc->esc_mac.octet[5]) << 8); 392 393 /* pci ids */ 394 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 395 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 396 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 397 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 398 399 /* fill in the checksum */ 400 checksum = 0; 401 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 402 checksum += sc->eeprom_data[i]; 403 } 404 checksum = NVM_SUM - checksum; 405 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 406 DPRINTF("eeprom checksum: 0x%x\r\n", checksum); 407 } 408 409 static void 410 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 411 uint8_t phy_addr, uint32_t data) 412 { 413 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x\r\n", reg_addr, phy_addr, data); 414 } 415 416 static uint32_t 417 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 418 uint8_t phy_addr) 419 { 420 //DPRINTF("Read mdi reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 421 switch (reg_addr) { 422 case PHY_STATUS: 423 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 424 MII_SR_AUTONEG_COMPLETE); 425 case PHY_AUTONEG_ADV: 426 return NWAY_AR_SELECTOR_FIELD; 427 case PHY_LP_ABILITY: 428 return 0; 429 case PHY_1000T_STATUS: 430 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 431 SR_1000T_LOCAL_RX_STATUS); 432 case PHY_ID1: 433 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 434 case PHY_ID2: 435 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 436 default: 437 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 438 return 0; 439 } 440 /* not reached */ 441 } 442 443 static void 444 e82545_eecd_strobe(struct e82545_softc *sc) 445 { 446 /* Microwire state machine */ 447 /* 448 DPRINTF("eeprom state machine srtobe " 449 "0x%x 0x%x 0x%x 0x%x\r\n", 450 sc->nvm_mode, sc->nvm_bits, 451 sc->nvm_opaddr, sc->nvm_data);*/ 452 453 if (sc->nvm_bits == 0) { 454 DPRINTF("eeprom state machine not expecting data! " 455 "0x%x 0x%x 0x%x 0x%x\r\n", 456 sc->nvm_mode, sc->nvm_bits, 457 sc->nvm_opaddr, sc->nvm_data); 458 return; 459 } 460 sc->nvm_bits--; 461 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 462 /* shifting out */ 463 if (sc->nvm_data & 0x8000) { 464 sc->eeprom_control |= E1000_EECD_DO; 465 } else { 466 sc->eeprom_control &= ~E1000_EECD_DO; 467 } 468 sc->nvm_data <<= 1; 469 if (sc->nvm_bits == 0) { 470 /* read done, back to opcode mode. */ 471 sc->nvm_opaddr = 0; 472 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 473 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 474 } 475 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 476 /* shifting in */ 477 sc->nvm_data <<= 1; 478 if (sc->eeprom_control & E1000_EECD_DI) { 479 sc->nvm_data |= 1; 480 } 481 if (sc->nvm_bits == 0) { 482 /* eeprom write */ 483 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 484 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 485 if (op != E82545_NVM_OPCODE_WRITE) { 486 DPRINTF("Illegal eeprom write op 0x%x\r\n", 487 sc->nvm_opaddr); 488 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 489 DPRINTF("Illegal eeprom write addr 0x%x\r\n", 490 sc->nvm_opaddr); 491 } else { 492 DPRINTF("eeprom write eeprom[0x%x] = 0x%x\r\n", 493 addr, sc->nvm_data); 494 sc->eeprom_data[addr] = sc->nvm_data; 495 } 496 /* back to opcode mode */ 497 sc->nvm_opaddr = 0; 498 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 499 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 500 } 501 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 502 sc->nvm_opaddr <<= 1; 503 if (sc->eeprom_control & E1000_EECD_DI) { 504 sc->nvm_opaddr |= 1; 505 } 506 if (sc->nvm_bits == 0) { 507 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 508 switch (op) { 509 case E82545_NVM_OPCODE_EWEN: 510 DPRINTF("eeprom write enable: 0x%x\r\n", 511 sc->nvm_opaddr); 512 /* back to opcode mode */ 513 sc->nvm_opaddr = 0; 514 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 515 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 516 break; 517 case E82545_NVM_OPCODE_READ: 518 { 519 uint16_t addr = sc->nvm_opaddr & 520 E82545_NVM_ADDR_MASK; 521 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 522 sc->nvm_bits = E82545_NVM_DATA_BITS; 523 if (addr < E82545_NVM_EEPROM_SIZE) { 524 sc->nvm_data = sc->eeprom_data[addr]; 525 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x\r\n", 526 addr, sc->nvm_data); 527 } else { 528 DPRINTF("eeprom illegal read: 0x%x\r\n", 529 sc->nvm_opaddr); 530 sc->nvm_data = 0; 531 } 532 break; 533 } 534 case E82545_NVM_OPCODE_WRITE: 535 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 536 sc->nvm_bits = E82545_NVM_DATA_BITS; 537 sc->nvm_data = 0; 538 break; 539 default: 540 DPRINTF("eeprom unknown op: 0x%x\r\r", 541 sc->nvm_opaddr); 542 /* back to opcode mode */ 543 sc->nvm_opaddr = 0; 544 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 545 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 546 } 547 } 548 } else { 549 DPRINTF("eeprom state machine wrong state! " 550 "0x%x 0x%x 0x%x 0x%x\r\n", 551 sc->nvm_mode, sc->nvm_bits, 552 sc->nvm_opaddr, sc->nvm_data); 553 } 554 } 555 556 #ifdef __FreeBSD__ 557 static void 558 e82545_itr_callback(int fd, enum ev_type type, void *param) 559 { 560 uint32_t new; 561 struct e82545_softc *sc = param; 562 563 pthread_mutex_lock(&sc->esc_mtx); 564 new = sc->esc_ICR & sc->esc_IMS; 565 if (new && !sc->esc_irq_asserted) { 566 DPRINTF("itr callback: lintr assert %x\r\n", new); 567 sc->esc_irq_asserted = 1; 568 pci_lintr_assert(sc->esc_pi); 569 } else { 570 mevent_delete(sc->esc_mevpitr); 571 sc->esc_mevpitr = NULL; 572 } 573 pthread_mutex_unlock(&sc->esc_mtx); 574 } 575 #endif 576 577 static void 578 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 579 { 580 uint32_t new; 581 582 DPRINTF("icr assert: 0x%x\r\n", bits); 583 584 /* 585 * An interrupt is only generated if bits are set that 586 * aren't already in the ICR, these bits are unmasked, 587 * and there isn't an interrupt already pending. 588 */ 589 new = bits & ~sc->esc_ICR & sc->esc_IMS; 590 sc->esc_ICR |= bits; 591 592 if (new == 0) { 593 DPRINTF("icr assert: masked %x, ims %x\r\n", new, sc->esc_IMS); 594 } else if (sc->esc_mevpitr != NULL) { 595 DPRINTF("icr assert: throttled %x, ims %x\r\n", new, sc->esc_IMS); 596 } else if (!sc->esc_irq_asserted) { 597 DPRINTF("icr assert: lintr assert %x\r\n", new); 598 sc->esc_irq_asserted = 1; 599 pci_lintr_assert(sc->esc_pi); 600 if (sc->esc_ITR != 0) { 601 #ifdef __FreeBSD__ 602 sc->esc_mevpitr = mevent_add( 603 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 604 EVF_TIMER, e82545_itr_callback, sc); 605 #endif 606 } 607 } 608 } 609 610 static void 611 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 612 { 613 uint32_t new; 614 615 /* 616 * Changing the mask may allow previously asserted 617 * but masked interrupt requests to generate an interrupt. 618 */ 619 new = bits & sc->esc_ICR & ~sc->esc_IMS; 620 sc->esc_IMS |= bits; 621 622 if (new == 0) { 623 DPRINTF("ims change: masked %x, ims %x\r\n", new, sc->esc_IMS); 624 } else if (sc->esc_mevpitr != NULL) { 625 DPRINTF("ims change: throttled %x, ims %x\r\n", new, sc->esc_IMS); 626 } else if (!sc->esc_irq_asserted) { 627 DPRINTF("ims change: lintr assert %x\n\r", new); 628 sc->esc_irq_asserted = 1; 629 pci_lintr_assert(sc->esc_pi); 630 if (sc->esc_ITR != 0) { 631 #ifdef __FreeBSD__ 632 sc->esc_mevpitr = mevent_add( 633 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 634 EVF_TIMER, e82545_itr_callback, sc); 635 #endif 636 } 637 } 638 } 639 640 static void 641 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 642 { 643 644 DPRINTF("icr deassert: 0x%x\r\n", bits); 645 sc->esc_ICR &= ~bits; 646 647 /* 648 * If there are no longer any interrupt sources and there 649 * was an asserted interrupt, clear it 650 */ 651 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 652 DPRINTF("icr deassert: lintr deassert %x\r\n", bits); 653 pci_lintr_deassert(sc->esc_pi); 654 sc->esc_irq_asserted = 0; 655 } 656 } 657 658 static void 659 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 660 { 661 662 DPRINTF("intr_write: off %x, val %x\n\r", offset, value); 663 664 switch (offset) { 665 case E1000_ICR: 666 e82545_icr_deassert(sc, value); 667 break; 668 case E1000_ITR: 669 sc->esc_ITR = value; 670 break; 671 case E1000_ICS: 672 sc->esc_ICS = value; /* not used: store for debug */ 673 e82545_icr_assert(sc, value); 674 break; 675 case E1000_IMS: 676 e82545_ims_change(sc, value); 677 break; 678 case E1000_IMC: 679 sc->esc_IMC = value; /* for debug */ 680 sc->esc_IMS &= ~value; 681 // XXX clear interrupts if all ICR bits now masked 682 // and interrupt was pending ? 683 break; 684 default: 685 break; 686 } 687 } 688 689 static uint32_t 690 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 691 { 692 uint32_t retval; 693 694 retval = 0; 695 696 DPRINTF("intr_read: off %x\n\r", offset); 697 698 switch (offset) { 699 case E1000_ICR: 700 retval = sc->esc_ICR; 701 sc->esc_ICR = 0; 702 e82545_icr_deassert(sc, ~0); 703 break; 704 case E1000_ITR: 705 retval = sc->esc_ITR; 706 break; 707 case E1000_ICS: 708 /* write-only register */ 709 break; 710 case E1000_IMS: 711 retval = sc->esc_IMS; 712 break; 713 case E1000_IMC: 714 /* write-only register */ 715 break; 716 default: 717 break; 718 } 719 720 return (retval); 721 } 722 723 static void 724 e82545_devctl(struct e82545_softc *sc, uint32_t val) 725 { 726 727 sc->esc_CTRL = val & ~E1000_CTRL_RST; 728 729 if (val & E1000_CTRL_RST) { 730 DPRINTF("e1k: s/w reset, ctl %x\n", val); 731 e82545_reset(sc, 1); 732 } 733 /* XXX check for phy reset ? */ 734 } 735 736 static void 737 e82545_rx_update_rdba(struct e82545_softc *sc) 738 { 739 740 /* XXX verify desc base/len within phys mem range */ 741 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 742 sc->esc_RDBAL; 743 744 /* Cache host mapping of guest descriptor array */ 745 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 746 sc->esc_rdba, sc->esc_RDLEN); 747 } 748 749 static void 750 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 751 { 752 int on; 753 754 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 755 756 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 757 sc->esc_RCTL = val & ~0xF9204c01; 758 759 DPRINTF("rx_ctl - %s RCTL %x, val %x\n", 760 on ? "on" : "off", sc->esc_RCTL, val); 761 762 /* state change requested */ 763 if (on != sc->esc_rx_enabled) { 764 if (on) { 765 /* Catch disallowed/unimplemented settings */ 766 //assert(!(val & E1000_RCTL_LBM_TCVR)); 767 768 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 769 sc->esc_rx_loopback = 1; 770 } else { 771 sc->esc_rx_loopback = 0; 772 } 773 774 e82545_rx_update_rdba(sc); 775 e82545_rx_enable(sc); 776 } else { 777 e82545_rx_disable(sc); 778 sc->esc_rx_loopback = 0; 779 sc->esc_rdba = 0; 780 sc->esc_rxdesc = NULL; 781 } 782 } 783 } 784 785 static void 786 e82545_tx_update_tdba(struct e82545_softc *sc) 787 { 788 789 /* XXX verify desc base/len within phys mem range */ 790 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 791 792 /* Cache host mapping of guest descriptor array */ 793 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 794 sc->esc_TDLEN); 795 } 796 797 static void 798 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 799 { 800 int on; 801 802 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 803 804 /* ignore TCTL_EN settings that don't change state */ 805 if (on == sc->esc_tx_enabled) 806 return; 807 808 if (on) { 809 e82545_tx_update_tdba(sc); 810 e82545_tx_enable(sc); 811 } else { 812 e82545_tx_disable(sc); 813 sc->esc_tdba = 0; 814 sc->esc_txdesc = NULL; 815 } 816 817 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 818 sc->esc_TCTL = val & ~0xFE800005; 819 } 820 821 int 822 e82545_bufsz(uint32_t rctl) 823 { 824 825 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 826 case (E1000_RCTL_SZ_2048): return (2048); 827 case (E1000_RCTL_SZ_1024): return (1024); 828 case (E1000_RCTL_SZ_512): return (512); 829 case (E1000_RCTL_SZ_256): return (256); 830 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 831 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 832 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 833 } 834 return (256); /* Forbidden value. */ 835 } 836 837 #ifdef __FreeBSD__ 838 static uint8_t dummybuf[2048]; 839 840 /* XXX one packet at a time until this is debugged */ 841 static void 842 e82545_tap_callback(int fd, enum ev_type type, void *param) 843 { 844 struct e82545_softc *sc = param; 845 struct e1000_rx_desc *rxd; 846 struct iovec vec[64]; 847 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 848 uint32_t cause = 0; 849 uint16_t *tp, tag, head; 850 851 pthread_mutex_lock(&sc->esc_mtx); 852 DPRINTF("rx_run: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 853 854 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 855 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped\r\n", 856 sc->esc_rx_enabled, sc->esc_rx_loopback); 857 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 858 } 859 goto done1; 860 } 861 bufsz = e82545_bufsz(sc->esc_RCTL); 862 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 863 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 864 size = sc->esc_RDLEN / 16; 865 head = sc->esc_RDH; 866 left = (size + sc->esc_RDT - head) % size; 867 if (left < maxpktdesc) { 868 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped\r\n", 869 left, maxpktdesc); 870 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 871 } 872 goto done1; 873 } 874 875 sc->esc_rx_active = 1; 876 pthread_mutex_unlock(&sc->esc_mtx); 877 878 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 879 880 /* Grab rx descriptor pointed to by the head pointer */ 881 for (i = 0; i < maxpktdesc; i++) { 882 rxd = &sc->esc_rxdesc[(head + i) % size]; 883 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 884 rxd->buffer_addr, bufsz); 885 vec[i].iov_len = bufsz; 886 } 887 len = readv(sc->esc_tapfd, vec, maxpktdesc); 888 if (len <= 0) { 889 DPRINTF("tap: readv() returned %d\n", len); 890 goto done; 891 } 892 893 /* 894 * Adjust the packet length based on whether the CRC needs 895 * to be stripped or if the packet is less than the minimum 896 * eth packet size. 897 */ 898 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 899 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 900 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 901 len += ETHER_CRC_LEN; 902 n = (len + bufsz - 1) / bufsz; 903 904 DPRINTF("packet read %d bytes, %d segs, head %d\r\n", 905 len, n, head); 906 907 /* Apply VLAN filter. */ 908 tp = (uint16_t *)vec[0].iov_base + 6; 909 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 910 (ntohs(tp[0]) == sc->esc_VET)) { 911 tag = ntohs(tp[1]) & 0x0fff; 912 if ((sc->esc_fvlan[tag >> 5] & 913 (1 << (tag & 0x1f))) != 0) { 914 DPRINTF("known VLAN %d\r\n", tag); 915 } else { 916 DPRINTF("unknown VLAN %d\r\n", tag); 917 n = 0; 918 continue; 919 } 920 } 921 922 /* Update all consumed descriptors. */ 923 for (i = 0; i < n - 1; i++) { 924 rxd = &sc->esc_rxdesc[(head + i) % size]; 925 rxd->length = bufsz; 926 rxd->csum = 0; 927 rxd->errors = 0; 928 rxd->special = 0; 929 rxd->status = E1000_RXD_STAT_DD; 930 } 931 rxd = &sc->esc_rxdesc[(head + i) % size]; 932 rxd->length = len % bufsz; 933 rxd->csum = 0; 934 rxd->errors = 0; 935 rxd->special = 0; 936 /* XXX signal no checksum for now */ 937 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 938 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 939 940 /* Schedule receive interrupts. */ 941 if (len <= sc->esc_RSRPD) { 942 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 943 } else { 944 /* XXX: RDRT and RADV timers should be here. */ 945 cause |= E1000_ICR_RXT0; 946 } 947 948 head = (head + n) % size; 949 left -= n; 950 } 951 952 done: 953 pthread_mutex_lock(&sc->esc_mtx); 954 sc->esc_rx_active = 0; 955 if (sc->esc_rx_enabled == 0) 956 pthread_cond_signal(&sc->esc_rx_cond); 957 958 sc->esc_RDH = head; 959 /* Respect E1000_RCTL_RDMTS */ 960 left = (size + sc->esc_RDT - head) % size; 961 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 962 cause |= E1000_ICR_RXDMT0; 963 /* Assert all accumulated interrupts. */ 964 if (cause != 0) 965 e82545_icr_assert(sc, cause); 966 done1: 967 DPRINTF("rx_run done: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 968 pthread_mutex_unlock(&sc->esc_mtx); 969 } 970 #endif 971 972 static uint16_t 973 e82545_carry(uint32_t sum) 974 { 975 976 sum = (sum & 0xFFFF) + (sum >> 16); 977 if (sum > 0xFFFF) 978 sum -= 0xFFFF; 979 return (sum); 980 } 981 982 static uint16_t 983 #ifdef __FreeBSD__ 984 e82545_buf_checksum(uint8_t *buf, int len) 985 #else 986 e82545_buf_checksum(caddr_t buf, int len) 987 #endif 988 { 989 int i; 990 uint32_t sum = 0; 991 992 /* Checksum all the pairs of bytes first... */ 993 for (i = 0; i < (len & ~1U); i += 2) 994 sum += *((u_int16_t *)(buf + i)); 995 996 /* 997 * If there's a single byte left over, checksum it, too. 998 * Network byte order is big-endian, so the remaining byte is 999 * the high byte. 1000 */ 1001 if (i < len) 1002 sum += htons(buf[i] << 8); 1003 1004 return (e82545_carry(sum)); 1005 } 1006 1007 static uint16_t 1008 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 1009 { 1010 int now, odd; 1011 uint32_t sum = 0, s; 1012 1013 /* Skip completely unneeded vectors. */ 1014 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1015 off -= iov->iov_len; 1016 iov++; 1017 iovcnt--; 1018 } 1019 1020 /* Calculate checksum of requested range. */ 1021 odd = 0; 1022 while (len > 0 && iovcnt > 0) { 1023 now = MIN(len, iov->iov_len - off); 1024 s = e82545_buf_checksum(iov->iov_base + off, now); 1025 sum += odd ? (s << 8) : s; 1026 odd ^= (now & 1); 1027 len -= now; 1028 off = 0; 1029 iov++; 1030 iovcnt--; 1031 } 1032 1033 return (e82545_carry(sum)); 1034 } 1035 1036 /* 1037 * Return the transmit descriptor type. 1038 */ 1039 int 1040 e82545_txdesc_type(uint32_t lower) 1041 { 1042 int type; 1043 1044 type = 0; 1045 1046 if (lower & E1000_TXD_CMD_DEXT) 1047 type = lower & E1000_TXD_MASK; 1048 1049 return (type); 1050 } 1051 1052 static void 1053 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1054 { 1055 uint16_t cksum; 1056 int cklen; 1057 1058 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d\r\n", 1059 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1060 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1061 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1062 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1063 } 1064 1065 static void 1066 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1067 { 1068 1069 if (sc->esc_tapfd == -1) 1070 return; 1071 1072 (void) writev(sc->esc_tapfd, iov, iovcnt); 1073 } 1074 1075 static void 1076 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1077 uint16_t dsize, int *tdwb) 1078 { 1079 union e1000_tx_udesc *dsc; 1080 1081 for ( ; head != tail; head = (head + 1) % dsize) { 1082 dsc = &sc->esc_txdesc[head]; 1083 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1084 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1085 *tdwb = 1; 1086 } 1087 } 1088 } 1089 1090 static int 1091 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1092 uint16_t dsize, uint16_t *rhead, int *tdwb) 1093 { 1094 #ifdef __FreeBSD__ 1095 uint8_t *hdr, *hdrp; 1096 #else 1097 caddr_t hdr, hdrp; 1098 #endif 1099 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1100 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1101 struct e1000_context_desc *cd; 1102 struct ck_info ckinfo[2]; 1103 struct iovec *iov; 1104 union e1000_tx_udesc *dsc; 1105 int desc, dtype, len, ntype, iovcnt, tlen, hdrlen, vlen, tcp, tso; 1106 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1107 uint32_t tcpsum, tcpseq; 1108 uint16_t ipcs, tcpcs, ipid, ohead; 1109 1110 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1111 iovcnt = 0; 1112 tlen = 0; 1113 ntype = 0; 1114 tso = 0; 1115 ohead = head; 1116 hdr = NULL; 1117 1118 /* iovb[0/1] may be used for writable copy of headers. */ 1119 iov = &iovb[2]; 1120 1121 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1122 if (head == tail) { 1123 *rhead = head; 1124 return (0); 1125 } 1126 dsc = &sc->esc_txdesc[head]; 1127 dtype = e82545_txdesc_type(dsc->td.lower.data); 1128 1129 if (desc == 0) { 1130 switch (dtype) { 1131 case E1000_TXD_TYP_C: 1132 DPRINTF("tx ctxt desc idx %d: %016jx " 1133 "%08x%08x\r\n", 1134 head, dsc->td.buffer_addr, 1135 dsc->td.upper.data, dsc->td.lower.data); 1136 /* Save context and return */ 1137 sc->esc_txctx = dsc->cd; 1138 goto done; 1139 case E1000_TXD_TYP_L: 1140 DPRINTF("tx legacy desc idx %d: %08x%08x\r\n", 1141 head, dsc->td.upper.data, dsc->td.lower.data); 1142 /* 1143 * legacy cksum start valid in first descriptor 1144 */ 1145 ntype = dtype; 1146 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1147 break; 1148 case E1000_TXD_TYP_D: 1149 DPRINTF("tx data desc idx %d: %08x%08x\r\n", 1150 head, dsc->td.upper.data, dsc->td.lower.data); 1151 ntype = dtype; 1152 break; 1153 default: 1154 break; 1155 } 1156 } else { 1157 /* Descriptor type must be consistent */ 1158 assert(dtype == ntype); 1159 DPRINTF("tx next desc idx %d: %08x%08x\r\n", 1160 head, dsc->td.upper.data, dsc->td.lower.data); 1161 } 1162 1163 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1164 dsc->dd.lower.data & 0xFFFFF; 1165 1166 if (len > 0) { 1167 /* Strip checksum supplied by guest. */ 1168 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1169 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1170 len -= 2; 1171 tlen += len; 1172 if (iovcnt < I82545_MAX_TXSEGS) { 1173 iov[iovcnt].iov_base = paddr_guest2host( 1174 sc->esc_ctx, dsc->td.buffer_addr, len); 1175 iov[iovcnt].iov_len = len; 1176 } 1177 iovcnt++; 1178 } 1179 1180 /* 1181 * Pull out info that is valid in the final descriptor 1182 * and exit descriptor loop. 1183 */ 1184 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1185 if (dtype == E1000_TXD_TYP_L) { 1186 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1187 ckinfo[0].ck_valid = 1; 1188 ckinfo[0].ck_off = 1189 dsc->td.lower.flags.cso; 1190 ckinfo[0].ck_len = 0; 1191 } 1192 } else { 1193 cd = &sc->esc_txctx; 1194 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1195 tso = 1; 1196 if (dsc->dd.upper.fields.popts & 1197 E1000_TXD_POPTS_IXSM) 1198 ckinfo[0].ck_valid = 1; 1199 if (dsc->dd.upper.fields.popts & 1200 E1000_TXD_POPTS_IXSM || tso) { 1201 ckinfo[0].ck_start = 1202 cd->lower_setup.ip_fields.ipcss; 1203 ckinfo[0].ck_off = 1204 cd->lower_setup.ip_fields.ipcso; 1205 ckinfo[0].ck_len = 1206 cd->lower_setup.ip_fields.ipcse; 1207 } 1208 if (dsc->dd.upper.fields.popts & 1209 E1000_TXD_POPTS_TXSM) 1210 ckinfo[1].ck_valid = 1; 1211 if (dsc->dd.upper.fields.popts & 1212 E1000_TXD_POPTS_TXSM || tso) { 1213 ckinfo[1].ck_start = 1214 cd->upper_setup.tcp_fields.tucss; 1215 ckinfo[1].ck_off = 1216 cd->upper_setup.tcp_fields.tucso; 1217 ckinfo[1].ck_len = 1218 cd->upper_setup.tcp_fields.tucse; 1219 } 1220 } 1221 break; 1222 } 1223 } 1224 1225 if (iovcnt > I82545_MAX_TXSEGS) { 1226 WPRINTF("tx too many descriptors (%d > %d) -- dropped\r\n", 1227 iovcnt, I82545_MAX_TXSEGS); 1228 goto done; 1229 } 1230 1231 hdrlen = vlen = 0; 1232 /* Estimate writable space for VLAN header insertion. */ 1233 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1234 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1235 hdrlen = ETHER_ADDR_LEN*2; 1236 vlen = ETHER_VLAN_ENCAP_LEN; 1237 } 1238 if (!tso) { 1239 /* Estimate required writable space for checksums. */ 1240 if (ckinfo[0].ck_valid) 1241 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1242 if (ckinfo[1].ck_valid) 1243 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1244 /* Round up writable space to the first vector. */ 1245 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1246 iov[0].iov_len < hdrlen + 100) 1247 hdrlen = iov[0].iov_len; 1248 } else { 1249 /* In case of TSO header length provided by software. */ 1250 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1251 } 1252 1253 /* Allocate, fill and prepend writable header vector. */ 1254 if (hdrlen != 0) { 1255 hdr = __builtin_alloca(hdrlen + vlen); 1256 hdr += vlen; 1257 for (left = hdrlen, hdrp = hdr; left > 0; 1258 left -= now, hdrp += now) { 1259 now = MIN(left, iov->iov_len); 1260 memcpy(hdrp, iov->iov_base, now); 1261 iov->iov_base += now; 1262 iov->iov_len -= now; 1263 if (iov->iov_len == 0) { 1264 iov++; 1265 iovcnt--; 1266 } 1267 } 1268 iov--; 1269 iovcnt++; 1270 iov->iov_base = hdr; 1271 iov->iov_len = hdrlen; 1272 } 1273 1274 /* Insert VLAN tag. */ 1275 if (vlen != 0) { 1276 hdr -= ETHER_VLAN_ENCAP_LEN; 1277 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1278 hdrlen += ETHER_VLAN_ENCAP_LEN; 1279 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1280 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1281 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1282 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1283 iov->iov_base = hdr; 1284 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1285 /* Correct checksum offsets after VLAN tag insertion. */ 1286 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1287 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1288 if (ckinfo[0].ck_len != 0) 1289 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1290 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1291 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1292 if (ckinfo[1].ck_len != 0) 1293 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1294 } 1295 1296 /* Simple non-TSO case. */ 1297 if (!tso) { 1298 /* Calculate checksums and transmit. */ 1299 if (ckinfo[0].ck_valid) 1300 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1301 if (ckinfo[1].ck_valid) 1302 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1303 e82545_transmit_backend(sc, iov, iovcnt); 1304 goto done; 1305 } 1306 1307 /* Doing TSO. */ 1308 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1309 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1310 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1311 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n", 1312 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1313 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1314 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1315 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1316 tcpcs = 0; 1317 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1318 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1319 pv = 1; 1320 pvoff = 0; 1321 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1322 now = MIN(left, mss); 1323 1324 /* Construct IOVs for the segment. */ 1325 /* Include whole original header. */ 1326 tiov[0].iov_base = hdr; 1327 tiov[0].iov_len = hdrlen; 1328 tiovcnt = 1; 1329 /* Include respective part of payload IOV. */ 1330 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1331 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1332 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1333 tiov[tiovcnt++].iov_len = nnow; 1334 if (pvoff + nnow == iov[pv].iov_len) { 1335 pv++; 1336 pvoff = 0; 1337 } else 1338 pvoff += nnow; 1339 } 1340 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n", 1341 seg, hdrlen, now, tiovcnt); 1342 1343 /* Update IP header. */ 1344 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1345 /* IPv4 -- set length and ID */ 1346 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1347 htons(hdrlen - ckinfo[0].ck_start + now); 1348 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1349 htons(ipid + seg); 1350 } else { 1351 /* IPv6 -- set length */ 1352 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1353 htons(hdrlen - ckinfo[0].ck_start - 40 + 1354 now); 1355 } 1356 1357 /* Update pseudo-header checksum. */ 1358 tcpsum = tcpcs; 1359 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1360 1361 /* Update TCP/UDP headers. */ 1362 if (tcp) { 1363 /* Update sequence number and FIN/PUSH flags. */ 1364 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1365 htonl(tcpseq + paylen - left); 1366 if (now < left) { 1367 hdr[ckinfo[1].ck_start + 13] &= 1368 ~(TH_FIN | TH_PUSH); 1369 } 1370 } else { 1371 /* Update payload length. */ 1372 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1373 hdrlen - ckinfo[1].ck_start + now; 1374 } 1375 1376 /* Calculate checksums and transmit. */ 1377 if (ckinfo[0].ck_valid) { 1378 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1379 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1380 } 1381 if (ckinfo[1].ck_valid) { 1382 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1383 e82545_carry(tcpsum); 1384 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1385 } 1386 e82545_transmit_backend(sc, tiov, tiovcnt); 1387 } 1388 1389 done: 1390 head = (head + 1) % dsize; 1391 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1392 1393 *rhead = head; 1394 return (desc + 1); 1395 } 1396 1397 static void 1398 e82545_tx_run(struct e82545_softc *sc) 1399 { 1400 uint32_t cause; 1401 uint16_t head, rhead, tail, size; 1402 int lim, tdwb, sent; 1403 1404 head = sc->esc_TDH; 1405 tail = sc->esc_TDT; 1406 size = sc->esc_TDLEN / 16; 1407 DPRINTF("tx_run: head %x, rhead %x, tail %x\r\n", 1408 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1409 1410 pthread_mutex_unlock(&sc->esc_mtx); 1411 rhead = head; 1412 tdwb = 0; 1413 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1414 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1415 if (sent == 0) 1416 break; 1417 head = rhead; 1418 } 1419 pthread_mutex_lock(&sc->esc_mtx); 1420 1421 sc->esc_TDH = head; 1422 sc->esc_TDHr = rhead; 1423 cause = 0; 1424 if (tdwb) 1425 cause |= E1000_ICR_TXDW; 1426 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1427 cause |= E1000_ICR_TXQE; 1428 if (cause) 1429 e82545_icr_assert(sc, cause); 1430 1431 DPRINTF("tx_run done: head %x, rhead %x, tail %x\r\n", 1432 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1433 } 1434 1435 static void * 1436 e82545_tx_thread(void *param) 1437 { 1438 struct e82545_softc *sc = param; 1439 1440 pthread_mutex_lock(&sc->esc_mtx); 1441 for (;;) { 1442 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1443 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1444 break; 1445 sc->esc_tx_active = 0; 1446 if (sc->esc_tx_enabled == 0) 1447 pthread_cond_signal(&sc->esc_tx_cond); 1448 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1449 } 1450 sc->esc_tx_active = 1; 1451 1452 /* Process some tx descriptors. Lock dropped inside. */ 1453 e82545_tx_run(sc); 1454 } 1455 #ifndef __FreeBSD__ 1456 return (NULL); 1457 #endif 1458 } 1459 1460 static void 1461 e82545_tx_start(struct e82545_softc *sc) 1462 { 1463 1464 if (sc->esc_tx_active == 0) 1465 pthread_cond_signal(&sc->esc_tx_cond); 1466 } 1467 1468 static void 1469 e82545_tx_enable(struct e82545_softc *sc) 1470 { 1471 1472 sc->esc_tx_enabled = 1; 1473 } 1474 1475 static void 1476 e82545_tx_disable(struct e82545_softc *sc) 1477 { 1478 1479 sc->esc_tx_enabled = 0; 1480 while (sc->esc_tx_active) 1481 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1482 } 1483 1484 static void 1485 e82545_rx_enable(struct e82545_softc *sc) 1486 { 1487 1488 sc->esc_rx_enabled = 1; 1489 } 1490 1491 static void 1492 e82545_rx_disable(struct e82545_softc *sc) 1493 { 1494 1495 sc->esc_rx_enabled = 0; 1496 while (sc->esc_rx_active) 1497 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1498 } 1499 1500 static void 1501 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1502 { 1503 struct eth_uni *eu; 1504 int idx; 1505 1506 idx = reg >> 1; 1507 assert(idx < 15); 1508 1509 eu = &sc->esc_uni[idx]; 1510 1511 if (reg & 0x1) { 1512 /* RAH */ 1513 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1514 eu->eu_addrsel = (wval >> 16) & 0x3; 1515 eu->eu_eth.octet[5] = wval >> 8; 1516 eu->eu_eth.octet[4] = wval; 1517 } else { 1518 /* RAL */ 1519 eu->eu_eth.octet[3] = wval >> 24; 1520 eu->eu_eth.octet[2] = wval >> 16; 1521 eu->eu_eth.octet[1] = wval >> 8; 1522 eu->eu_eth.octet[0] = wval; 1523 } 1524 } 1525 1526 static uint32_t 1527 e82545_read_ra(struct e82545_softc *sc, int reg) 1528 { 1529 struct eth_uni *eu; 1530 uint32_t retval; 1531 int idx; 1532 1533 idx = reg >> 1; 1534 assert(idx < 15); 1535 1536 eu = &sc->esc_uni[idx]; 1537 1538 if (reg & 0x1) { 1539 /* RAH */ 1540 retval = (eu->eu_valid << 31) | 1541 (eu->eu_addrsel << 16) | 1542 (eu->eu_eth.octet[5] << 8) | 1543 eu->eu_eth.octet[4]; 1544 } else { 1545 /* RAL */ 1546 retval = (eu->eu_eth.octet[3] << 24) | 1547 (eu->eu_eth.octet[2] << 16) | 1548 (eu->eu_eth.octet[1] << 8) | 1549 eu->eu_eth.octet[0]; 1550 } 1551 1552 return (retval); 1553 } 1554 1555 static void 1556 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1557 { 1558 int ridx; 1559 1560 if (offset & 0x3) { 1561 DPRINTF("Unaligned register write offset:0x%x value:0x%x\r\n", offset, value); 1562 return; 1563 } 1564 DPRINTF("Register write: 0x%x value: 0x%x\r\n", offset, value); 1565 1566 switch (offset) { 1567 case E1000_CTRL: 1568 case E1000_CTRL_DUP: 1569 e82545_devctl(sc, value); 1570 break; 1571 case E1000_FCAL: 1572 sc->esc_FCAL = value; 1573 break; 1574 case E1000_FCAH: 1575 sc->esc_FCAH = value & ~0xFFFF0000; 1576 break; 1577 case E1000_FCT: 1578 sc->esc_FCT = value & ~0xFFFF0000; 1579 break; 1580 case E1000_VET: 1581 sc->esc_VET = value & ~0xFFFF0000; 1582 break; 1583 case E1000_FCTTV: 1584 sc->esc_FCTTV = value & ~0xFFFF0000; 1585 break; 1586 case E1000_LEDCTL: 1587 sc->esc_LEDCTL = value & ~0x30303000; 1588 break; 1589 case E1000_PBA: 1590 sc->esc_PBA = value & 0x0000FF80; 1591 break; 1592 case E1000_ICR: 1593 case E1000_ITR: 1594 case E1000_ICS: 1595 case E1000_IMS: 1596 case E1000_IMC: 1597 e82545_intr_write(sc, offset, value); 1598 break; 1599 case E1000_RCTL: 1600 e82545_rx_ctl(sc, value); 1601 break; 1602 case E1000_FCRTL: 1603 sc->esc_FCRTL = value & ~0xFFFF0007; 1604 break; 1605 case E1000_FCRTH: 1606 sc->esc_FCRTH = value & ~0xFFFF0007; 1607 break; 1608 case E1000_RDBAL(0): 1609 sc->esc_RDBAL = value & ~0xF; 1610 if (sc->esc_rx_enabled) { 1611 /* Apparently legal: update cached address */ 1612 e82545_rx_update_rdba(sc); 1613 } 1614 break; 1615 case E1000_RDBAH(0): 1616 assert(!sc->esc_rx_enabled); 1617 sc->esc_RDBAH = value; 1618 break; 1619 case E1000_RDLEN(0): 1620 assert(!sc->esc_rx_enabled); 1621 sc->esc_RDLEN = value & ~0xFFF0007F; 1622 break; 1623 case E1000_RDH(0): 1624 /* XXX should only ever be zero ? Range check ? */ 1625 sc->esc_RDH = value; 1626 break; 1627 case E1000_RDT(0): 1628 /* XXX if this opens up the rx ring, do something ? */ 1629 sc->esc_RDT = value; 1630 break; 1631 case E1000_RDTR: 1632 /* ignore FPD bit 31 */ 1633 sc->esc_RDTR = value & ~0xFFFF0000; 1634 break; 1635 case E1000_RXDCTL(0): 1636 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1637 break; 1638 case E1000_RADV: 1639 sc->esc_RADV = value & ~0xFFFF0000; 1640 break; 1641 case E1000_RSRPD: 1642 sc->esc_RSRPD = value & ~0xFFFFF000; 1643 break; 1644 case E1000_RXCSUM: 1645 sc->esc_RXCSUM = value & ~0xFFFFF800; 1646 break; 1647 case E1000_TXCW: 1648 sc->esc_TXCW = value & ~0x3FFF0000; 1649 break; 1650 case E1000_TCTL: 1651 e82545_tx_ctl(sc, value); 1652 break; 1653 case E1000_TIPG: 1654 sc->esc_TIPG = value; 1655 break; 1656 case E1000_AIT: 1657 sc->esc_AIT = value; 1658 break; 1659 case E1000_TDBAL(0): 1660 sc->esc_TDBAL = value & ~0xF; 1661 if (sc->esc_tx_enabled) { 1662 /* Apparently legal */ 1663 e82545_tx_update_tdba(sc); 1664 } 1665 break; 1666 case E1000_TDBAH(0): 1667 //assert(!sc->esc_tx_enabled); 1668 sc->esc_TDBAH = value; 1669 break; 1670 case E1000_TDLEN(0): 1671 //assert(!sc->esc_tx_enabled); 1672 sc->esc_TDLEN = value & ~0xFFF0007F; 1673 break; 1674 case E1000_TDH(0): 1675 //assert(!sc->esc_tx_enabled); 1676 /* XXX should only ever be zero ? Range check ? */ 1677 sc->esc_TDHr = sc->esc_TDH = value; 1678 break; 1679 case E1000_TDT(0): 1680 /* XXX range check ? */ 1681 sc->esc_TDT = value; 1682 if (sc->esc_tx_enabled) 1683 e82545_tx_start(sc); 1684 break; 1685 case E1000_TIDV: 1686 sc->esc_TIDV = value & ~0xFFFF0000; 1687 break; 1688 case E1000_TXDCTL(0): 1689 //assert(!sc->esc_tx_enabled); 1690 sc->esc_TXDCTL = value & ~0xC0C0C0; 1691 break; 1692 case E1000_TADV: 1693 sc->esc_TADV = value & ~0xFFFF0000; 1694 break; 1695 case E1000_RAL(0) ... E1000_RAH(15): 1696 /* convert to u32 offset */ 1697 ridx = (offset - E1000_RAL(0)) >> 2; 1698 e82545_write_ra(sc, ridx, value); 1699 break; 1700 case E1000_MTA ... (E1000_MTA + (127*4)): 1701 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1702 break; 1703 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1704 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1705 break; 1706 case E1000_EECD: 1707 { 1708 //DPRINTF("EECD write 0x%x -> 0x%x\r\n", sc->eeprom_control, value); 1709 /* edge triggered low->high */ 1710 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1711 0 : (value & E1000_EECD_SK)); 1712 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1713 E1000_EECD_DI|E1000_EECD_REQ); 1714 sc->eeprom_control &= ~eecd_mask; 1715 sc->eeprom_control |= (value & eecd_mask); 1716 /* grant/revoke immediately */ 1717 if (value & E1000_EECD_REQ) { 1718 sc->eeprom_control |= E1000_EECD_GNT; 1719 } else { 1720 sc->eeprom_control &= ~E1000_EECD_GNT; 1721 } 1722 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1723 e82545_eecd_strobe(sc); 1724 } 1725 return; 1726 } 1727 case E1000_MDIC: 1728 { 1729 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1730 E1000_MDIC_REG_SHIFT); 1731 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1732 E1000_MDIC_PHY_SHIFT); 1733 sc->mdi_control = 1734 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1735 if ((value & E1000_MDIC_READY) != 0) { 1736 DPRINTF("Incorrect MDIC ready bit: 0x%x\r\n", value); 1737 return; 1738 } 1739 switch (value & E82545_MDIC_OP_MASK) { 1740 case E1000_MDIC_OP_READ: 1741 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1742 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1743 break; 1744 case E1000_MDIC_OP_WRITE: 1745 e82545_write_mdi(sc, reg_addr, phy_addr, 1746 value & E82545_MDIC_DATA_MASK); 1747 break; 1748 default: 1749 DPRINTF("Unknown MDIC op: 0x%x\r\n", value); 1750 return; 1751 } 1752 /* TODO: barrier? */ 1753 sc->mdi_control |= E1000_MDIC_READY; 1754 if (value & E82545_MDIC_IE) { 1755 // TODO: generate interrupt 1756 } 1757 return; 1758 } 1759 case E1000_MANC: 1760 case E1000_STATUS: 1761 return; 1762 default: 1763 DPRINTF("Unknown write register: 0x%x value:%x\r\n", offset, value); 1764 return; 1765 } 1766 } 1767 1768 static uint32_t 1769 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1770 { 1771 uint32_t retval; 1772 int ridx; 1773 1774 if (offset & 0x3) { 1775 DPRINTF("Unaligned register read offset:0x%x\r\n", offset); 1776 return 0; 1777 } 1778 1779 DPRINTF("Register read: 0x%x\r\n", offset); 1780 1781 switch (offset) { 1782 case E1000_CTRL: 1783 retval = sc->esc_CTRL; 1784 break; 1785 case E1000_STATUS: 1786 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1787 E1000_STATUS_SPEED_1000; 1788 break; 1789 case E1000_FCAL: 1790 retval = sc->esc_FCAL; 1791 break; 1792 case E1000_FCAH: 1793 retval = sc->esc_FCAH; 1794 break; 1795 case E1000_FCT: 1796 retval = sc->esc_FCT; 1797 break; 1798 case E1000_VET: 1799 retval = sc->esc_VET; 1800 break; 1801 case E1000_FCTTV: 1802 retval = sc->esc_FCTTV; 1803 break; 1804 case E1000_LEDCTL: 1805 retval = sc->esc_LEDCTL; 1806 break; 1807 case E1000_PBA: 1808 retval = sc->esc_PBA; 1809 break; 1810 case E1000_ICR: 1811 case E1000_ITR: 1812 case E1000_ICS: 1813 case E1000_IMS: 1814 case E1000_IMC: 1815 retval = e82545_intr_read(sc, offset); 1816 break; 1817 case E1000_RCTL: 1818 retval = sc->esc_RCTL; 1819 break; 1820 case E1000_FCRTL: 1821 retval = sc->esc_FCRTL; 1822 break; 1823 case E1000_FCRTH: 1824 retval = sc->esc_FCRTH; 1825 break; 1826 case E1000_RDBAL(0): 1827 retval = sc->esc_RDBAL; 1828 break; 1829 case E1000_RDBAH(0): 1830 retval = sc->esc_RDBAH; 1831 break; 1832 case E1000_RDLEN(0): 1833 retval = sc->esc_RDLEN; 1834 break; 1835 case E1000_RDH(0): 1836 retval = sc->esc_RDH; 1837 break; 1838 case E1000_RDT(0): 1839 retval = sc->esc_RDT; 1840 break; 1841 case E1000_RDTR: 1842 retval = sc->esc_RDTR; 1843 break; 1844 case E1000_RXDCTL(0): 1845 retval = sc->esc_RXDCTL; 1846 break; 1847 case E1000_RADV: 1848 retval = sc->esc_RADV; 1849 break; 1850 case E1000_RSRPD: 1851 retval = sc->esc_RSRPD; 1852 break; 1853 case E1000_RXCSUM: 1854 retval = sc->esc_RXCSUM; 1855 break; 1856 case E1000_TXCW: 1857 retval = sc->esc_TXCW; 1858 break; 1859 case E1000_TCTL: 1860 retval = sc->esc_TCTL; 1861 break; 1862 case E1000_TIPG: 1863 retval = sc->esc_TIPG; 1864 break; 1865 case E1000_AIT: 1866 retval = sc->esc_AIT; 1867 break; 1868 case E1000_TDBAL(0): 1869 retval = sc->esc_TDBAL; 1870 break; 1871 case E1000_TDBAH(0): 1872 retval = sc->esc_TDBAH; 1873 break; 1874 case E1000_TDLEN(0): 1875 retval = sc->esc_TDLEN; 1876 break; 1877 case E1000_TDH(0): 1878 retval = sc->esc_TDH; 1879 break; 1880 case E1000_TDT(0): 1881 retval = sc->esc_TDT; 1882 break; 1883 case E1000_TIDV: 1884 retval = sc->esc_TIDV; 1885 break; 1886 case E1000_TXDCTL(0): 1887 retval = sc->esc_TXDCTL; 1888 break; 1889 case E1000_TADV: 1890 retval = sc->esc_TADV; 1891 break; 1892 case E1000_RAL(0) ... E1000_RAH(15): 1893 /* convert to u32 offset */ 1894 ridx = (offset - E1000_RAL(0)) >> 2; 1895 retval = e82545_read_ra(sc, ridx); 1896 break; 1897 case E1000_MTA ... (E1000_MTA + (127*4)): 1898 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1899 break; 1900 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1901 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1902 break; 1903 case E1000_EECD: 1904 //DPRINTF("EECD read %x\r\n", sc->eeprom_control); 1905 retval = sc->eeprom_control; 1906 break; 1907 case E1000_MDIC: 1908 retval = sc->mdi_control; 1909 break; 1910 case E1000_MANC: 1911 retval = 0; 1912 break; 1913 /* stats that we emulate. */ 1914 case E1000_MPC: 1915 retval = sc->missed_pkt_count; 1916 break; 1917 case E1000_PRC64: 1918 retval = sc->pkt_rx_by_size[0]; 1919 break; 1920 case E1000_PRC127: 1921 retval = sc->pkt_rx_by_size[1]; 1922 break; 1923 case E1000_PRC255: 1924 retval = sc->pkt_rx_by_size[2]; 1925 break; 1926 case E1000_PRC511: 1927 retval = sc->pkt_rx_by_size[3]; 1928 break; 1929 case E1000_PRC1023: 1930 retval = sc->pkt_rx_by_size[4]; 1931 break; 1932 case E1000_PRC1522: 1933 retval = sc->pkt_rx_by_size[5]; 1934 break; 1935 case E1000_GPRC: 1936 retval = sc->good_pkt_rx_count; 1937 break; 1938 case E1000_BPRC: 1939 retval = sc->bcast_pkt_rx_count; 1940 break; 1941 case E1000_MPRC: 1942 retval = sc->mcast_pkt_rx_count; 1943 break; 1944 case E1000_GPTC: 1945 case E1000_TPT: 1946 retval = sc->good_pkt_tx_count; 1947 break; 1948 case E1000_GORCL: 1949 retval = (uint32_t)sc->good_octets_rx; 1950 break; 1951 case E1000_GORCH: 1952 retval = (uint32_t)(sc->good_octets_rx >> 32); 1953 break; 1954 case E1000_TOTL: 1955 case E1000_GOTCL: 1956 retval = (uint32_t)sc->good_octets_tx; 1957 break; 1958 case E1000_TOTH: 1959 case E1000_GOTCH: 1960 retval = (uint32_t)(sc->good_octets_tx >> 32); 1961 break; 1962 case E1000_ROC: 1963 retval = sc->oversize_rx_count; 1964 break; 1965 case E1000_TORL: 1966 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 1967 break; 1968 case E1000_TORH: 1969 retval = (uint32_t)((sc->good_octets_rx + 1970 sc->missed_octets) >> 32); 1971 break; 1972 case E1000_TPR: 1973 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 1974 sc->oversize_rx_count; 1975 break; 1976 case E1000_PTC64: 1977 retval = sc->pkt_tx_by_size[0]; 1978 break; 1979 case E1000_PTC127: 1980 retval = sc->pkt_tx_by_size[1]; 1981 break; 1982 case E1000_PTC255: 1983 retval = sc->pkt_tx_by_size[2]; 1984 break; 1985 case E1000_PTC511: 1986 retval = sc->pkt_tx_by_size[3]; 1987 break; 1988 case E1000_PTC1023: 1989 retval = sc->pkt_tx_by_size[4]; 1990 break; 1991 case E1000_PTC1522: 1992 retval = sc->pkt_tx_by_size[5]; 1993 break; 1994 case E1000_MPTC: 1995 retval = sc->mcast_pkt_tx_count; 1996 break; 1997 case E1000_BPTC: 1998 retval = sc->bcast_pkt_tx_count; 1999 break; 2000 case E1000_TSCTC: 2001 retval = sc->tso_tx_count; 2002 break; 2003 /* stats that are always 0. */ 2004 case E1000_CRCERRS: 2005 case E1000_ALGNERRC: 2006 case E1000_SYMERRS: 2007 case E1000_RXERRC: 2008 case E1000_SCC: 2009 case E1000_ECOL: 2010 case E1000_MCC: 2011 case E1000_LATECOL: 2012 case E1000_COLC: 2013 case E1000_DC: 2014 case E1000_TNCRS: 2015 case E1000_SEC: 2016 case E1000_CEXTERR: 2017 case E1000_RLEC: 2018 case E1000_XONRXC: 2019 case E1000_XONTXC: 2020 case E1000_XOFFRXC: 2021 case E1000_XOFFTXC: 2022 case E1000_FCRUC: 2023 case E1000_RNBC: 2024 case E1000_RUC: 2025 case E1000_RFC: 2026 case E1000_RJC: 2027 case E1000_MGTPRC: 2028 case E1000_MGTPDC: 2029 case E1000_MGTPTC: 2030 case E1000_TSCTFC: 2031 retval = 0; 2032 break; 2033 default: 2034 DPRINTF("Unknown read register: 0x%x\r\n", offset); 2035 retval = 0; 2036 break; 2037 } 2038 2039 return (retval); 2040 } 2041 2042 static void 2043 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2044 uint64_t offset, int size, uint64_t value) 2045 { 2046 struct e82545_softc *sc; 2047 2048 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d\r\n", baridx, offset, value, size); 2049 2050 sc = pi->pi_arg; 2051 2052 pthread_mutex_lock(&sc->esc_mtx); 2053 2054 switch (baridx) { 2055 case E82545_BAR_IO: 2056 switch (offset) { 2057 case E82545_IOADDR: 2058 if (size != 4) { 2059 DPRINTF("Wrong io addr write sz:%d value:0x%lx\r\n", size, value); 2060 } else 2061 sc->io_addr = (uint32_t)value; 2062 break; 2063 case E82545_IODATA: 2064 if (size != 4) { 2065 DPRINTF("Wrong io data write size:%d value:0x%lx\r\n", size, value); 2066 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2067 DPRINTF("Non-register io write addr:0x%x value:0x%lx\r\n", sc->io_addr, value); 2068 } else 2069 e82545_write_register(sc, sc->io_addr, 2070 (uint32_t)value); 2071 break; 2072 default: 2073 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d\r\n", offset, value, size); 2074 break; 2075 } 2076 break; 2077 case E82545_BAR_REGISTER: 2078 if (size != 4) { 2079 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx\r\n", size, offset, value); 2080 } else 2081 e82545_write_register(sc, (uint32_t)offset, 2082 (uint32_t)value); 2083 break; 2084 default: 2085 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d\r\n", 2086 baridx, offset, value, size); 2087 } 2088 2089 pthread_mutex_unlock(&sc->esc_mtx); 2090 } 2091 2092 static uint64_t 2093 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2094 uint64_t offset, int size) 2095 { 2096 struct e82545_softc *sc; 2097 uint64_t retval; 2098 2099 //DPRINTF("Read bar:%d offset:0x%lx size:%d\r\n", baridx, offset, size); 2100 sc = pi->pi_arg; 2101 retval = 0; 2102 2103 pthread_mutex_lock(&sc->esc_mtx); 2104 2105 switch (baridx) { 2106 case E82545_BAR_IO: 2107 switch (offset) { 2108 case E82545_IOADDR: 2109 if (size != 4) { 2110 DPRINTF("Wrong io addr read sz:%d\r\n", size); 2111 } else 2112 retval = sc->io_addr; 2113 break; 2114 case E82545_IODATA: 2115 if (size != 4) { 2116 DPRINTF("Wrong io data read sz:%d\r\n", size); 2117 } 2118 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2119 DPRINTF("Non-register io read addr:0x%x\r\n", 2120 sc->io_addr); 2121 } else 2122 retval = e82545_read_register(sc, sc->io_addr); 2123 break; 2124 default: 2125 DPRINTF("Unknown io bar read offset:0x%lx size:%d\r\n", 2126 offset, size); 2127 break; 2128 } 2129 break; 2130 case E82545_BAR_REGISTER: 2131 if (size != 4) { 2132 DPRINTF("Wrong register read size:%d offset:0x%lx\r\n", 2133 size, offset); 2134 } else 2135 retval = e82545_read_register(sc, (uint32_t)offset); 2136 break; 2137 default: 2138 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d\r\n", 2139 baridx, offset, size); 2140 break; 2141 } 2142 2143 pthread_mutex_unlock(&sc->esc_mtx); 2144 2145 return (retval); 2146 } 2147 2148 static void 2149 e82545_reset(struct e82545_softc *sc, int drvr) 2150 { 2151 int i; 2152 2153 e82545_rx_disable(sc); 2154 e82545_tx_disable(sc); 2155 2156 /* clear outstanding interrupts */ 2157 if (sc->esc_irq_asserted) 2158 pci_lintr_deassert(sc->esc_pi); 2159 2160 /* misc */ 2161 if (!drvr) { 2162 sc->esc_FCAL = 0; 2163 sc->esc_FCAH = 0; 2164 sc->esc_FCT = 0; 2165 sc->esc_VET = 0; 2166 sc->esc_FCTTV = 0; 2167 } 2168 sc->esc_LEDCTL = 0x07061302; 2169 sc->esc_PBA = 0x00100030; 2170 2171 /* start nvm in opcode mode. */ 2172 sc->nvm_opaddr = 0; 2173 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2174 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2175 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2176 e82545_init_eeprom(sc); 2177 2178 /* interrupt */ 2179 sc->esc_ICR = 0; 2180 sc->esc_ITR = 250; 2181 sc->esc_ICS = 0; 2182 sc->esc_IMS = 0; 2183 sc->esc_IMC = 0; 2184 2185 /* L2 filters */ 2186 if (!drvr) { 2187 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2188 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2189 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2190 2191 /* XXX not necessary on 82545 ?? */ 2192 sc->esc_uni[0].eu_valid = 1; 2193 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2194 ETHER_ADDR_LEN); 2195 } else { 2196 /* Clear RAH valid bits */ 2197 for (i = 0; i < 16; i++) 2198 sc->esc_uni[i].eu_valid = 0; 2199 } 2200 2201 /* receive */ 2202 if (!drvr) { 2203 sc->esc_RDBAL = 0; 2204 sc->esc_RDBAH = 0; 2205 } 2206 sc->esc_RCTL = 0; 2207 sc->esc_FCRTL = 0; 2208 sc->esc_FCRTH = 0; 2209 sc->esc_RDLEN = 0; 2210 sc->esc_RDH = 0; 2211 sc->esc_RDT = 0; 2212 sc->esc_RDTR = 0; 2213 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2214 sc->esc_RADV = 0; 2215 sc->esc_RXCSUM = 0; 2216 2217 /* transmit */ 2218 if (!drvr) { 2219 sc->esc_TDBAL = 0; 2220 sc->esc_TDBAH = 0; 2221 sc->esc_TIPG = 0; 2222 sc->esc_AIT = 0; 2223 sc->esc_TIDV = 0; 2224 sc->esc_TADV = 0; 2225 } 2226 sc->esc_tdba = 0; 2227 sc->esc_txdesc = NULL; 2228 sc->esc_TXCW = 0; 2229 sc->esc_TCTL = 0; 2230 sc->esc_TDLEN = 0; 2231 sc->esc_TDT = 0; 2232 sc->esc_TDHr = sc->esc_TDH = 0; 2233 sc->esc_TXDCTL = 0; 2234 } 2235 2236 static void 2237 e82545_open_tap(struct e82545_softc *sc, char *opts) 2238 { 2239 char tbuf[80]; 2240 #ifndef WITHOUT_CAPSICUM 2241 cap_rights_t rights; 2242 #endif 2243 2244 if (opts == NULL) { 2245 sc->esc_tapfd = -1; 2246 return; 2247 } 2248 2249 strcpy(tbuf, "/dev/"); 2250 strlcat(tbuf, opts, sizeof(tbuf)); 2251 2252 sc->esc_tapfd = open(tbuf, O_RDWR); 2253 if (sc->esc_tapfd == -1) { 2254 DPRINTF("unable to open tap device %s\n", opts); 2255 exit(4); 2256 } 2257 2258 /* 2259 * Set non-blocking and register for read 2260 * notifications with the event loop 2261 */ 2262 int opt = 1; 2263 if (ioctl(sc->esc_tapfd, FIONBIO, &opt) < 0) { 2264 WPRINTF("tap device O_NONBLOCK failed: %d\n", errno); 2265 close(sc->esc_tapfd); 2266 sc->esc_tapfd = -1; 2267 } 2268 2269 #ifndef WITHOUT_CAPSICUM 2270 cap_rights_init(&rights, CAP_EVENT, CAP_READ, CAP_WRITE); 2271 if (caph_rights_limit(sc->esc_tapfd, &rights) == -1) 2272 errx(EX_OSERR, "Unable to apply rights for sandbox"); 2273 #endif 2274 2275 #ifdef __FreeBSD__ 2276 sc->esc_mevp = mevent_add(sc->esc_tapfd, 2277 EVF_READ, 2278 e82545_tap_callback, 2279 sc); 2280 if (sc->esc_mevp == NULL) { 2281 DPRINTF("Could not register mevent %d\n", EVF_READ); 2282 close(sc->esc_tapfd); 2283 sc->esc_tapfd = -1; 2284 } 2285 #endif 2286 } 2287 2288 static int 2289 e82545_parsemac(char *mac_str, uint8_t *mac_addr) 2290 { 2291 struct ether_addr *ea; 2292 char *tmpstr; 2293 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 2294 2295 tmpstr = strsep(&mac_str,"="); 2296 if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) { 2297 ea = ether_aton(mac_str); 2298 if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) || 2299 memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) { 2300 fprintf(stderr, "Invalid MAC %s\n", mac_str); 2301 return (1); 2302 } else 2303 memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN); 2304 } 2305 return (0); 2306 } 2307 2308 static int 2309 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2310 { 2311 DPRINTF("Loading with options: %s\r\n", opts); 2312 2313 MD5_CTX mdctx; 2314 unsigned char digest[16]; 2315 char nstr[80]; 2316 struct e82545_softc *sc; 2317 char *devname; 2318 char *vtopts; 2319 int mac_provided; 2320 2321 /* Setup our softc */ 2322 sc = calloc(1, sizeof(*sc)); 2323 2324 pi->pi_arg = sc; 2325 sc->esc_pi = pi; 2326 sc->esc_ctx = ctx; 2327 2328 pthread_mutex_init(&sc->esc_mtx, NULL); 2329 pthread_cond_init(&sc->esc_rx_cond, NULL); 2330 pthread_cond_init(&sc->esc_tx_cond, NULL); 2331 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2332 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2333 pi->pi_func); 2334 pthread_set_name_np(sc->esc_tx_tid, nstr); 2335 2336 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2337 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2338 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2339 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2340 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2341 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2342 2343 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2344 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2345 2346 /* TODO: this card also supports msi, but the freebsd driver for it 2347 * does not, so I have not implemented it. */ 2348 pci_lintr_request(pi); 2349 2350 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2351 E82545_BAR_REGISTER_LEN); 2352 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2353 E82545_BAR_FLASH_LEN); 2354 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2355 E82545_BAR_IO_LEN); 2356 2357 /* 2358 * Attempt to open the tap device and read the MAC address 2359 * if specified. Copied from virtio-net, slightly modified. 2360 */ 2361 mac_provided = 0; 2362 sc->esc_tapfd = -1; 2363 if (opts != NULL) { 2364 int err; 2365 2366 devname = vtopts = strdup(opts); 2367 (void) strsep(&vtopts, ","); 2368 2369 if (vtopts != NULL) { 2370 err = e82545_parsemac(vtopts, sc->esc_mac.octet); 2371 if (err != 0) { 2372 free(devname); 2373 return (err); 2374 } 2375 mac_provided = 1; 2376 } 2377 2378 if (strncmp(devname, "tap", 3) == 0 || 2379 strncmp(devname, "vmnet", 5) == 0) 2380 e82545_open_tap(sc, devname); 2381 2382 free(devname); 2383 } 2384 2385 /* 2386 * The default MAC address is the standard NetApp OUI of 00-a0-98, 2387 * followed by an MD5 of the PCI slot/func number and dev name 2388 */ 2389 if (!mac_provided) { 2390 snprintf(nstr, sizeof(nstr), "%d-%d-%s", pi->pi_slot, 2391 pi->pi_func, vmname); 2392 2393 MD5Init(&mdctx); 2394 MD5Update(&mdctx, nstr, strlen(nstr)); 2395 MD5Final(digest, &mdctx); 2396 2397 sc->esc_mac.octet[0] = 0x00; 2398 sc->esc_mac.octet[1] = 0xa0; 2399 sc->esc_mac.octet[2] = 0x98; 2400 sc->esc_mac.octet[3] = digest[0]; 2401 sc->esc_mac.octet[4] = digest[1]; 2402 sc->esc_mac.octet[5] = digest[2]; 2403 } 2404 2405 /* H/w initiated reset */ 2406 e82545_reset(sc, 0); 2407 2408 return (0); 2409 } 2410 2411 struct pci_devemu pci_de_e82545 = { 2412 .pe_emu = "e1000", 2413 .pe_init = e82545_init, 2414 .pe_barwrite = e82545_write, 2415 .pe_barread = e82545_read 2416 }; 2417 PCI_EMUL_SET(pci_de_e82545); 2418 2419