1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 #include <sys/types.h> 35 #ifndef WITHOUT_CAPSICUM 36 #include <sys/capsicum.h> 37 #endif 38 #include <sys/limits.h> 39 #include <sys/ioctl.h> 40 #include <sys/uio.h> 41 #include <net/ethernet.h> 42 #include <netinet/in.h> 43 #include <netinet/tcp.h> 44 45 #ifndef WITHOUT_CAPSICUM 46 #include <capsicum_helpers.h> 47 #endif 48 49 #include <err.h> 50 #include <errno.h> 51 #include <fcntl.h> 52 #include <md5.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <sysexits.h> 57 #include <unistd.h> 58 #include <pthread.h> 59 #include <pthread_np.h> 60 61 #include "e1000_regs.h" 62 #include "e1000_defines.h" 63 #include "mii.h" 64 65 #include "bhyverun.h" 66 #include "config.h" 67 #include "debug.h" 68 #include "pci_emul.h" 69 #include "mevent.h" 70 #include "net_utils.h" 71 #include "net_backends.h" 72 73 /* Hardware/register definitions XXX: move some to common code. */ 74 #define E82545_VENDOR_ID_INTEL 0x8086 75 #define E82545_DEV_ID_82545EM_COPPER 0x100F 76 #define E82545_SUBDEV_ID 0x1008 77 78 #define E82545_REVISION_4 4 79 80 #define E82545_MDIC_DATA_MASK 0x0000FFFF 81 #define E82545_MDIC_OP_MASK 0x0c000000 82 #define E82545_MDIC_IE 0x20000000 83 84 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 85 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 86 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 87 88 #define E82545_BAR_REGISTER 0 89 #define E82545_BAR_REGISTER_LEN (128*1024) 90 #define E82545_BAR_FLASH 1 91 #define E82545_BAR_FLASH_LEN (64*1024) 92 #define E82545_BAR_IO 2 93 #define E82545_BAR_IO_LEN 8 94 95 #define E82545_IOADDR 0x00000000 96 #define E82545_IODATA 0x00000004 97 #define E82545_IO_REGISTER_MAX 0x0001FFFF 98 #define E82545_IO_FLASH_BASE 0x00080000 99 #define E82545_IO_FLASH_MAX 0x000FFFFF 100 101 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 102 #define E82545_RAR_MAX 15 103 #define E82545_MTA_MAX 127 104 #define E82545_VFTA_MAX 127 105 106 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 107 * followed by 6 address bits. 108 * TODO: make opcode bits and addr bits configurable? 109 * NVM Commands - Microwire */ 110 #define E82545_NVM_OPCODE_BITS 3 111 #define E82545_NVM_ADDR_BITS 6 112 #define E82545_NVM_DATA_BITS 16 113 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 114 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 115 #define E82545_NVM_OPCODE_MASK \ 116 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 117 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 118 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 119 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 120 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 121 122 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 123 124 #define E1000_ICR_SRPD 0x00010000 125 126 /* This is an arbitrary number. There is no hard limit on the chip. */ 127 #define I82545_MAX_TXSEGS 64 128 129 /* Legacy receive descriptor */ 130 struct e1000_rx_desc { 131 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 132 uint16_t length; /* Length of data DMAed into data buffer */ 133 uint16_t csum; /* Packet checksum */ 134 uint8_t status; /* Descriptor status */ 135 uint8_t errors; /* Descriptor Errors */ 136 uint16_t special; 137 }; 138 139 /* Transmit descriptor types */ 140 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 141 #define E1000_TXD_TYP_L (0) 142 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 143 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 144 145 /* Legacy transmit descriptor */ 146 struct e1000_tx_desc { 147 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 148 union { 149 uint32_t data; 150 struct { 151 uint16_t length; /* Data buffer length */ 152 uint8_t cso; /* Checksum offset */ 153 uint8_t cmd; /* Descriptor control */ 154 } flags; 155 } lower; 156 union { 157 uint32_t data; 158 struct { 159 uint8_t status; /* Descriptor status */ 160 uint8_t css; /* Checksum start */ 161 uint16_t special; 162 } fields; 163 } upper; 164 }; 165 166 /* Context descriptor */ 167 struct e1000_context_desc { 168 union { 169 uint32_t ip_config; 170 struct { 171 uint8_t ipcss; /* IP checksum start */ 172 uint8_t ipcso; /* IP checksum offset */ 173 uint16_t ipcse; /* IP checksum end */ 174 } ip_fields; 175 } lower_setup; 176 union { 177 uint32_t tcp_config; 178 struct { 179 uint8_t tucss; /* TCP checksum start */ 180 uint8_t tucso; /* TCP checksum offset */ 181 uint16_t tucse; /* TCP checksum end */ 182 } tcp_fields; 183 } upper_setup; 184 uint32_t cmd_and_length; 185 union { 186 uint32_t data; 187 struct { 188 uint8_t status; /* Descriptor status */ 189 uint8_t hdr_len; /* Header length */ 190 uint16_t mss; /* Maximum segment size */ 191 } fields; 192 } tcp_seg_setup; 193 }; 194 195 /* Data descriptor */ 196 struct e1000_data_desc { 197 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 198 union { 199 uint32_t data; 200 struct { 201 uint16_t length; /* Data buffer length */ 202 uint8_t typ_len_ext; 203 uint8_t cmd; 204 } flags; 205 } lower; 206 union { 207 uint32_t data; 208 struct { 209 uint8_t status; /* Descriptor status */ 210 uint8_t popts; /* Packet Options */ 211 uint16_t special; 212 } fields; 213 } upper; 214 }; 215 216 union e1000_tx_udesc { 217 struct e1000_tx_desc td; 218 struct e1000_context_desc cd; 219 struct e1000_data_desc dd; 220 }; 221 222 /* Tx checksum info for a packet. */ 223 struct ck_info { 224 int ck_valid; /* ck_info is valid */ 225 uint8_t ck_start; /* start byte of cksum calcuation */ 226 uint8_t ck_off; /* offset of cksum insertion */ 227 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 228 }; 229 230 /* 231 * Debug printf 232 */ 233 static int e82545_debug = 0; 234 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, ##params) 235 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params) 236 237 #define MIN(a,b) (((a)<(b))?(a):(b)) 238 #define MAX(a,b) (((a)>(b))?(a):(b)) 239 240 /* s/w representation of the RAL/RAH regs */ 241 struct eth_uni { 242 int eu_valid; 243 int eu_addrsel; 244 struct ether_addr eu_eth; 245 }; 246 247 248 struct e82545_softc { 249 struct pci_devinst *esc_pi; 250 struct vmctx *esc_ctx; 251 struct mevent *esc_mevpitr; 252 pthread_mutex_t esc_mtx; 253 struct ether_addr esc_mac; 254 net_backend_t *esc_be; 255 256 /* General */ 257 uint32_t esc_CTRL; /* x0000 device ctl */ 258 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 259 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 260 uint32_t esc_FCT; /* x0030 flow ctl type */ 261 uint32_t esc_VET; /* x0038 VLAN eth type */ 262 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 263 uint32_t esc_LEDCTL; /* x0E00 LED control */ 264 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 265 266 /* Interrupt control */ 267 int esc_irq_asserted; 268 uint32_t esc_ICR; /* x00C0 cause read/clear */ 269 uint32_t esc_ITR; /* x00C4 intr throttling */ 270 uint32_t esc_ICS; /* x00C8 cause set */ 271 uint32_t esc_IMS; /* x00D0 mask set/read */ 272 uint32_t esc_IMC; /* x00D8 mask clear */ 273 274 /* Transmit */ 275 union e1000_tx_udesc *esc_txdesc; 276 struct e1000_context_desc esc_txctx; 277 pthread_t esc_tx_tid; 278 pthread_cond_t esc_tx_cond; 279 int esc_tx_enabled; 280 int esc_tx_active; 281 uint32_t esc_TXCW; /* x0178 transmit config */ 282 uint32_t esc_TCTL; /* x0400 transmit ctl */ 283 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 284 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 285 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 286 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 287 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 288 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 289 uint16_t esc_TDH; /* x3810 desc table head idx */ 290 uint16_t esc_TDHr; /* internal read version of TDH */ 291 uint16_t esc_TDT; /* x3818 desc table tail idx */ 292 uint32_t esc_TIDV; /* x3820 intr delay */ 293 uint32_t esc_TXDCTL; /* x3828 desc control */ 294 uint32_t esc_TADV; /* x382C intr absolute delay */ 295 296 /* L2 frame acceptance */ 297 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 298 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 299 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 300 301 /* Receive */ 302 struct e1000_rx_desc *esc_rxdesc; 303 pthread_cond_t esc_rx_cond; 304 int esc_rx_enabled; 305 int esc_rx_active; 306 int esc_rx_loopback; 307 uint32_t esc_RCTL; /* x0100 receive ctl */ 308 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 309 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 310 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 311 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 312 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 313 uint32_t esc_RDLEN; /* x2808 #descriptors */ 314 uint16_t esc_RDH; /* x2810 desc table head idx */ 315 uint16_t esc_RDT; /* x2818 desc table tail idx */ 316 uint32_t esc_RDTR; /* x2820 intr delay */ 317 uint32_t esc_RXDCTL; /* x2828 desc control */ 318 uint32_t esc_RADV; /* x282C intr absolute delay */ 319 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 320 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 321 322 /* IO Port register access */ 323 uint32_t io_addr; 324 325 /* Shadow copy of MDIC */ 326 uint32_t mdi_control; 327 /* Shadow copy of EECD */ 328 uint32_t eeprom_control; 329 /* Latest NVM in/out */ 330 uint16_t nvm_data; 331 uint16_t nvm_opaddr; 332 /* stats */ 333 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 334 uint32_t pkt_rx_by_size[6]; 335 uint32_t pkt_tx_by_size[6]; 336 uint32_t good_pkt_rx_count; 337 uint32_t bcast_pkt_rx_count; 338 uint32_t mcast_pkt_rx_count; 339 uint32_t good_pkt_tx_count; 340 uint32_t bcast_pkt_tx_count; 341 uint32_t mcast_pkt_tx_count; 342 uint32_t oversize_rx_count; 343 uint32_t tso_tx_count; 344 uint64_t good_octets_rx; 345 uint64_t good_octets_tx; 346 uint64_t missed_octets; /* counts missed and oversized */ 347 348 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 349 uint8_t nvm_mode:2; 350 #define E82545_NVM_MODE_OPADDR 0x0 351 #define E82545_NVM_MODE_DATAIN 0x1 352 #define E82545_NVM_MODE_DATAOUT 0x2 353 /* EEPROM data */ 354 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 355 }; 356 357 static void e82545_reset(struct e82545_softc *sc, int dev); 358 static void e82545_rx_enable(struct e82545_softc *sc); 359 static void e82545_rx_disable(struct e82545_softc *sc); 360 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 361 static void e82545_tx_start(struct e82545_softc *sc); 362 static void e82545_tx_enable(struct e82545_softc *sc); 363 static void e82545_tx_disable(struct e82545_softc *sc); 364 365 static inline int __unused 366 e82545_size_stat_index(uint32_t size) 367 { 368 if (size <= 64) { 369 return 0; 370 } else if (size >= 1024) { 371 return 5; 372 } else { 373 /* should be 1-4 */ 374 return (ffs(size) - 6); 375 } 376 } 377 378 static void 379 e82545_init_eeprom(struct e82545_softc *sc) 380 { 381 uint16_t checksum, i; 382 383 /* mac addr */ 384 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 385 (((uint16_t)sc->esc_mac.octet[1]) << 8); 386 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 387 (((uint16_t)sc->esc_mac.octet[3]) << 8); 388 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 389 (((uint16_t)sc->esc_mac.octet[5]) << 8); 390 391 /* pci ids */ 392 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 393 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 394 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 395 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 396 397 /* fill in the checksum */ 398 checksum = 0; 399 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 400 checksum += sc->eeprom_data[i]; 401 } 402 checksum = NVM_SUM - checksum; 403 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 404 DPRINTF("eeprom checksum: 0x%x", checksum); 405 } 406 407 static void 408 e82545_write_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr, 409 uint8_t phy_addr, uint32_t data) 410 { 411 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); 412 } 413 414 static uint32_t 415 e82545_read_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr, 416 uint8_t phy_addr) 417 { 418 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr); 419 switch (reg_addr) { 420 case PHY_STATUS: 421 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 422 MII_SR_AUTONEG_COMPLETE); 423 case PHY_AUTONEG_ADV: 424 return NWAY_AR_SELECTOR_FIELD; 425 case PHY_LP_ABILITY: 426 return 0; 427 case PHY_1000T_STATUS: 428 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 429 SR_1000T_LOCAL_RX_STATUS); 430 case PHY_ID1: 431 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 432 case PHY_ID2: 433 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 434 default: 435 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); 436 return 0; 437 } 438 /* not reached */ 439 } 440 441 static void 442 e82545_eecd_strobe(struct e82545_softc *sc) 443 { 444 /* Microwire state machine */ 445 /* 446 DPRINTF("eeprom state machine srtobe " 447 "0x%x 0x%x 0x%x 0x%x", 448 sc->nvm_mode, sc->nvm_bits, 449 sc->nvm_opaddr, sc->nvm_data);*/ 450 451 if (sc->nvm_bits == 0) { 452 DPRINTF("eeprom state machine not expecting data! " 453 "0x%x 0x%x 0x%x 0x%x", 454 sc->nvm_mode, sc->nvm_bits, 455 sc->nvm_opaddr, sc->nvm_data); 456 return; 457 } 458 sc->nvm_bits--; 459 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 460 /* shifting out */ 461 if (sc->nvm_data & 0x8000) { 462 sc->eeprom_control |= E1000_EECD_DO; 463 } else { 464 sc->eeprom_control &= ~E1000_EECD_DO; 465 } 466 sc->nvm_data <<= 1; 467 if (sc->nvm_bits == 0) { 468 /* read done, back to opcode mode. */ 469 sc->nvm_opaddr = 0; 470 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 471 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 472 } 473 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 474 /* shifting in */ 475 sc->nvm_data <<= 1; 476 if (sc->eeprom_control & E1000_EECD_DI) { 477 sc->nvm_data |= 1; 478 } 479 if (sc->nvm_bits == 0) { 480 /* eeprom write */ 481 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 482 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 483 if (op != E82545_NVM_OPCODE_WRITE) { 484 DPRINTF("Illegal eeprom write op 0x%x", 485 sc->nvm_opaddr); 486 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 487 DPRINTF("Illegal eeprom write addr 0x%x", 488 sc->nvm_opaddr); 489 } else { 490 DPRINTF("eeprom write eeprom[0x%x] = 0x%x", 491 addr, sc->nvm_data); 492 sc->eeprom_data[addr] = sc->nvm_data; 493 } 494 /* back to opcode mode */ 495 sc->nvm_opaddr = 0; 496 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 497 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 498 } 499 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 500 sc->nvm_opaddr <<= 1; 501 if (sc->eeprom_control & E1000_EECD_DI) { 502 sc->nvm_opaddr |= 1; 503 } 504 if (sc->nvm_bits == 0) { 505 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 506 switch (op) { 507 case E82545_NVM_OPCODE_EWEN: 508 DPRINTF("eeprom write enable: 0x%x", 509 sc->nvm_opaddr); 510 /* back to opcode mode */ 511 sc->nvm_opaddr = 0; 512 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 513 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 514 break; 515 case E82545_NVM_OPCODE_READ: 516 { 517 uint16_t addr = sc->nvm_opaddr & 518 E82545_NVM_ADDR_MASK; 519 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 520 sc->nvm_bits = E82545_NVM_DATA_BITS; 521 if (addr < E82545_NVM_EEPROM_SIZE) { 522 sc->nvm_data = sc->eeprom_data[addr]; 523 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x", 524 addr, sc->nvm_data); 525 } else { 526 DPRINTF("eeprom illegal read: 0x%x", 527 sc->nvm_opaddr); 528 sc->nvm_data = 0; 529 } 530 break; 531 } 532 case E82545_NVM_OPCODE_WRITE: 533 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 534 sc->nvm_bits = E82545_NVM_DATA_BITS; 535 sc->nvm_data = 0; 536 break; 537 default: 538 DPRINTF("eeprom unknown op: 0x%x", 539 sc->nvm_opaddr); 540 /* back to opcode mode */ 541 sc->nvm_opaddr = 0; 542 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 543 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 544 } 545 } 546 } else { 547 DPRINTF("eeprom state machine wrong state! " 548 "0x%x 0x%x 0x%x 0x%x", 549 sc->nvm_mode, sc->nvm_bits, 550 sc->nvm_opaddr, sc->nvm_data); 551 } 552 } 553 554 static void 555 e82545_itr_callback(int fd __unused, enum ev_type type __unused, void *param) 556 { 557 uint32_t new; 558 struct e82545_softc *sc = param; 559 560 pthread_mutex_lock(&sc->esc_mtx); 561 new = sc->esc_ICR & sc->esc_IMS; 562 if (new && !sc->esc_irq_asserted) { 563 DPRINTF("itr callback: lintr assert %x", new); 564 sc->esc_irq_asserted = 1; 565 pci_lintr_assert(sc->esc_pi); 566 } else { 567 mevent_delete(sc->esc_mevpitr); 568 sc->esc_mevpitr = NULL; 569 } 570 pthread_mutex_unlock(&sc->esc_mtx); 571 } 572 573 static void 574 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 575 { 576 uint32_t new; 577 578 DPRINTF("icr assert: 0x%x", bits); 579 580 /* 581 * An interrupt is only generated if bits are set that 582 * aren't already in the ICR, these bits are unmasked, 583 * and there isn't an interrupt already pending. 584 */ 585 new = bits & ~sc->esc_ICR & sc->esc_IMS; 586 sc->esc_ICR |= bits; 587 588 if (new == 0) { 589 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS); 590 } else if (sc->esc_mevpitr != NULL) { 591 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS); 592 } else if (!sc->esc_irq_asserted) { 593 DPRINTF("icr assert: lintr assert %x", new); 594 sc->esc_irq_asserted = 1; 595 pci_lintr_assert(sc->esc_pi); 596 if (sc->esc_ITR != 0) { 597 sc->esc_mevpitr = mevent_add( 598 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 599 EVF_TIMER, e82545_itr_callback, sc); 600 } 601 } 602 } 603 604 static void 605 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 606 { 607 uint32_t new; 608 609 /* 610 * Changing the mask may allow previously asserted 611 * but masked interrupt requests to generate an interrupt. 612 */ 613 new = bits & sc->esc_ICR & ~sc->esc_IMS; 614 sc->esc_IMS |= bits; 615 616 if (new == 0) { 617 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS); 618 } else if (sc->esc_mevpitr != NULL) { 619 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS); 620 } else if (!sc->esc_irq_asserted) { 621 DPRINTF("ims change: lintr assert %x", new); 622 sc->esc_irq_asserted = 1; 623 pci_lintr_assert(sc->esc_pi); 624 if (sc->esc_ITR != 0) { 625 sc->esc_mevpitr = mevent_add( 626 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 627 EVF_TIMER, e82545_itr_callback, sc); 628 } 629 } 630 } 631 632 static void 633 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 634 { 635 636 DPRINTF("icr deassert: 0x%x", bits); 637 sc->esc_ICR &= ~bits; 638 639 /* 640 * If there are no longer any interrupt sources and there 641 * was an asserted interrupt, clear it 642 */ 643 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 644 DPRINTF("icr deassert: lintr deassert %x", bits); 645 pci_lintr_deassert(sc->esc_pi); 646 sc->esc_irq_asserted = 0; 647 } 648 } 649 650 static void 651 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 652 { 653 654 DPRINTF("intr_write: off %x, val %x", offset, value); 655 656 switch (offset) { 657 case E1000_ICR: 658 e82545_icr_deassert(sc, value); 659 break; 660 case E1000_ITR: 661 sc->esc_ITR = value; 662 break; 663 case E1000_ICS: 664 sc->esc_ICS = value; /* not used: store for debug */ 665 e82545_icr_assert(sc, value); 666 break; 667 case E1000_IMS: 668 e82545_ims_change(sc, value); 669 break; 670 case E1000_IMC: 671 sc->esc_IMC = value; /* for debug */ 672 sc->esc_IMS &= ~value; 673 // XXX clear interrupts if all ICR bits now masked 674 // and interrupt was pending ? 675 break; 676 default: 677 break; 678 } 679 } 680 681 static uint32_t 682 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 683 { 684 uint32_t retval; 685 686 retval = 0; 687 688 DPRINTF("intr_read: off %x", offset); 689 690 switch (offset) { 691 case E1000_ICR: 692 retval = sc->esc_ICR; 693 sc->esc_ICR = 0; 694 e82545_icr_deassert(sc, ~0); 695 break; 696 case E1000_ITR: 697 retval = sc->esc_ITR; 698 break; 699 case E1000_ICS: 700 /* write-only register */ 701 break; 702 case E1000_IMS: 703 retval = sc->esc_IMS; 704 break; 705 case E1000_IMC: 706 /* write-only register */ 707 break; 708 default: 709 break; 710 } 711 712 return (retval); 713 } 714 715 static void 716 e82545_devctl(struct e82545_softc *sc, uint32_t val) 717 { 718 719 sc->esc_CTRL = val & ~E1000_CTRL_RST; 720 721 if (val & E1000_CTRL_RST) { 722 DPRINTF("e1k: s/w reset, ctl %x", val); 723 e82545_reset(sc, 1); 724 } 725 /* XXX check for phy reset ? */ 726 } 727 728 static void 729 e82545_rx_update_rdba(struct e82545_softc *sc) 730 { 731 732 /* XXX verify desc base/len within phys mem range */ 733 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 734 sc->esc_RDBAL; 735 736 /* Cache host mapping of guest descriptor array */ 737 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 738 sc->esc_rdba, sc->esc_RDLEN); 739 } 740 741 static void 742 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 743 { 744 int on; 745 746 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 747 748 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 749 sc->esc_RCTL = val & ~0xF9204c01; 750 751 DPRINTF("rx_ctl - %s RCTL %x, val %x", 752 on ? "on" : "off", sc->esc_RCTL, val); 753 754 /* state change requested */ 755 if (on != sc->esc_rx_enabled) { 756 if (on) { 757 /* Catch disallowed/unimplemented settings */ 758 //assert(!(val & E1000_RCTL_LBM_TCVR)); 759 760 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 761 sc->esc_rx_loopback = 1; 762 } else { 763 sc->esc_rx_loopback = 0; 764 } 765 766 e82545_rx_update_rdba(sc); 767 e82545_rx_enable(sc); 768 } else { 769 e82545_rx_disable(sc); 770 sc->esc_rx_loopback = 0; 771 sc->esc_rdba = 0; 772 sc->esc_rxdesc = NULL; 773 } 774 } 775 } 776 777 static void 778 e82545_tx_update_tdba(struct e82545_softc *sc) 779 { 780 781 /* XXX verify desc base/len within phys mem range */ 782 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 783 784 /* Cache host mapping of guest descriptor array */ 785 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 786 sc->esc_TDLEN); 787 } 788 789 static void 790 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 791 { 792 int on; 793 794 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 795 796 /* ignore TCTL_EN settings that don't change state */ 797 if (on == sc->esc_tx_enabled) 798 return; 799 800 if (on) { 801 e82545_tx_update_tdba(sc); 802 e82545_tx_enable(sc); 803 } else { 804 e82545_tx_disable(sc); 805 sc->esc_tdba = 0; 806 sc->esc_txdesc = NULL; 807 } 808 809 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 810 sc->esc_TCTL = val & ~0xFE800005; 811 } 812 813 static int 814 e82545_bufsz(uint32_t rctl) 815 { 816 817 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 818 case (E1000_RCTL_SZ_2048): return (2048); 819 case (E1000_RCTL_SZ_1024): return (1024); 820 case (E1000_RCTL_SZ_512): return (512); 821 case (E1000_RCTL_SZ_256): return (256); 822 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 823 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 824 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 825 } 826 return (256); /* Forbidden value. */ 827 } 828 829 /* XXX one packet at a time until this is debugged */ 830 static void 831 e82545_rx_callback(int fd __unused, enum ev_type type __unused, void *param) 832 { 833 struct e82545_softc *sc = param; 834 struct e1000_rx_desc *rxd; 835 struct iovec vec[64]; 836 ssize_t len; 837 int left, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 838 uint32_t cause = 0; 839 uint16_t *tp, tag, head; 840 841 pthread_mutex_lock(&sc->esc_mtx); 842 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 843 844 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 845 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped", 846 sc->esc_rx_enabled, sc->esc_rx_loopback); 847 while (netbe_rx_discard(sc->esc_be) > 0) { 848 } 849 goto done1; 850 } 851 bufsz = e82545_bufsz(sc->esc_RCTL); 852 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 853 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 854 size = sc->esc_RDLEN / 16; 855 head = sc->esc_RDH; 856 left = (size + sc->esc_RDT - head) % size; 857 if (left < maxpktdesc) { 858 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped", 859 left, maxpktdesc); 860 while (netbe_rx_discard(sc->esc_be) > 0) { 861 } 862 goto done1; 863 } 864 865 sc->esc_rx_active = 1; 866 pthread_mutex_unlock(&sc->esc_mtx); 867 868 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 869 870 /* Grab rx descriptor pointed to by the head pointer */ 871 for (i = 0; i < maxpktdesc; i++) { 872 rxd = &sc->esc_rxdesc[(head + i) % size]; 873 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 874 rxd->buffer_addr, bufsz); 875 vec[i].iov_len = bufsz; 876 } 877 len = netbe_recv(sc->esc_be, vec, maxpktdesc); 878 if (len <= 0) { 879 DPRINTF("netbe_recv() returned %zd", len); 880 goto done; 881 } 882 883 /* 884 * Adjust the packet length based on whether the CRC needs 885 * to be stripped or if the packet is less than the minimum 886 * eth packet size. 887 */ 888 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 889 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 890 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 891 len += ETHER_CRC_LEN; 892 n = (len + bufsz - 1) / bufsz; 893 894 DPRINTF("packet read %zd bytes, %d segs, head %d", 895 len, n, head); 896 897 /* Apply VLAN filter. */ 898 tp = (uint16_t *)vec[0].iov_base + 6; 899 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 900 (ntohs(tp[0]) == sc->esc_VET)) { 901 tag = ntohs(tp[1]) & 0x0fff; 902 if ((sc->esc_fvlan[tag >> 5] & 903 (1 << (tag & 0x1f))) != 0) { 904 DPRINTF("known VLAN %d", tag); 905 } else { 906 DPRINTF("unknown VLAN %d", tag); 907 n = 0; 908 continue; 909 } 910 } 911 912 /* Update all consumed descriptors. */ 913 for (i = 0; i < n - 1; i++) { 914 rxd = &sc->esc_rxdesc[(head + i) % size]; 915 rxd->length = bufsz; 916 rxd->csum = 0; 917 rxd->errors = 0; 918 rxd->special = 0; 919 rxd->status = E1000_RXD_STAT_DD; 920 } 921 rxd = &sc->esc_rxdesc[(head + i) % size]; 922 rxd->length = len % bufsz; 923 rxd->csum = 0; 924 rxd->errors = 0; 925 rxd->special = 0; 926 /* XXX signal no checksum for now */ 927 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 928 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 929 930 /* Schedule receive interrupts. */ 931 if ((uint32_t)len <= sc->esc_RSRPD) { 932 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 933 } else { 934 /* XXX: RDRT and RADV timers should be here. */ 935 cause |= E1000_ICR_RXT0; 936 } 937 938 head = (head + n) % size; 939 left -= n; 940 } 941 942 done: 943 pthread_mutex_lock(&sc->esc_mtx); 944 sc->esc_rx_active = 0; 945 if (sc->esc_rx_enabled == 0) 946 pthread_cond_signal(&sc->esc_rx_cond); 947 948 sc->esc_RDH = head; 949 /* Respect E1000_RCTL_RDMTS */ 950 left = (size + sc->esc_RDT - head) % size; 951 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 952 cause |= E1000_ICR_RXDMT0; 953 /* Assert all accumulated interrupts. */ 954 if (cause != 0) 955 e82545_icr_assert(sc, cause); 956 done1: 957 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 958 pthread_mutex_unlock(&sc->esc_mtx); 959 } 960 961 static uint16_t 962 e82545_carry(uint32_t sum) 963 { 964 965 sum = (sum & 0xFFFF) + (sum >> 16); 966 if (sum > 0xFFFF) 967 sum -= 0xFFFF; 968 return (sum); 969 } 970 971 static uint16_t 972 e82545_buf_checksum(uint8_t *buf, int len) 973 { 974 int i; 975 uint32_t sum = 0; 976 977 /* Checksum all the pairs of bytes first... */ 978 for (i = 0; i < (len & ~1); i += 2) 979 sum += *((u_int16_t *)(buf + i)); 980 981 /* 982 * If there's a single byte left over, checksum it, too. 983 * Network byte order is big-endian, so the remaining byte is 984 * the high byte. 985 */ 986 if (i < len) 987 sum += htons(buf[i] << 8); 988 989 return (e82545_carry(sum)); 990 } 991 992 static uint16_t 993 e82545_iov_checksum(struct iovec *iov, int iovcnt, unsigned int off, 994 unsigned int len) 995 { 996 unsigned int now, odd; 997 uint32_t sum = 0, s; 998 999 /* Skip completely unneeded vectors. */ 1000 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1001 off -= iov->iov_len; 1002 iov++; 1003 iovcnt--; 1004 } 1005 1006 /* Calculate checksum of requested range. */ 1007 odd = 0; 1008 while (len > 0 && iovcnt > 0) { 1009 now = MIN(len, iov->iov_len - off); 1010 s = e82545_buf_checksum((uint8_t *)iov->iov_base + off, now); 1011 sum += odd ? (s << 8) : s; 1012 odd ^= (now & 1); 1013 len -= now; 1014 off = 0; 1015 iov++; 1016 iovcnt--; 1017 } 1018 1019 return (e82545_carry(sum)); 1020 } 1021 1022 /* 1023 * Return the transmit descriptor type. 1024 */ 1025 static int 1026 e82545_txdesc_type(uint32_t lower) 1027 { 1028 int type; 1029 1030 type = 0; 1031 1032 if (lower & E1000_TXD_CMD_DEXT) 1033 type = lower & E1000_TXD_MASK; 1034 1035 return (type); 1036 } 1037 1038 static void 1039 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1040 { 1041 uint16_t cksum; 1042 unsigned int cklen; 1043 1044 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d", 1045 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1046 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1U : UINT_MAX; 1047 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1048 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1049 } 1050 1051 static void 1052 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1053 { 1054 1055 if (sc->esc_be == NULL) 1056 return; 1057 1058 (void) netbe_send(sc->esc_be, iov, iovcnt); 1059 } 1060 1061 static void 1062 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1063 uint16_t dsize, int *tdwb) 1064 { 1065 union e1000_tx_udesc *dsc; 1066 1067 for ( ; head != tail; head = (head + 1) % dsize) { 1068 dsc = &sc->esc_txdesc[head]; 1069 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1070 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1071 *tdwb = 1; 1072 } 1073 } 1074 } 1075 1076 static int 1077 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1078 uint16_t dsize, uint16_t *rhead, int *tdwb) 1079 { 1080 uint8_t *hdr, *hdrp; 1081 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1082 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1083 struct e1000_context_desc *cd; 1084 struct ck_info ckinfo[2]; 1085 struct iovec *iov; 1086 union e1000_tx_udesc *dsc; 1087 int desc, dtype, ntype, iovcnt, tcp, tso, paylen, seg, tiovcnt, pv; 1088 unsigned hdrlen, vlen, pktlen, len, left, mss, now, nnow, nleft, pvoff; 1089 uint32_t tcpsum, tcpseq; 1090 uint16_t ipcs, tcpcs, ipid, ohead; 1091 bool invalid; 1092 1093 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1094 iovcnt = 0; 1095 ntype = 0; 1096 tso = 0; 1097 pktlen = 0; 1098 ohead = head; 1099 invalid = false; 1100 1101 /* iovb[0/1] may be used for writable copy of headers. */ 1102 iov = &iovb[2]; 1103 1104 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1105 if (head == tail) { 1106 *rhead = head; 1107 return (0); 1108 } 1109 dsc = &sc->esc_txdesc[head]; 1110 dtype = e82545_txdesc_type(dsc->td.lower.data); 1111 1112 if (desc == 0) { 1113 switch (dtype) { 1114 case E1000_TXD_TYP_C: 1115 DPRINTF("tx ctxt desc idx %d: %016jx " 1116 "%08x%08x", 1117 head, dsc->td.buffer_addr, 1118 dsc->td.upper.data, dsc->td.lower.data); 1119 /* Save context and return */ 1120 sc->esc_txctx = dsc->cd; 1121 goto done; 1122 case E1000_TXD_TYP_L: 1123 DPRINTF("tx legacy desc idx %d: %08x%08x", 1124 head, dsc->td.upper.data, dsc->td.lower.data); 1125 /* 1126 * legacy cksum start valid in first descriptor 1127 */ 1128 ntype = dtype; 1129 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1130 break; 1131 case E1000_TXD_TYP_D: 1132 DPRINTF("tx data desc idx %d: %08x%08x", 1133 head, dsc->td.upper.data, dsc->td.lower.data); 1134 ntype = dtype; 1135 break; 1136 default: 1137 break; 1138 } 1139 } else { 1140 /* Descriptor type must be consistent */ 1141 assert(dtype == ntype); 1142 DPRINTF("tx next desc idx %d: %08x%08x", 1143 head, dsc->td.upper.data, dsc->td.lower.data); 1144 } 1145 1146 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1147 dsc->dd.lower.data & 0xFFFFF; 1148 1149 /* Strip checksum supplied by guest. */ 1150 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1151 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) { 1152 if (len <= 2) { 1153 WPRINTF("final descriptor too short (%d) -- dropped", 1154 len); 1155 invalid = true; 1156 } else 1157 len -= 2; 1158 } 1159 1160 if (len > 0 && iovcnt < I82545_MAX_TXSEGS) { 1161 iov[iovcnt].iov_base = paddr_guest2host(sc->esc_ctx, 1162 dsc->td.buffer_addr, len); 1163 iov[iovcnt].iov_len = len; 1164 iovcnt++; 1165 pktlen += len; 1166 } 1167 1168 /* 1169 * Pull out info that is valid in the final descriptor 1170 * and exit descriptor loop. 1171 */ 1172 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1173 if (dtype == E1000_TXD_TYP_L) { 1174 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1175 ckinfo[0].ck_valid = 1; 1176 ckinfo[0].ck_off = 1177 dsc->td.lower.flags.cso; 1178 ckinfo[0].ck_len = 0; 1179 } 1180 } else { 1181 cd = &sc->esc_txctx; 1182 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1183 tso = 1; 1184 if (dsc->dd.upper.fields.popts & 1185 E1000_TXD_POPTS_IXSM) 1186 ckinfo[0].ck_valid = 1; 1187 if (dsc->dd.upper.fields.popts & 1188 E1000_TXD_POPTS_IXSM || tso) { 1189 ckinfo[0].ck_start = 1190 cd->lower_setup.ip_fields.ipcss; 1191 ckinfo[0].ck_off = 1192 cd->lower_setup.ip_fields.ipcso; 1193 ckinfo[0].ck_len = 1194 cd->lower_setup.ip_fields.ipcse; 1195 } 1196 if (dsc->dd.upper.fields.popts & 1197 E1000_TXD_POPTS_TXSM) 1198 ckinfo[1].ck_valid = 1; 1199 if (dsc->dd.upper.fields.popts & 1200 E1000_TXD_POPTS_TXSM || tso) { 1201 ckinfo[1].ck_start = 1202 cd->upper_setup.tcp_fields.tucss; 1203 ckinfo[1].ck_off = 1204 cd->upper_setup.tcp_fields.tucso; 1205 ckinfo[1].ck_len = 1206 cd->upper_setup.tcp_fields.tucse; 1207 } 1208 } 1209 break; 1210 } 1211 } 1212 1213 if (invalid) 1214 goto done; 1215 1216 if (iovcnt > I82545_MAX_TXSEGS) { 1217 WPRINTF("tx too many descriptors (%d > %d) -- dropped", 1218 iovcnt, I82545_MAX_TXSEGS); 1219 goto done; 1220 } 1221 1222 hdrlen = vlen = 0; 1223 /* Estimate writable space for VLAN header insertion. */ 1224 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1225 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1226 hdrlen = ETHER_ADDR_LEN*2; 1227 vlen = ETHER_VLAN_ENCAP_LEN; 1228 } 1229 if (!tso) { 1230 /* Estimate required writable space for checksums. */ 1231 if (ckinfo[0].ck_valid) 1232 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2U); 1233 if (ckinfo[1].ck_valid) 1234 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2U); 1235 /* Round up writable space to the first vector. */ 1236 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1237 iov[0].iov_len < hdrlen + 100) 1238 hdrlen = iov[0].iov_len; 1239 } else { 1240 /* In case of TSO header length provided by software. */ 1241 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1242 1243 /* 1244 * Cap the header length at 240 based on 7.2.4.5 of 1245 * the Intel 82576EB (Rev 2.63) datasheet. 1246 */ 1247 if (hdrlen > 240) { 1248 WPRINTF("TSO hdrlen too large: %d", hdrlen); 1249 goto done; 1250 } 1251 1252 /* 1253 * If VLAN insertion is requested, ensure the header 1254 * at least holds the amount of data copied during 1255 * VLAN insertion below. 1256 * 1257 * XXX: Realistic packets will include a full Ethernet 1258 * header before the IP header at ckinfo[0].ck_start, 1259 * but this check is sufficient to prevent 1260 * out-of-bounds access below. 1261 */ 1262 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) { 1263 WPRINTF("TSO hdrlen too small for vlan insertion " 1264 "(%d vs %d) -- dropped", hdrlen, 1265 ETHER_ADDR_LEN*2); 1266 goto done; 1267 } 1268 1269 /* 1270 * Ensure that the header length covers the used fields 1271 * in the IP and TCP headers as well as the IP and TCP 1272 * checksums. The following fields are accessed below: 1273 * 1274 * Header | Field | Offset | Length 1275 * -------+-------+--------+------- 1276 * IPv4 | len | 2 | 2 1277 * IPv4 | ID | 4 | 2 1278 * IPv6 | len | 4 | 2 1279 * TCP | seq # | 4 | 4 1280 * TCP | flags | 13 | 1 1281 * UDP | len | 4 | 4 1282 */ 1283 if (hdrlen < ckinfo[0].ck_start + 6U || 1284 hdrlen < ckinfo[0].ck_off + 2U) { 1285 WPRINTF("TSO hdrlen too small for IP fields (%d) " 1286 "-- dropped", hdrlen); 1287 goto done; 1288 } 1289 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) { 1290 if (hdrlen < ckinfo[1].ck_start + 14U) { 1291 WPRINTF("TSO hdrlen too small for TCP fields " 1292 "(%d) -- dropped", hdrlen); 1293 goto done; 1294 } 1295 } else { 1296 if (hdrlen < ckinfo[1].ck_start + 8U) { 1297 WPRINTF("TSO hdrlen too small for UDP fields " 1298 "(%d) -- dropped", hdrlen); 1299 goto done; 1300 } 1301 } 1302 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2U) { 1303 WPRINTF("TSO hdrlen too small for TCP/UDP fields " 1304 "(%d) -- dropped", hdrlen); 1305 goto done; 1306 } 1307 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2) { 1308 WPRINTF("TSO hdrlen too small for TCP/UDP fields " 1309 "(%d) -- dropped", hdrlen); 1310 goto done; 1311 } 1312 } 1313 1314 if (pktlen < hdrlen + vlen) { 1315 WPRINTF("packet too small for writable header"); 1316 goto done; 1317 } 1318 1319 /* Allocate, fill and prepend writable header vector. */ 1320 if (hdrlen + vlen != 0) { 1321 hdr = __builtin_alloca(hdrlen + vlen); 1322 hdr += vlen; 1323 for (left = hdrlen, hdrp = hdr; left > 0; 1324 left -= now, hdrp += now) { 1325 now = MIN(left, iov->iov_len); 1326 memcpy(hdrp, iov->iov_base, now); 1327 #ifdef __FreeBSD__ 1328 iov->iov_base = (uint8_t *)iov->iov_base + now; 1329 #else 1330 /* 1331 * The type of iov_base changed in SUS (XPG4v2) from 1332 * caddr_t (char * - note signed) to 'void *'. On 1333 * illumos, bhyve is not currently compiled with XPG4v2 1334 * or higher, and so we can't cast the RHS to unsigned. 1335 * error: pointer targets in assignment differ in 1336 * signedness 1337 * This also means that we need to apply some casts to 1338 * (caddr_t) below. 1339 */ 1340 iov->iov_base += now; 1341 #endif 1342 iov->iov_len -= now; 1343 if (iov->iov_len == 0) { 1344 iov++; 1345 iovcnt--; 1346 } 1347 } 1348 iov--; 1349 iovcnt++; 1350 #ifdef __FreeBSD__ 1351 iov->iov_base = hdr; 1352 #else 1353 iov->iov_base = (caddr_t)hdr; 1354 #endif 1355 iov->iov_len = hdrlen; 1356 } else 1357 hdr = NULL; 1358 1359 /* Insert VLAN tag. */ 1360 if (vlen != 0) { 1361 hdr -= ETHER_VLAN_ENCAP_LEN; 1362 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1363 hdrlen += ETHER_VLAN_ENCAP_LEN; 1364 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1365 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1366 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1367 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1368 #ifdef __FreeBSD__ 1369 iov->iov_base = hdr; 1370 #else 1371 iov->iov_base = (caddr_t)hdr; 1372 #endif 1373 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1374 /* Correct checksum offsets after VLAN tag insertion. */ 1375 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1376 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1377 if (ckinfo[0].ck_len != 0) 1378 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1379 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1380 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1381 if (ckinfo[1].ck_len != 0) 1382 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1383 } 1384 1385 /* Simple non-TSO case. */ 1386 if (!tso) { 1387 /* Calculate checksums and transmit. */ 1388 if (ckinfo[0].ck_valid) 1389 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1390 if (ckinfo[1].ck_valid) 1391 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1392 e82545_transmit_backend(sc, iov, iovcnt); 1393 goto done; 1394 } 1395 1396 /* Doing TSO. */ 1397 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1398 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1399 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1400 DPRINTF("tx %s segmentation offload %d+%d/%u bytes %d iovs", 1401 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1402 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1403 tcpseq = 0; 1404 if (tcp) 1405 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1406 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1407 tcpcs = 0; 1408 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1409 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1410 pv = 1; 1411 pvoff = 0; 1412 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1413 now = MIN(left, mss); 1414 1415 /* Construct IOVs for the segment. */ 1416 /* Include whole original header. */ 1417 #ifdef __FreeBSD__ 1418 tiov[0].iov_base = hdr; 1419 #else 1420 tiov[0].iov_base = (caddr_t)hdr; 1421 #endif 1422 tiov[0].iov_len = hdrlen; 1423 tiovcnt = 1; 1424 /* Include respective part of payload IOV. */ 1425 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1426 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1427 #ifdef __FreeBSD__ 1428 tiov[tiovcnt].iov_base = (uint8_t *)iov[pv].iov_base + 1429 pvoff; 1430 #else 1431 tiov[tiovcnt].iov_base += pvoff; 1432 #endif 1433 tiov[tiovcnt++].iov_len = nnow; 1434 if (pvoff + nnow == iov[pv].iov_len) { 1435 pv++; 1436 pvoff = 0; 1437 } else 1438 pvoff += nnow; 1439 } 1440 DPRINTF("tx segment %d %d+%d bytes %d iovs", 1441 seg, hdrlen, now, tiovcnt); 1442 1443 /* Update IP header. */ 1444 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1445 /* IPv4 -- set length and ID */ 1446 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1447 htons(hdrlen - ckinfo[0].ck_start + now); 1448 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1449 htons(ipid + seg); 1450 } else { 1451 /* IPv6 -- set length */ 1452 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1453 htons(hdrlen - ckinfo[0].ck_start - 40 + 1454 now); 1455 } 1456 1457 /* Update pseudo-header checksum. */ 1458 tcpsum = tcpcs; 1459 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1460 1461 /* Update TCP/UDP headers. */ 1462 if (tcp) { 1463 /* Update sequence number and FIN/PUSH flags. */ 1464 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1465 htonl(tcpseq + paylen - left); 1466 if (now < left) { 1467 hdr[ckinfo[1].ck_start + 13] &= 1468 ~(TH_FIN | TH_PUSH); 1469 } 1470 } else { 1471 /* Update payload length. */ 1472 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1473 hdrlen - ckinfo[1].ck_start + now; 1474 } 1475 1476 /* Calculate checksums and transmit. */ 1477 if (ckinfo[0].ck_valid) { 1478 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1479 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1480 } 1481 if (ckinfo[1].ck_valid) { 1482 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1483 e82545_carry(tcpsum); 1484 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1485 } 1486 e82545_transmit_backend(sc, tiov, tiovcnt); 1487 } 1488 1489 done: 1490 head = (head + 1) % dsize; 1491 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1492 1493 *rhead = head; 1494 return (desc + 1); 1495 } 1496 1497 static void 1498 e82545_tx_run(struct e82545_softc *sc) 1499 { 1500 uint32_t cause; 1501 uint16_t head, rhead, tail, size; 1502 int lim, tdwb, sent; 1503 1504 size = sc->esc_TDLEN / 16; 1505 if (size == 0) 1506 return; 1507 1508 head = sc->esc_TDH % size; 1509 tail = sc->esc_TDT % size; 1510 DPRINTF("tx_run: head %x, rhead %x, tail %x", 1511 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1512 1513 pthread_mutex_unlock(&sc->esc_mtx); 1514 rhead = head; 1515 tdwb = 0; 1516 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1517 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1518 if (sent == 0) 1519 break; 1520 head = rhead; 1521 } 1522 pthread_mutex_lock(&sc->esc_mtx); 1523 1524 sc->esc_TDH = head; 1525 sc->esc_TDHr = rhead; 1526 cause = 0; 1527 if (tdwb) 1528 cause |= E1000_ICR_TXDW; 1529 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1530 cause |= E1000_ICR_TXQE; 1531 if (cause) 1532 e82545_icr_assert(sc, cause); 1533 1534 DPRINTF("tx_run done: head %x, rhead %x, tail %x", 1535 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1536 } 1537 1538 static _Noreturn void * 1539 e82545_tx_thread(void *param) 1540 { 1541 struct e82545_softc *sc = param; 1542 1543 pthread_mutex_lock(&sc->esc_mtx); 1544 for (;;) { 1545 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1546 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1547 break; 1548 sc->esc_tx_active = 0; 1549 if (sc->esc_tx_enabled == 0) 1550 pthread_cond_signal(&sc->esc_tx_cond); 1551 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1552 } 1553 sc->esc_tx_active = 1; 1554 1555 /* Process some tx descriptors. Lock dropped inside. */ 1556 e82545_tx_run(sc); 1557 } 1558 } 1559 1560 static void 1561 e82545_tx_start(struct e82545_softc *sc) 1562 { 1563 1564 if (sc->esc_tx_active == 0) 1565 pthread_cond_signal(&sc->esc_tx_cond); 1566 } 1567 1568 static void 1569 e82545_tx_enable(struct e82545_softc *sc) 1570 { 1571 1572 sc->esc_tx_enabled = 1; 1573 } 1574 1575 static void 1576 e82545_tx_disable(struct e82545_softc *sc) 1577 { 1578 1579 sc->esc_tx_enabled = 0; 1580 while (sc->esc_tx_active) 1581 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1582 } 1583 1584 static void 1585 e82545_rx_enable(struct e82545_softc *sc) 1586 { 1587 1588 sc->esc_rx_enabled = 1; 1589 } 1590 1591 static void 1592 e82545_rx_disable(struct e82545_softc *sc) 1593 { 1594 1595 sc->esc_rx_enabled = 0; 1596 while (sc->esc_rx_active) 1597 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1598 } 1599 1600 static void 1601 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1602 { 1603 struct eth_uni *eu; 1604 int idx; 1605 1606 idx = reg >> 1; 1607 assert(idx < 15); 1608 1609 eu = &sc->esc_uni[idx]; 1610 1611 if (reg & 0x1) { 1612 /* RAH */ 1613 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1614 eu->eu_addrsel = (wval >> 16) & 0x3; 1615 eu->eu_eth.octet[5] = wval >> 8; 1616 eu->eu_eth.octet[4] = wval; 1617 } else { 1618 /* RAL */ 1619 eu->eu_eth.octet[3] = wval >> 24; 1620 eu->eu_eth.octet[2] = wval >> 16; 1621 eu->eu_eth.octet[1] = wval >> 8; 1622 eu->eu_eth.octet[0] = wval; 1623 } 1624 } 1625 1626 static uint32_t 1627 e82545_read_ra(struct e82545_softc *sc, int reg) 1628 { 1629 struct eth_uni *eu; 1630 uint32_t retval; 1631 int idx; 1632 1633 idx = reg >> 1; 1634 assert(idx < 15); 1635 1636 eu = &sc->esc_uni[idx]; 1637 1638 if (reg & 0x1) { 1639 /* RAH */ 1640 retval = (eu->eu_valid << 31) | 1641 (eu->eu_addrsel << 16) | 1642 (eu->eu_eth.octet[5] << 8) | 1643 eu->eu_eth.octet[4]; 1644 } else { 1645 /* RAL */ 1646 retval = (eu->eu_eth.octet[3] << 24) | 1647 (eu->eu_eth.octet[2] << 16) | 1648 (eu->eu_eth.octet[1] << 8) | 1649 eu->eu_eth.octet[0]; 1650 } 1651 1652 return (retval); 1653 } 1654 1655 static void 1656 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1657 { 1658 int ridx; 1659 1660 if (offset & 0x3) { 1661 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value); 1662 return; 1663 } 1664 DPRINTF("Register write: 0x%x value: 0x%x", offset, value); 1665 1666 switch (offset) { 1667 case E1000_CTRL: 1668 case E1000_CTRL_DUP: 1669 e82545_devctl(sc, value); 1670 break; 1671 case E1000_FCAL: 1672 sc->esc_FCAL = value; 1673 break; 1674 case E1000_FCAH: 1675 sc->esc_FCAH = value & ~0xFFFF0000; 1676 break; 1677 case E1000_FCT: 1678 sc->esc_FCT = value & ~0xFFFF0000; 1679 break; 1680 case E1000_VET: 1681 sc->esc_VET = value & ~0xFFFF0000; 1682 break; 1683 case E1000_FCTTV: 1684 sc->esc_FCTTV = value & ~0xFFFF0000; 1685 break; 1686 case E1000_LEDCTL: 1687 sc->esc_LEDCTL = value & ~0x30303000; 1688 break; 1689 case E1000_PBA: 1690 sc->esc_PBA = value & 0x0000FF80; 1691 break; 1692 case E1000_ICR: 1693 case E1000_ITR: 1694 case E1000_ICS: 1695 case E1000_IMS: 1696 case E1000_IMC: 1697 e82545_intr_write(sc, offset, value); 1698 break; 1699 case E1000_RCTL: 1700 e82545_rx_ctl(sc, value); 1701 break; 1702 case E1000_FCRTL: 1703 sc->esc_FCRTL = value & ~0xFFFF0007; 1704 break; 1705 case E1000_FCRTH: 1706 sc->esc_FCRTH = value & ~0xFFFF0007; 1707 break; 1708 case E1000_RDBAL(0): 1709 sc->esc_RDBAL = value & ~0xF; 1710 if (sc->esc_rx_enabled) { 1711 /* Apparently legal: update cached address */ 1712 e82545_rx_update_rdba(sc); 1713 } 1714 break; 1715 case E1000_RDBAH(0): 1716 assert(!sc->esc_rx_enabled); 1717 sc->esc_RDBAH = value; 1718 break; 1719 case E1000_RDLEN(0): 1720 assert(!sc->esc_rx_enabled); 1721 sc->esc_RDLEN = value & ~0xFFF0007F; 1722 break; 1723 case E1000_RDH(0): 1724 /* XXX should only ever be zero ? Range check ? */ 1725 sc->esc_RDH = value; 1726 break; 1727 case E1000_RDT(0): 1728 /* XXX if this opens up the rx ring, do something ? */ 1729 sc->esc_RDT = value; 1730 break; 1731 case E1000_RDTR: 1732 /* ignore FPD bit 31 */ 1733 sc->esc_RDTR = value & ~0xFFFF0000; 1734 break; 1735 case E1000_RXDCTL(0): 1736 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1737 break; 1738 case E1000_RADV: 1739 sc->esc_RADV = value & ~0xFFFF0000; 1740 break; 1741 case E1000_RSRPD: 1742 sc->esc_RSRPD = value & ~0xFFFFF000; 1743 break; 1744 case E1000_RXCSUM: 1745 sc->esc_RXCSUM = value & ~0xFFFFF800; 1746 break; 1747 case E1000_TXCW: 1748 sc->esc_TXCW = value & ~0x3FFF0000; 1749 break; 1750 case E1000_TCTL: 1751 e82545_tx_ctl(sc, value); 1752 break; 1753 case E1000_TIPG: 1754 sc->esc_TIPG = value; 1755 break; 1756 case E1000_AIT: 1757 sc->esc_AIT = value; 1758 break; 1759 case E1000_TDBAL(0): 1760 sc->esc_TDBAL = value & ~0xF; 1761 if (sc->esc_tx_enabled) 1762 e82545_tx_update_tdba(sc); 1763 break; 1764 case E1000_TDBAH(0): 1765 sc->esc_TDBAH = value; 1766 if (sc->esc_tx_enabled) 1767 e82545_tx_update_tdba(sc); 1768 break; 1769 case E1000_TDLEN(0): 1770 sc->esc_TDLEN = value & ~0xFFF0007F; 1771 if (sc->esc_tx_enabled) 1772 e82545_tx_update_tdba(sc); 1773 break; 1774 case E1000_TDH(0): 1775 if (sc->esc_tx_enabled) { 1776 WPRINTF("ignoring write to TDH while transmit enabled"); 1777 break; 1778 } 1779 if (value != 0) { 1780 WPRINTF("ignoring non-zero value written to TDH"); 1781 break; 1782 } 1783 sc->esc_TDHr = sc->esc_TDH = value; 1784 break; 1785 case E1000_TDT(0): 1786 sc->esc_TDT = value; 1787 if (sc->esc_tx_enabled) 1788 e82545_tx_start(sc); 1789 break; 1790 case E1000_TIDV: 1791 sc->esc_TIDV = value & ~0xFFFF0000; 1792 break; 1793 case E1000_TXDCTL(0): 1794 //assert(!sc->esc_tx_enabled); 1795 sc->esc_TXDCTL = value & ~0xC0C0C0; 1796 break; 1797 case E1000_TADV: 1798 sc->esc_TADV = value & ~0xFFFF0000; 1799 break; 1800 case E1000_RAL(0) ... E1000_RAH(15): 1801 /* convert to u32 offset */ 1802 ridx = (offset - E1000_RAL(0)) >> 2; 1803 e82545_write_ra(sc, ridx, value); 1804 break; 1805 case E1000_MTA ... (E1000_MTA + (127*4)): 1806 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1807 break; 1808 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1809 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1810 break; 1811 case E1000_EECD: 1812 { 1813 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value); 1814 /* edge triggered low->high */ 1815 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1816 0 : (value & E1000_EECD_SK)); 1817 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1818 E1000_EECD_DI|E1000_EECD_REQ); 1819 sc->eeprom_control &= ~eecd_mask; 1820 sc->eeprom_control |= (value & eecd_mask); 1821 /* grant/revoke immediately */ 1822 if (value & E1000_EECD_REQ) { 1823 sc->eeprom_control |= E1000_EECD_GNT; 1824 } else { 1825 sc->eeprom_control &= ~E1000_EECD_GNT; 1826 } 1827 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1828 e82545_eecd_strobe(sc); 1829 } 1830 return; 1831 } 1832 case E1000_MDIC: 1833 { 1834 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1835 E1000_MDIC_REG_SHIFT); 1836 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1837 E1000_MDIC_PHY_SHIFT); 1838 sc->mdi_control = 1839 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1840 if ((value & E1000_MDIC_READY) != 0) { 1841 DPRINTF("Incorrect MDIC ready bit: 0x%x", value); 1842 return; 1843 } 1844 switch (value & E82545_MDIC_OP_MASK) { 1845 case E1000_MDIC_OP_READ: 1846 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1847 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1848 break; 1849 case E1000_MDIC_OP_WRITE: 1850 e82545_write_mdi(sc, reg_addr, phy_addr, 1851 value & E82545_MDIC_DATA_MASK); 1852 break; 1853 default: 1854 DPRINTF("Unknown MDIC op: 0x%x", value); 1855 return; 1856 } 1857 /* TODO: barrier? */ 1858 sc->mdi_control |= E1000_MDIC_READY; 1859 if (value & E82545_MDIC_IE) { 1860 // TODO: generate interrupt 1861 } 1862 return; 1863 } 1864 case E1000_MANC: 1865 case E1000_STATUS: 1866 return; 1867 default: 1868 DPRINTF("Unknown write register: 0x%x value:%x", offset, value); 1869 return; 1870 } 1871 } 1872 1873 static uint32_t 1874 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1875 { 1876 uint32_t retval; 1877 int ridx; 1878 1879 if (offset & 0x3) { 1880 DPRINTF("Unaligned register read offset:0x%x", offset); 1881 return 0; 1882 } 1883 1884 DPRINTF("Register read: 0x%x", offset); 1885 1886 switch (offset) { 1887 case E1000_CTRL: 1888 retval = sc->esc_CTRL; 1889 break; 1890 case E1000_STATUS: 1891 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1892 E1000_STATUS_SPEED_1000; 1893 break; 1894 case E1000_FCAL: 1895 retval = sc->esc_FCAL; 1896 break; 1897 case E1000_FCAH: 1898 retval = sc->esc_FCAH; 1899 break; 1900 case E1000_FCT: 1901 retval = sc->esc_FCT; 1902 break; 1903 case E1000_VET: 1904 retval = sc->esc_VET; 1905 break; 1906 case E1000_FCTTV: 1907 retval = sc->esc_FCTTV; 1908 break; 1909 case E1000_LEDCTL: 1910 retval = sc->esc_LEDCTL; 1911 break; 1912 case E1000_PBA: 1913 retval = sc->esc_PBA; 1914 break; 1915 case E1000_ICR: 1916 case E1000_ITR: 1917 case E1000_ICS: 1918 case E1000_IMS: 1919 case E1000_IMC: 1920 retval = e82545_intr_read(sc, offset); 1921 break; 1922 case E1000_RCTL: 1923 retval = sc->esc_RCTL; 1924 break; 1925 case E1000_FCRTL: 1926 retval = sc->esc_FCRTL; 1927 break; 1928 case E1000_FCRTH: 1929 retval = sc->esc_FCRTH; 1930 break; 1931 case E1000_RDBAL(0): 1932 retval = sc->esc_RDBAL; 1933 break; 1934 case E1000_RDBAH(0): 1935 retval = sc->esc_RDBAH; 1936 break; 1937 case E1000_RDLEN(0): 1938 retval = sc->esc_RDLEN; 1939 break; 1940 case E1000_RDH(0): 1941 retval = sc->esc_RDH; 1942 break; 1943 case E1000_RDT(0): 1944 retval = sc->esc_RDT; 1945 break; 1946 case E1000_RDTR: 1947 retval = sc->esc_RDTR; 1948 break; 1949 case E1000_RXDCTL(0): 1950 retval = sc->esc_RXDCTL; 1951 break; 1952 case E1000_RADV: 1953 retval = sc->esc_RADV; 1954 break; 1955 case E1000_RSRPD: 1956 retval = sc->esc_RSRPD; 1957 break; 1958 case E1000_RXCSUM: 1959 retval = sc->esc_RXCSUM; 1960 break; 1961 case E1000_TXCW: 1962 retval = sc->esc_TXCW; 1963 break; 1964 case E1000_TCTL: 1965 retval = sc->esc_TCTL; 1966 break; 1967 case E1000_TIPG: 1968 retval = sc->esc_TIPG; 1969 break; 1970 case E1000_AIT: 1971 retval = sc->esc_AIT; 1972 break; 1973 case E1000_TDBAL(0): 1974 retval = sc->esc_TDBAL; 1975 break; 1976 case E1000_TDBAH(0): 1977 retval = sc->esc_TDBAH; 1978 break; 1979 case E1000_TDLEN(0): 1980 retval = sc->esc_TDLEN; 1981 break; 1982 case E1000_TDH(0): 1983 retval = sc->esc_TDH; 1984 break; 1985 case E1000_TDT(0): 1986 retval = sc->esc_TDT; 1987 break; 1988 case E1000_TIDV: 1989 retval = sc->esc_TIDV; 1990 break; 1991 case E1000_TXDCTL(0): 1992 retval = sc->esc_TXDCTL; 1993 break; 1994 case E1000_TADV: 1995 retval = sc->esc_TADV; 1996 break; 1997 case E1000_RAL(0) ... E1000_RAH(15): 1998 /* convert to u32 offset */ 1999 ridx = (offset - E1000_RAL(0)) >> 2; 2000 retval = e82545_read_ra(sc, ridx); 2001 break; 2002 case E1000_MTA ... (E1000_MTA + (127*4)): 2003 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 2004 break; 2005 case E1000_VFTA ... (E1000_VFTA + (127*4)): 2006 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 2007 break; 2008 case E1000_EECD: 2009 //DPRINTF("EECD read %x", sc->eeprom_control); 2010 retval = sc->eeprom_control; 2011 break; 2012 case E1000_MDIC: 2013 retval = sc->mdi_control; 2014 break; 2015 case E1000_MANC: 2016 retval = 0; 2017 break; 2018 /* stats that we emulate. */ 2019 case E1000_MPC: 2020 retval = sc->missed_pkt_count; 2021 break; 2022 case E1000_PRC64: 2023 retval = sc->pkt_rx_by_size[0]; 2024 break; 2025 case E1000_PRC127: 2026 retval = sc->pkt_rx_by_size[1]; 2027 break; 2028 case E1000_PRC255: 2029 retval = sc->pkt_rx_by_size[2]; 2030 break; 2031 case E1000_PRC511: 2032 retval = sc->pkt_rx_by_size[3]; 2033 break; 2034 case E1000_PRC1023: 2035 retval = sc->pkt_rx_by_size[4]; 2036 break; 2037 case E1000_PRC1522: 2038 retval = sc->pkt_rx_by_size[5]; 2039 break; 2040 case E1000_GPRC: 2041 retval = sc->good_pkt_rx_count; 2042 break; 2043 case E1000_BPRC: 2044 retval = sc->bcast_pkt_rx_count; 2045 break; 2046 case E1000_MPRC: 2047 retval = sc->mcast_pkt_rx_count; 2048 break; 2049 case E1000_GPTC: 2050 case E1000_TPT: 2051 retval = sc->good_pkt_tx_count; 2052 break; 2053 case E1000_GORCL: 2054 retval = (uint32_t)sc->good_octets_rx; 2055 break; 2056 case E1000_GORCH: 2057 retval = (uint32_t)(sc->good_octets_rx >> 32); 2058 break; 2059 case E1000_TOTL: 2060 case E1000_GOTCL: 2061 retval = (uint32_t)sc->good_octets_tx; 2062 break; 2063 case E1000_TOTH: 2064 case E1000_GOTCH: 2065 retval = (uint32_t)(sc->good_octets_tx >> 32); 2066 break; 2067 case E1000_ROC: 2068 retval = sc->oversize_rx_count; 2069 break; 2070 case E1000_TORL: 2071 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 2072 break; 2073 case E1000_TORH: 2074 retval = (uint32_t)((sc->good_octets_rx + 2075 sc->missed_octets) >> 32); 2076 break; 2077 case E1000_TPR: 2078 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 2079 sc->oversize_rx_count; 2080 break; 2081 case E1000_PTC64: 2082 retval = sc->pkt_tx_by_size[0]; 2083 break; 2084 case E1000_PTC127: 2085 retval = sc->pkt_tx_by_size[1]; 2086 break; 2087 case E1000_PTC255: 2088 retval = sc->pkt_tx_by_size[2]; 2089 break; 2090 case E1000_PTC511: 2091 retval = sc->pkt_tx_by_size[3]; 2092 break; 2093 case E1000_PTC1023: 2094 retval = sc->pkt_tx_by_size[4]; 2095 break; 2096 case E1000_PTC1522: 2097 retval = sc->pkt_tx_by_size[5]; 2098 break; 2099 case E1000_MPTC: 2100 retval = sc->mcast_pkt_tx_count; 2101 break; 2102 case E1000_BPTC: 2103 retval = sc->bcast_pkt_tx_count; 2104 break; 2105 case E1000_TSCTC: 2106 retval = sc->tso_tx_count; 2107 break; 2108 /* stats that are always 0. */ 2109 case E1000_CRCERRS: 2110 case E1000_ALGNERRC: 2111 case E1000_SYMERRS: 2112 case E1000_RXERRC: 2113 case E1000_SCC: 2114 case E1000_ECOL: 2115 case E1000_MCC: 2116 case E1000_LATECOL: 2117 case E1000_COLC: 2118 case E1000_DC: 2119 case E1000_TNCRS: 2120 case E1000_SEC: 2121 case E1000_CEXTERR: 2122 case E1000_RLEC: 2123 case E1000_XONRXC: 2124 case E1000_XONTXC: 2125 case E1000_XOFFRXC: 2126 case E1000_XOFFTXC: 2127 case E1000_FCRUC: 2128 case E1000_RNBC: 2129 case E1000_RUC: 2130 case E1000_RFC: 2131 case E1000_RJC: 2132 case E1000_MGTPRC: 2133 case E1000_MGTPDC: 2134 case E1000_MGTPTC: 2135 case E1000_TSCTFC: 2136 retval = 0; 2137 break; 2138 default: 2139 DPRINTF("Unknown read register: 0x%x", offset); 2140 retval = 0; 2141 break; 2142 } 2143 2144 return (retval); 2145 } 2146 2147 static void 2148 e82545_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2149 uint64_t value) 2150 { 2151 struct e82545_softc *sc; 2152 2153 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size); 2154 2155 sc = pi->pi_arg; 2156 2157 pthread_mutex_lock(&sc->esc_mtx); 2158 2159 switch (baridx) { 2160 case E82545_BAR_IO: 2161 switch (offset) { 2162 case E82545_IOADDR: 2163 if (size != 4) { 2164 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value); 2165 } else 2166 sc->io_addr = (uint32_t)value; 2167 break; 2168 case E82545_IODATA: 2169 if (size != 4) { 2170 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value); 2171 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2172 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value); 2173 } else 2174 e82545_write_register(sc, sc->io_addr, 2175 (uint32_t)value); 2176 break; 2177 default: 2178 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size); 2179 break; 2180 } 2181 break; 2182 case E82545_BAR_REGISTER: 2183 if (size != 4) { 2184 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value); 2185 } else 2186 e82545_write_register(sc, (uint32_t)offset, 2187 (uint32_t)value); 2188 break; 2189 default: 2190 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d", 2191 baridx, offset, value, size); 2192 } 2193 2194 pthread_mutex_unlock(&sc->esc_mtx); 2195 } 2196 2197 static uint64_t 2198 e82545_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2199 { 2200 struct e82545_softc *sc; 2201 uint64_t retval; 2202 2203 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size); 2204 sc = pi->pi_arg; 2205 retval = 0; 2206 2207 pthread_mutex_lock(&sc->esc_mtx); 2208 2209 switch (baridx) { 2210 case E82545_BAR_IO: 2211 switch (offset) { 2212 case E82545_IOADDR: 2213 if (size != 4) { 2214 DPRINTF("Wrong io addr read sz:%d", size); 2215 } else 2216 retval = sc->io_addr; 2217 break; 2218 case E82545_IODATA: 2219 if (size != 4) { 2220 DPRINTF("Wrong io data read sz:%d", size); 2221 } 2222 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2223 DPRINTF("Non-register io read addr:0x%x", 2224 sc->io_addr); 2225 } else 2226 retval = e82545_read_register(sc, sc->io_addr); 2227 break; 2228 default: 2229 DPRINTF("Unknown io bar read offset:0x%lx size:%d", 2230 offset, size); 2231 break; 2232 } 2233 break; 2234 case E82545_BAR_REGISTER: 2235 if (size != 4) { 2236 DPRINTF("Wrong register read size:%d offset:0x%lx", 2237 size, offset); 2238 } else 2239 retval = e82545_read_register(sc, (uint32_t)offset); 2240 break; 2241 default: 2242 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d", 2243 baridx, offset, size); 2244 break; 2245 } 2246 2247 pthread_mutex_unlock(&sc->esc_mtx); 2248 2249 return (retval); 2250 } 2251 2252 static void 2253 e82545_reset(struct e82545_softc *sc, int drvr) 2254 { 2255 int i; 2256 2257 e82545_rx_disable(sc); 2258 e82545_tx_disable(sc); 2259 2260 /* clear outstanding interrupts */ 2261 if (sc->esc_irq_asserted) 2262 pci_lintr_deassert(sc->esc_pi); 2263 2264 /* misc */ 2265 if (!drvr) { 2266 sc->esc_FCAL = 0; 2267 sc->esc_FCAH = 0; 2268 sc->esc_FCT = 0; 2269 sc->esc_VET = 0; 2270 sc->esc_FCTTV = 0; 2271 } 2272 sc->esc_LEDCTL = 0x07061302; 2273 sc->esc_PBA = 0x00100030; 2274 2275 /* start nvm in opcode mode. */ 2276 sc->nvm_opaddr = 0; 2277 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2278 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2279 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2280 e82545_init_eeprom(sc); 2281 2282 /* interrupt */ 2283 sc->esc_ICR = 0; 2284 sc->esc_ITR = 250; 2285 sc->esc_ICS = 0; 2286 sc->esc_IMS = 0; 2287 sc->esc_IMC = 0; 2288 2289 /* L2 filters */ 2290 if (!drvr) { 2291 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2292 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2293 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2294 2295 /* XXX not necessary on 82545 ?? */ 2296 sc->esc_uni[0].eu_valid = 1; 2297 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2298 ETHER_ADDR_LEN); 2299 } else { 2300 /* Clear RAH valid bits */ 2301 for (i = 0; i < 16; i++) 2302 sc->esc_uni[i].eu_valid = 0; 2303 } 2304 2305 /* receive */ 2306 if (!drvr) { 2307 sc->esc_RDBAL = 0; 2308 sc->esc_RDBAH = 0; 2309 } 2310 sc->esc_RCTL = 0; 2311 sc->esc_FCRTL = 0; 2312 sc->esc_FCRTH = 0; 2313 sc->esc_RDLEN = 0; 2314 sc->esc_RDH = 0; 2315 sc->esc_RDT = 0; 2316 sc->esc_RDTR = 0; 2317 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2318 sc->esc_RADV = 0; 2319 sc->esc_RXCSUM = 0; 2320 2321 /* transmit */ 2322 if (!drvr) { 2323 sc->esc_TDBAL = 0; 2324 sc->esc_TDBAH = 0; 2325 sc->esc_TIPG = 0; 2326 sc->esc_AIT = 0; 2327 sc->esc_TIDV = 0; 2328 sc->esc_TADV = 0; 2329 } 2330 sc->esc_tdba = 0; 2331 sc->esc_txdesc = NULL; 2332 sc->esc_TXCW = 0; 2333 sc->esc_TCTL = 0; 2334 sc->esc_TDLEN = 0; 2335 sc->esc_TDT = 0; 2336 sc->esc_TDHr = sc->esc_TDH = 0; 2337 sc->esc_TXDCTL = 0; 2338 } 2339 2340 static int 2341 e82545_init(struct pci_devinst *pi, nvlist_t *nvl) 2342 { 2343 char nstr[80]; 2344 struct e82545_softc *sc; 2345 const char *mac; 2346 int err; 2347 2348 /* Setup our softc */ 2349 sc = calloc(1, sizeof(*sc)); 2350 2351 pi->pi_arg = sc; 2352 sc->esc_pi = pi; 2353 sc->esc_ctx = pi->pi_vmctx; 2354 2355 pthread_mutex_init(&sc->esc_mtx, NULL); 2356 pthread_cond_init(&sc->esc_rx_cond, NULL); 2357 pthread_cond_init(&sc->esc_tx_cond, NULL); 2358 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2359 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2360 pi->pi_func); 2361 pthread_set_name_np(sc->esc_tx_tid, nstr); 2362 2363 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2364 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2365 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2366 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2367 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2368 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2369 2370 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2371 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2372 2373 /* TODO: this card also supports msi, but the freebsd driver for it 2374 * does not, so I have not implemented it. */ 2375 pci_lintr_request(pi); 2376 2377 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2378 E82545_BAR_REGISTER_LEN); 2379 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2380 E82545_BAR_FLASH_LEN); 2381 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2382 E82545_BAR_IO_LEN); 2383 2384 mac = get_config_value_node(nvl, "mac"); 2385 if (mac != NULL) { 2386 err = net_parsemac(mac, sc->esc_mac.octet); 2387 if (err) { 2388 free(sc); 2389 return (err); 2390 } 2391 } else 2392 net_genmac(pi, sc->esc_mac.octet); 2393 2394 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc); 2395 if (err) { 2396 free(sc); 2397 return (err); 2398 } 2399 2400 #ifndef __FreeBSD__ 2401 size_t buflen = sizeof (sc->esc_mac.octet); 2402 2403 err = netbe_get_mac(sc->esc_be, sc->esc_mac.octet, &buflen); 2404 if (err != 0) { 2405 free(sc); 2406 return (err); 2407 } 2408 #endif 2409 2410 netbe_rx_enable(sc->esc_be); 2411 2412 /* H/w initiated reset */ 2413 e82545_reset(sc, 0); 2414 2415 return (0); 2416 } 2417 2418 static const struct pci_devemu pci_de_e82545 = { 2419 .pe_emu = "e1000", 2420 .pe_init = e82545_init, 2421 .pe_legacy_config = netbe_legacy_config, 2422 .pe_barwrite = e82545_write, 2423 .pe_barread = e82545_read, 2424 }; 2425 PCI_EMUL_SET(pci_de_e82545); 2426