1 /*- 2 * Copyright (c) 2010 Advanced Computing Technologies LLC 3 * Written by: John H. Baldwin <jhb@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This driver provides a psuedo-bus to enumerate the PCI buses 30 * present on a sytem using a QPI chipset. It creates a qpi0 bus that 31 * is a child of nexus0 and then creates two Host-PCI bridges as a 32 * child of that. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/systm.h> 45 46 #include <machine/cputypes.h> 47 #include <machine/md_var.h> 48 #include <machine/pci_cfgreg.h> 49 #include <machine/specialreg.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcib_private.h> 54 #include "pcib_if.h" 55 56 struct qpi_device { 57 int qd_pcibus; 58 }; 59 60 static MALLOC_DEFINE(M_QPI, "qpidrv", "qpi system device"); 61 62 static void 63 qpi_identify(driver_t *driver, device_t parent) 64 { 65 66 /* Check CPUID to ensure this is an i7 CPU of some sort. */ 67 if (!(cpu_vendor_id == CPU_VENDOR_INTEL && 68 CPUID_TO_FAMILY(cpu_id) == 0x6 && 69 (CPUID_TO_MODEL(cpu_id) == 0x1a || CPUID_TO_MODEL(cpu_id) == 0x2c))) 70 return; 71 72 /* PCI config register access is required. */ 73 if (pci_cfgregopen() == 0) 74 return; 75 76 /* Add a qpi bus device. */ 77 if (BUS_ADD_CHILD(parent, 20, "qpi", -1) == NULL) 78 panic("Failed to add qpi bus"); 79 } 80 81 static int 82 qpi_probe(device_t dev) 83 { 84 85 device_set_desc(dev, "QPI system bus"); 86 return (BUS_PROBE_SPECIFIC); 87 } 88 89 /* 90 * Look for a PCI bus with the specified bus address. If one is found, 91 * add a pcib device and return 0. Otherwise, return an error code. 92 */ 93 static int 94 qpi_probe_pcib(device_t dev, int bus) 95 { 96 struct qpi_device *qdev; 97 device_t child; 98 uint32_t devid; 99 100 /* 101 * If a PCI bus already exists for this bus number, then 102 * fail. 103 */ 104 if (pci_find_bsf(bus, 0, 0) != NULL) 105 return (EEXIST); 106 107 /* 108 * Attempt to read the device id for device 0, function 0 on 109 * the bus. A value of 0xffffffff means that the bus is not 110 * present. 111 */ 112 devid = pci_cfgregread(bus, 0, 0, PCIR_DEVVENDOR, 4); 113 if (devid == 0xffffffff) 114 return (ENOENT); 115 116 if ((devid & 0xffff) != 0x8086) { 117 device_printf(dev, 118 "Device at pci%d.0.0 has non-Intel vendor 0x%x\n", bus, 119 devid & 0xffff); 120 return (ENXIO); 121 } 122 123 child = BUS_ADD_CHILD(dev, 0, "pcib", -1); 124 if (child == NULL) 125 panic("%s: failed to add pci bus %d", device_get_nameunit(dev), 126 bus); 127 qdev = malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK); 128 qdev->qd_pcibus = bus; 129 device_set_ivars(child, qdev); 130 return (0); 131 } 132 133 static int 134 qpi_attach(device_t dev) 135 { 136 int bus; 137 138 /* 139 * Each processor socket has a dedicated PCI bus counting down from 140 * 255. We keep probing buses until one fails. 141 */ 142 for (bus = 255;; bus--) 143 if (qpi_probe_pcib(dev, bus) != 0) 144 break; 145 146 return (bus_generic_attach(dev)); 147 } 148 149 static int 150 qpi_print_child(device_t bus, device_t child) 151 { 152 struct qpi_device *qdev; 153 int retval = 0; 154 155 qdev = device_get_ivars(child); 156 retval += bus_print_child_header(bus, child); 157 if (qdev->qd_pcibus != -1) 158 retval += printf(" pcibus %d", qdev->qd_pcibus); 159 retval += bus_print_child_footer(bus, child); 160 161 return (retval); 162 } 163 164 static int 165 qpi_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 166 { 167 struct qpi_device *qdev; 168 169 qdev = device_get_ivars(child); 170 switch (which) { 171 case PCIB_IVAR_BUS: 172 *result = qdev->qd_pcibus; 173 break; 174 default: 175 return (ENOENT); 176 } 177 return (0); 178 } 179 180 static device_method_t qpi_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_identify, qpi_identify), 183 DEVMETHOD(device_probe, qpi_probe), 184 DEVMETHOD(device_attach, qpi_attach), 185 DEVMETHOD(device_shutdown, bus_generic_shutdown), 186 DEVMETHOD(device_suspend, bus_generic_suspend), 187 DEVMETHOD(device_resume, bus_generic_resume), 188 189 /* Bus interface */ 190 DEVMETHOD(bus_print_child, qpi_print_child), 191 DEVMETHOD(bus_add_child, bus_generic_add_child), 192 DEVMETHOD(bus_read_ivar, qpi_read_ivar), 193 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 194 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 195 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 196 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 197 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 198 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 199 200 { 0, 0 } 201 }; 202 203 static devclass_t qpi_devclass; 204 205 DEFINE_CLASS_0(qpi, qpi_driver, qpi_methods, 0); 206 DRIVER_MODULE(qpi, nexus, qpi_driver, qpi_devclass, 0, 0); 207 208 static int 209 qpi_pcib_probe(device_t dev) 210 { 211 212 device_set_desc(dev, "QPI Host-PCI bridge"); 213 return (BUS_PROBE_SPECIFIC); 214 } 215 216 static int 217 qpi_pcib_attach(device_t dev) 218 { 219 220 device_add_child(dev, "pci", pcib_get_bus(dev)); 221 return (bus_generic_attach(dev)); 222 } 223 224 static int 225 qpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 226 { 227 228 switch (which) { 229 case PCIB_IVAR_DOMAIN: 230 *result = 0; 231 return (0); 232 case PCIB_IVAR_BUS: 233 *result = pcib_get_bus(dev); 234 return (0); 235 default: 236 return (ENOENT); 237 } 238 } 239 240 static uint32_t 241 qpi_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 242 u_int reg, int bytes) 243 { 244 245 return (pci_cfgregread(bus, slot, func, reg, bytes)); 246 } 247 248 static void 249 qpi_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 250 u_int reg, uint32_t data, int bytes) 251 { 252 253 pci_cfgregwrite(bus, slot, func, reg, data, bytes); 254 } 255 256 static int 257 qpi_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 258 int *irqs) 259 { 260 device_t bus; 261 262 bus = device_get_parent(pcib); 263 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 264 irqs)); 265 } 266 267 static int 268 qpi_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 269 { 270 device_t bus; 271 272 bus = device_get_parent(pcib); 273 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 274 } 275 276 static int 277 qpi_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 278 uint32_t *data) 279 { 280 device_t bus; 281 282 bus = device_get_parent(pcib); 283 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data)); 284 } 285 286 static device_method_t qpi_pcib_methods[] = { 287 /* Device interface */ 288 DEVMETHOD(device_probe, qpi_pcib_probe), 289 DEVMETHOD(device_attach, qpi_pcib_attach), 290 DEVMETHOD(device_shutdown, bus_generic_shutdown), 291 DEVMETHOD(device_suspend, bus_generic_suspend), 292 DEVMETHOD(device_resume, bus_generic_resume), 293 294 /* Bus interface */ 295 DEVMETHOD(bus_read_ivar, qpi_pcib_read_ivar), 296 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 297 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 298 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 299 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 300 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 301 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 302 303 /* pcib interface */ 304 DEVMETHOD(pcib_maxslots, pcib_maxslots), 305 DEVMETHOD(pcib_read_config, qpi_pcib_read_config), 306 DEVMETHOD(pcib_write_config, qpi_pcib_write_config), 307 DEVMETHOD(pcib_alloc_msi, qpi_pcib_alloc_msi), 308 DEVMETHOD(pcib_release_msi, pcib_release_msi), 309 DEVMETHOD(pcib_alloc_msix, qpi_pcib_alloc_msix), 310 DEVMETHOD(pcib_release_msix, pcib_release_msix), 311 DEVMETHOD(pcib_map_msi, qpi_pcib_map_msi), 312 313 DEVMETHOD_END 314 }; 315 316 static devclass_t qpi_pcib_devclass; 317 318 DEFINE_CLASS_0(pcib, qpi_pcib_driver, qpi_pcib_methods, 0); 319 DRIVER_MODULE(pcib, qpi, qpi_pcib_driver, qpi_pcib_devclass, 0, 0); 320