1 /*- 2 * Copyright (c) 2010 Advanced Computing Technologies LLC 3 * Written by: John H. Baldwin <jhb@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This driver provides a psuedo-bus to enumerate the PCI buses 30 * present on a sytem using a QPI chipset. It creates a qpi0 bus that 31 * is a child of nexus0 and then creates two Host-PCI bridges as a 32 * child of that. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/systm.h> 44 45 #include <machine/cputypes.h> 46 #include <machine/md_var.h> 47 #include <machine/pci_cfgreg.h> 48 #include <machine/specialreg.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcib_private.h> 53 #include "pcib_if.h" 54 55 struct qpi_device { 56 int qd_pcibus; 57 }; 58 59 static MALLOC_DEFINE(M_QPI, "qpidrv", "qpi system device"); 60 61 static void 62 qpi_identify(driver_t *driver, device_t parent) 63 { 64 65 /* Check CPUID to ensure this is an i7 CPU of some sort. */ 66 if (!(cpu_vendor_id == CPU_VENDOR_INTEL && 67 CPUID_TO_FAMILY(cpu_id) == 0x6 && 68 (CPUID_TO_MODEL(cpu_id) == 0x1a || CPUID_TO_MODEL(cpu_id) == 0x2c))) 69 return; 70 71 /* PCI config register access is required. */ 72 if (pci_cfgregopen() == 0) 73 return; 74 75 /* Add a qpi bus device. */ 76 if (BUS_ADD_CHILD(parent, 20, "qpi", -1) == NULL) 77 panic("Failed to add qpi bus"); 78 } 79 80 static int 81 qpi_probe(device_t dev) 82 { 83 84 device_set_desc(dev, "QPI system bus"); 85 return (BUS_PROBE_SPECIFIC); 86 } 87 88 /* 89 * Look for a PCI bus with the specified bus address. If one is found, 90 * add a pcib device and return 0. Otherwise, return an error code. 91 */ 92 static int 93 qpi_probe_pcib(device_t dev, int bus) 94 { 95 struct qpi_device *qdev; 96 device_t child; 97 uint32_t devid; 98 99 /* 100 * If a PCI bus already exists for this bus number, then 101 * fail. 102 */ 103 if (pci_find_bsf(bus, 0, 0) != NULL) 104 return (EEXIST); 105 106 /* 107 * Attempt to read the device id for device 0, function 0 on 108 * the bus. A value of 0xffffffff means that the bus is not 109 * present. 110 */ 111 devid = pci_cfgregread(bus, 0, 0, PCIR_DEVVENDOR, 4); 112 if (devid == 0xffffffff) 113 return (ENOENT); 114 115 if ((devid & 0xffff) != 0x8086) { 116 device_printf(dev, 117 "Device at pci%d.0.0 has non-Intel vendor 0x%x\n", bus, 118 devid & 0xffff); 119 return (ENXIO); 120 } 121 122 child = BUS_ADD_CHILD(dev, 0, "pcib", -1); 123 if (child == NULL) 124 panic("%s: failed to add pci bus %d", device_get_nameunit(dev), 125 bus); 126 qdev = malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK); 127 qdev->qd_pcibus = bus; 128 device_set_ivars(child, qdev); 129 return (0); 130 } 131 132 static int 133 qpi_attach(device_t dev) 134 { 135 int bus; 136 137 /* 138 * Each processor socket has a dedicated PCI bus counting down from 139 * 255. We keep probing buses until one fails. 140 */ 141 for (bus = 255;; bus--) 142 if (qpi_probe_pcib(dev, bus) != 0) 143 break; 144 145 return (bus_generic_attach(dev)); 146 } 147 148 static int 149 qpi_print_child(device_t bus, device_t child) 150 { 151 struct qpi_device *qdev; 152 int retval = 0; 153 154 qdev = device_get_ivars(child); 155 retval += bus_print_child_header(bus, child); 156 if (qdev->qd_pcibus != -1) 157 retval += printf(" pcibus %d", qdev->qd_pcibus); 158 retval += bus_print_child_footer(bus, child); 159 160 return (retval); 161 } 162 163 static int 164 qpi_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 165 { 166 struct qpi_device *qdev; 167 168 qdev = device_get_ivars(child); 169 switch (which) { 170 case PCIB_IVAR_BUS: 171 *result = qdev->qd_pcibus; 172 break; 173 default: 174 return (ENOENT); 175 } 176 return (0); 177 } 178 179 static device_method_t qpi_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_identify, qpi_identify), 182 DEVMETHOD(device_probe, qpi_probe), 183 DEVMETHOD(device_attach, qpi_attach), 184 DEVMETHOD(device_shutdown, bus_generic_shutdown), 185 DEVMETHOD(device_suspend, bus_generic_suspend), 186 DEVMETHOD(device_resume, bus_generic_resume), 187 188 /* Bus interface */ 189 DEVMETHOD(bus_print_child, qpi_print_child), 190 DEVMETHOD(bus_add_child, bus_generic_add_child), 191 DEVMETHOD(bus_read_ivar, qpi_read_ivar), 192 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 193 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 194 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 195 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 196 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 197 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 198 199 { 0, 0 } 200 }; 201 202 static devclass_t qpi_devclass; 203 204 DEFINE_CLASS_0(qpi, qpi_driver, qpi_methods, 0); 205 DRIVER_MODULE(qpi, nexus, qpi_driver, qpi_devclass, 0, 0); 206 207 static int 208 qpi_pcib_probe(device_t dev) 209 { 210 211 device_set_desc(dev, "QPI Host-PCI bridge"); 212 return (BUS_PROBE_SPECIFIC); 213 } 214 215 static int 216 qpi_pcib_attach(device_t dev) 217 { 218 219 device_add_child(dev, "pci", pcib_get_bus(dev)); 220 return (bus_generic_attach(dev)); 221 } 222 223 static int 224 qpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 225 { 226 227 switch (which) { 228 case PCIB_IVAR_DOMAIN: 229 *result = 0; 230 return (0); 231 case PCIB_IVAR_BUS: 232 *result = pcib_get_bus(dev); 233 return (0); 234 default: 235 return (ENOENT); 236 } 237 } 238 239 static uint32_t 240 qpi_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 241 u_int reg, int bytes) 242 { 243 244 return (pci_cfgregread(bus, slot, func, reg, bytes)); 245 } 246 247 static void 248 qpi_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 249 u_int reg, uint32_t data, int bytes) 250 { 251 252 pci_cfgregwrite(bus, slot, func, reg, data, bytes); 253 } 254 255 static int 256 qpi_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 257 int *irqs) 258 { 259 device_t bus; 260 261 bus = device_get_parent(pcib); 262 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 263 irqs)); 264 } 265 266 static int 267 qpi_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 268 { 269 device_t bus; 270 271 bus = device_get_parent(pcib); 272 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 273 } 274 275 static int 276 qpi_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 277 uint32_t *data) 278 { 279 device_t bus; 280 281 bus = device_get_parent(pcib); 282 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data)); 283 } 284 285 static device_method_t qpi_pcib_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, qpi_pcib_probe), 288 DEVMETHOD(device_attach, qpi_pcib_attach), 289 DEVMETHOD(device_shutdown, bus_generic_shutdown), 290 DEVMETHOD(device_suspend, bus_generic_suspend), 291 DEVMETHOD(device_resume, bus_generic_resume), 292 293 /* Bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_read_ivar, qpi_pcib_read_ivar), 296 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 297 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 298 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 299 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 300 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 301 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 302 303 /* pcib interface */ 304 DEVMETHOD(pcib_maxslots, pcib_maxslots), 305 DEVMETHOD(pcib_read_config, qpi_pcib_read_config), 306 DEVMETHOD(pcib_write_config, qpi_pcib_write_config), 307 DEVMETHOD(pcib_alloc_msi, qpi_pcib_alloc_msi), 308 DEVMETHOD(pcib_release_msi, pcib_release_msi), 309 DEVMETHOD(pcib_alloc_msix, qpi_pcib_alloc_msix), 310 DEVMETHOD(pcib_release_msix, pcib_release_msix), 311 DEVMETHOD(pcib_map_msi, qpi_pcib_map_msi), 312 313 {0, 0} 314 }; 315 316 static devclass_t qpi_pcib_devclass; 317 318 DEFINE_CLASS_0(pcib, qpi_pcib_driver, qpi_pcib_methods, 0); 319 DRIVER_MODULE(pcib, qpi, qpi_pcib_driver, qpi_pcib_devclass, 0, 0); 320